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| document no. u19291ej1v0ud00 (1st edition) date published july 2008 ns printed in japan 2008 pd78f1000 pd78f1001 pd78f1002 pd78f1003 pd78f1004 pd78f1005 pd78f1006 pd78f1007 pd78f1008 pd78f1009 78k0r/kx3-l 16-bit single-chip microcontrollers preliminary user?s manual
preliminary user?s manual u19291ej1v0ud 2 [memo] preliminary user?s manual u19291ej1v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 preliminary user?s manual u19291ej1v0ud 4 windows and windows nt are registered trademarks or trademarks of microsoft co rporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. eeprom is a trademark of nec electronics corporation. superflash is a registered trademark of silicon storage t echnology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from silicon storage technology, inc. the information contained in this document is being issued in advance of the production cycle for the product. the parameters for the product may change before final production or nec electronics corporation, at its own discretion, may withdraw the product prior to its production. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of an nec electronics products depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. ? ? ? ? ? ? ? m5d 02. 11-1 the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": preliminary user?s manual u19291ej1v0ud 5 introduction readers this manual is intended for user engineer s who wish to understand the functions of the 78k0r/kx3-l and design and develop app lication systems and programs for these devices. the target products are as follows. ? 78k0r/kc3-l: pd78f1000, 78f1001, 78f1002, 78f1003 ? 78k0r/kd3-l: pd78f1004, 78f1005, 78f1006 ? 78k0r/ke3-l: pd78f1007, 78f1008, 78f1009 purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the 78k0r/kx3-l manual is separated into tw o parts: this manual and the instructions edition (common to the 78k0r microcontroller). 78k0r/kx3-l user?s manual (this manual) 78k0r microcontroller user?s manual instructions ? pin functions ? internal block functions ? interrupts ? other on-chip peripheral functions ? electrical specifications (target) ? cpu functions ? instruction set ? explanation of each instruction how to read this manual it is assumed that the readers of this ma nual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? to gain a general understanding of functions: read this manual in the order of the contents . ? how to interpret the register format: for a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the ra78k0r, and is defined as an sfr variable using the #pragma sfr directive in the cc78k0r. ? to know details of the 78k0r microcontroller instructions: refer to the separate document 78k0r microcontroller instructions user?s manual (u17792e) . preliminary user?s manual u19291ej1v0ud 6 conventions data significance: higher digits on the left and lower digits on the right active low representations: (overscore over pin and signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representations: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this pu blication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. 78k0r/kx3-l user?s manual this manual 78k0r microcontroller instructions user?s manual u17792e documents related to development tools (software) (user?s manuals) document name document no. operation u18549e cc78k0r ver. 2.00 c compiler language u18548e operation u18547e ra78k0r ver. 1.20 assembler package language u18546e sm+ system simulator operation u18010e pm+ ver. 6.30 u18416e id78k0r-qb ver. 3.20 integrated debugger operation u17839e documents related to development tools (hardware) (user?s manuals) document name document no. qb-mini2 on-chip debug emulator with programming function u18371e qb-78k0rix3 in-circuit emulator to be prepared documents related to fl ash memory programming document name document no. pg-fp4 flash memory programmer user?s manual u15260e pg-fp5 flash memory programmer user?s manual u18865e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing. preliminary user?s manual u19291ej1v0ud 7 other documents document name document no. semiconductor selection guide ? products and packages ? x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device m ount manual? website (h ttp://www.necel.com/pkg/en/mount/index.html). caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing. preliminary user?s manual u19291ej1v0ud 8 contents chapter 1 outline ........................................................................................................... ................. 18 1.1 features.................................................................................................................. ....................... 18 1.2 applications .............................................................................................................. .................... 19 1.3 ordering information...................................................................................................... .............. 19 1.4 pin configuration (top view) .............................................................................................. ........ 20 1.4.1 78k 0r/kc3-l ............................................................................................................. ...................... 20 1.4.2 78k 0r/kd3-l ............................................................................................................. ...................... 22 1.4.3 78k 0r/ke3-l ............................................................................................................. ...................... 23 1.5 pin identification........................................................................................................ ................... 25 1.6 block diagram ............................................................................................................. ................. 26 1.6.1 78k 0r/kc3-l ............................................................................................................. ...................... 26 1.6.2 78k 0r/kd3-l ............................................................................................................. ...................... 28 1.6.3 78k 0r/ke3-l ............................................................................................................. ...................... 29 1.7 outline of functions...................................................................................................... ............... 30 chapter 2 pin functions .................................................................................................... ........... 32 2.1 pin function list ......................................................................................................... ................. 32 2.1.1 78k 0r/kc3-l ............................................................................................................. ...................... 33 2.1.2 78k 0r/kd3-l ............................................................................................................. ...................... 38 2.1.3 78k 0r/ke3-l ............................................................................................................. ...................... 43 2.2 description of pin functions .............................................................................................. ........ 48 2.2.1 p00, p01 (por t 0)....................................................................................................... ....................... 48 2.2.2 p10 to p17 (por t 1) ..................................................................................................... ...................... 49 2.2.3 p20 to p27 (por t 2) ..................................................................................................... ...................... 50 2.2.4 p30 to p33 (por t 3) ..................................................................................................... ...................... 50 2.2.5 p40 to p43 (por t 4) ..................................................................................................... ...................... 52 2.2.6 p50 to p53 (por t 5) ..................................................................................................... ...................... 53 2.2.7 p60 and p61 (por t 6) .................................................................................................... .................... 54 2.2.8 p70 to p77 (por t 7) ..................................................................................................... ...................... 55 2.2.9 p80 to p83 (por t 8) ..................................................................................................... ...................... 56 2.2.10 p120 to p124 ( port 12) ................................................................................................. .................. 57 2.2.11 p140, p141 (por t 14) ................................................................................................... ................... 58 2.2.12 p150 to p153 ( port 15) ................................................................................................. .................. 58 2.2.13 av ref , av ss , v dd , ev dd , v ss , ev ss ................................................................................................ 59 2.2.14 reset .................................................................................................................. ......................... 60 2.2.15 regc................................................................................................................... .......................... 60 2.2.16 flmd0 .................................................................................................................. ......................... 60 preliminary user?s manual u19291ej1v0ud 9 2.3 pin i/o circuits and recommend ed connection of unused pins........ ................................... 61 chapter 3 cpu architecture ................................................................................................. ..... 67 3.1 memory space .............................................................................................................. ................ 67 3.1.1 internal progr am memory space ........................................................................................... ............73 3.1.2 mi rror ar ea ............................................................................................................. ...........................75 3.1.3 internal dat a memory space.............................................................................................. ................76 3.1.4 special function register (sfr) area .................................................................................... .............77 3.1.5 extended special function register (2nd sfr: 2nd special func tion registe r) area ........................77 3.1.6 data me mory addr essing .................................................................................................. ................78 3.2 processor registers ....................................................................................................... ............. 82 3.2.1 contro l regist ers....................................................................................................... .........................82 3.2.2 general-pur pose registers ............................................................................................... .................84 3.2.3 es and cs regist ers ..................................................................................................... ....................86 3.2.4 special functi on register s (sfrs)....................................................................................... ...............87 3.2.5 extended specia l function registers (2nd sfrs: 2nd special function register s)............................92 3.3 instruction address addressing . ........................................................................................... .... 97 3.3.1 relati ve addre ssing ..................................................................................................... .....................97 3.3.2 immedi ate addres sing.................................................................................................... ...................97 3.3.3 table indi rect addr essing ............................................................................................... ...................98 3.3.4 register di rect addr essing .............................................................................................. ..................99 3.4 addressing for processing data a ddresses........................................................................... 100 3.4.1 impli ed addre ssing...................................................................................................... ....................100 3.4.2 regist er addre ssing ..................................................................................................... ...................100 3.4.3 direct addre ssing ....................................................................................................... .....................101 3.4.4 short di rect addr essing ................................................................................................. ..................102 3.4.5 sfr addressi ng .......................................................................................................... ....................103 3.4.6 register i ndirect addr essi ng............................................................................................ ................104 3.4.7 based addre ssing ........................................................................................................ ...................105 3.4.8 based in dexed addr essing................................................................................................ ..............108 3.4.9 stack addre ssing ........................................................................................................ ....................109 chapter 4 port functions ................................................................................................... ...... 110 4.1 port functions ............................................................................................................ ................ 110 4.2 port configuration ........................................................................................................ ............. 113 4.2.1 po rt 0 .................................................................................................................. ............................114 4.2.2 po rt 1 .................................................................................................................. ............................116 4.2.3 po rt 2 .................................................................................................................. ............................119 4.2.4 po rt 3 .................................................................................................................. ............................121 4.2.5 po rt 4 .................................................................................................................. ............................125 4.2.6 po rt 5 .................................................................................................................. ............................128 preliminary user?s manual u19291ej1v0ud 10 4.2.7 po rt 6.................................................................................................................. .............................132 4.2.8 po rt 7.................................................................................................................. .............................133 4.2.9 po rt 8.................................................................................................................. .............................138 4.2.10 po rt 12................................................................................................................ ...........................141 4.2.11 po rt 14................................................................................................................ ...........................145 4.2.12 po rt 15................................................................................................................ ...........................147 4.3 registers controlling port function .......................... ............................................................. . 149 4.4 port function operations .................................................................................................. ........ 162 4.4.1 writi ng to i/o port ..................................................................................................... .......................162 4.4.2 reading from i/o port................................................................................................... ...................162 4.4.3 operatio ns on i/o port.................................................................................................. ...................162 4.4.4 connecting to external device with different power potent ial (2.5 v, 3 v)........................................163 4.5 settings of port mode register and output latch when using alternate function........... 165 4.6 cautions on 1-bit manipulation instruction for port register n (p n) .................................... 168 chapter 5 clock generator .................................................................................................. .. 169 5.1 functions of clock genera tor.............................................................................................. ..... 169 5.2 configuration of clock gene rator .......................................................................................... .. 170 5.3 registers controlling clock generator.......................... .......................................................... 1 72 5.4 system clock oscillator ................................................................................................... ......... 186 5.4.1 x1 oscill ator........................................................................................................... ..........................186 5.4.2 xt1 oscilla tor .......................................................................................................... ........................186 5.4.3 internal hi gh-speed os cillator .......................................................................................... ................190 5.4.4 20 mhz internal high-speed os cillat or ................................................................................... ..........190 5.4.5 internal lo w-speed os cillator........................................................................................... .................190 5.4.6 pr escaler ............................................................................................................... ..........................190 5.5 clock generator operation ................................................................................................. ...... 191 5.6 controlling clock......................................................................................................... ............... 197 5.6.1 example of controlli ng high-speed syst em clock.......................................................................... ...197 5.6.2 example of controlling intern al high-speed osc illation clock............................................................ 200 5.6.3 example of cont rolling subsyst em clock.................................................................................. ........202 5.6.4 example of controlling intern al low-speed osci llation clock ............................................................. 204 5.6.5 cpu clock stat us transiti on diagr am..................................................................................... ...........205 5.6.6 condition before changing cpu clock and processi ng after changing cpu cl ock ..........................212 5.6.7 time required for switchover of cpu clock and main system cl ock ................................................214 5.6.8 conditions before clock osc illation is stopp ed .......................................................................... .......215 chapter 6 timer array unit taus......................... ................................................................. 216 6.1 functions of timer array unit taus........................................................................................ 217 6.1.1 functions of eac h channel when it oper ates indepe ndently ............................................................217 6.1.2 functions of each channel when it operates with another channe l .................................................218 preliminary user?s manual u19291ej1v0ud 11 6.1.3 lin-bus supporting function (cha nnel 7 only)............................................................................ ......218 6.2 configuration of timer array unit taus .................. ............................................................... 219 6.3 registers controlling timer array unit ..................... .............................................................. 2 25 6.4 channel output (to0n pin) co ntrol ......................................................................................... 247 6.4.1 to0n pin output ci rcuit config uration ................................................................................... ...........247 6.4.2 to0n pin output setting ................................................................................................. ................248 6.4.3 cautions on cha nnel output operation .................................................................................... ......248 6.4.4 collective mani pulation of to0n bit ..................................................................................... ...........252 6.4.5 timer interrupt and to0n pi n output at oper ation st art ................................................................25 3 6.5 channel input (ti0n pin) cont rol .......................................................................................... .... 254 6.5.1 ti0n edge det ection circuit ............................................................................................. .................254 6.6 basic function of timer array un it taus............................................................................... 255 6.6.1 overview of single-operation func tion and combination-op eration fu nction ....................................255 6.6.2 basic rules of comb ination-operat ion func tion........................................................................... ......255 6.6.3 applicable range of basic rules of combi nation-operation functi on .................................................256 6.7 operation of timer array unit taus as independe nt channel............................................. 257 6.7.1 operation as interv al timer/squar e wave output .......................................................................... ....257 6.7.2 operation as ex ternal event count er ..................................................................................... ..........261 6.7.3 operation as fr equency divider (channel 0 of 78k0r/k d3-l and 78k0r/ ke3-l only) ....................264 6.7.4 operation as input pulse interval measur ement ........................................................................... ...268 6.7.5 operation as in put signal high-/low-le vel width me asurem ent ........................................................ 272 6.8 operation of plural channels of timer array un it taus....................................................... 276 6.8.1 operation as pwm f unction ............................................................................................... .............276 6.8.2 operation as one-s hot pulse output function............................................................................. ......283 6.8.3 operation as mult iple pwm output func tion ............................................................................... .....290 chapter 7 real-time counter ................................................................................................ .. 297 7.1 functions of real-time counter................................ ............................................................ ... 297 7.2 configuration of real-time counter ......................... ............................................................... 297 7.3 registers controlling real-time counter ............................................................................... 299 7.4 real-time counter operation .................................... ........................................................... .... 314 7.4.1 starting operation of real-tim e coun ter ................................................................................. ...........314 7.4.2 shifting to stop m ode after starti ng operat ion.......................................................................... .....315 7.4.3 reading/writi ng real-tim e count er ....................................................................................... ............316 7.4.4 setting alarm of real-tim e count er ...................................................................................... .............318 7.4.5 1 hz output of real-tim e counter........................................................................................ ..............319 7.4.6 32.768 khz output of real-tim e coun ter .................................................................................. .........319 7.4.7 512 hz, 16.384 khz out put of real-t ime c ounter .......................................................................... ....319 7.4.8 example of watch error co rrection of real -time co unter.................................................................. .320 preliminary user?s manual u19291ej1v0ud 12 chapter 8 comparators/programmable gain amplifiers.......................................... 325 8.1 features of comparator and programmable gain am plifier.............................................. 325 8.2 configurations of comparator and programmable gain amplifier ................................... 327 8.3 registers controlling comparators and programma ble gain amplifiers......................... 327 8.4 operations of comparator and programmable gain amplifier.......................................... 333 8.4.1 starting comparator and programmabl e gain amplifie r operat ion .................................................333 8.4.2 stopping comparator and programma ble gain amplifie r operat ion ..............................................338 chapter 9 clock output/buzzer output controller................................................. 339 9.1 functions of clock output/buzze r output controller ................. ........................................... 339 9.2 configuration of clock output /buzzer output controller...................................................... 341 9.3 registers controlling clock ou tput/buzzer output controller ............................................. 341 9.4 operations of clock output/bu zzer output controller ............... ........................................... 343 9.4.1 operation as output pin ................................................................................................. ..................343 chapter 10 watchdog timer .................................................................................................. ... 344 10.1 functions of watchdog timer......................................... ..................................................... ... 344 10.2 configuration of watchdog ti mer .......................................................................................... 345 10.3 register controlling watchdog ti mer.................................................................................... 34 6 10.4 operation of watchdog timer....................................... ....................................................... ... 347 10.4.1 controlling oper ation of wa tchdog ti mer ................................................................................ ........347 10.4.2 setting overflow time of wa tchdog ti mer................................................................................ ........348 10.4.3 setting window open pe riod of watc hdog ti mer ........................................................................... ..349 10.4.4 setting watchdog ti mer interval interrupt .............................................................................. .........350 chapter 11 a/d converter .................................................................................................... ...... 351 11.1 function of a/d converter................................................................................................ ....... 351 11.2 configuration of a/d converter ........................................................................................... ... 352 11.3 registers used in a/d converter.......................................................................................... .. 354 11.4 a/d converter operations ............................................... .................................................. ...... 367 11.4.1 basic operations of a/d c onverter ...................................................................................... ...........367 11.4.2 input voltage and conversion results ................................................................................... ..........369 11.4.3 a/d converte r operati on modes.......................................................................................... ...........370 11.5 how to read a/d converter characteristics tabl e............................................................... 373 11.6 cautions for a/d converter ............................................................................................... ...... 375 chapter 12 serial array unit.............................................................................................. .... 379 12.1 functions of serial array unit........................................................................................... ...... 379 12.1.1 3-wire serial i/o (csi00, csi 01, cs i10) ................................................................................ ........379 12.1.2 uart (u art0, ua rt1).................................................................................................... ............380 preliminary user?s manual u19291ej1v0ud 13 12.1.3 simplified i 2 c (iic 10) .....................................................................................................................3 80 12.2 configuration of serial array unit ........................... ............................................................ ... 381 12.3 registers controlling serial array unit ................................................................................. 3 85 12.4 operation stop mode ...................................................................................................... ......... 407 12.4.1 stoppin g the operati on by units........................................................................................ .............407 12.4.2 stoppin g the operation by chann els..................................................................................... .........408 12.5 operation of 3-wire serial i/o (csi00, csi01, csi10) communication ............................... 409 12.5.1 master transmission .................................................................................................... ..................410 12.5.2 master recept ion ....................................................................................................... ....................419 12.5.3 master trans mission/rec eption .......................................................................................... ............425 12.5.4 slave transmi ssion ..................................................................................................... ...................433 12.5.5 slave reception ........................................................................................................ .....................442 12.5.6 slave trans mission/rec eption ........................................................................................... .............448 12.5.7 calculating tr ansfer clock frequency ................................................................................... ..........457 12.6 operation of uart (uart0, uart1) communication ......................................................... 459 12.6.1 uart transmi ssion ...................................................................................................... .................460 12.6.2 uart recept ion ......................................................................................................... ...................470 12.6.3 lin transmi ssion ....................................................................................................... ....................477 12.6.4 lin reception.......................................................................................................... .......................480 12.6.5 calculat ing baud rate .................................................................................................. ..................485 12.7 operation of simplified i 2 c (iic10) communication.............................................................. 489 12.7.1 address fi eld transmi ssion ............................................................................................. ...............490 12.7.2 data transmi ssion ...................................................................................................... ...................495 12.7.3 data reception......................................................................................................... ......................498 12.7.4 stop conditi on gener ation .............................................................................................. ...............502 12.7.5 calculati ng transfe r rate .............................................................................................. ..................503 12.8 processing procedure in case of error.................. ............................................................... 505 12.9 relationship between register settings and pins . .............................................................. 507 chapter 13 serial interface iica.......................................................................................... . 511 13.1 functions of serial interface iica ....................................................................................... ... 511 13.2 configuration of serial interf ace iica ................................................................................... . 514 13.3 registers controlling serial interface iica ............ ............................................................... 517 13.4 i 2 c bus mode functions .......................................................................................................... 5 30 13.4.1 pin c onfigurat ion ...................................................................................................... .....................530 13.5 i 2 c bus definitions and control methods .............................................................................. 531 13.5.1 start conditi ons ....................................................................................................... ......................531 13.5.2 a ddresses .............................................................................................................. .......................532 13.5.3 transfer direct ion specif ication ....................................................................................... ..............532 13.5.4 ackno wledge (a ck) ...................................................................................................... ................533 13.5.5 stop condition ......................................................................................................... ......................534 preliminary user?s manual u19291ej1v0ud 14 13.5.6 wait ................................................................................................................... ............................535 13.5.7 canc eling wait ......................................................................................................... ......................537 13.5.8 interrupt request (intiica) gen eration timing and wait cont rol .....................................................538 13.5.9 address matc h detection method......................................................................................... .........539 13.5.10 erro r detec tion....................................................................................................... ......................539 13.5.11 exte nsion code........................................................................................................ ....................539 13.5.12 arbi tration........................................................................................................... .........................540 13.5.13 wake up func tion ....................................................................................................... ..................542 13.5.14 communicati on reserv ation............................................................................................. ............545 13.5.15 ca utions .............................................................................................................. ........................549 13.5.16 communica tion oper ations.............................................................................................. ............550 13.5.17 timing of i 2 c interrupt request (int iica) occu rrence ..................................................................558 13.6 timing charts ............................................................................................................ ............... 579 chapter 14 multiplier/divider ............................................................................................... .... 586 14.1 functions of multiplier/divider ...................................... ........................................................ 58 6 14.2 configuration of multiplier/divide r ........................................................................................ 586 14.3 register controlling multiplier/di vider ................................................................................. 591 14.4 operations of multiplier/divider ............................................................................................. 59 2 14.4.1 multiplication operation ....................................................................................................... ..........592 14.4.2 division op eratio n ............................................................................................................. ............593 chapter 15 dma controller .................................................................................................. ... 595 15.1 functions of dma controller .............................................................................................. .... 595 15.2 configuration of dma controller ........................... ............................................................... .. 596 15.3 registers controlling dma cont roller ................................................................................... 59 9 15.4 operation of dma controller.............................................................................................. ..... 602 15.4.1 operat ion proc edure .................................................................................................... .................602 15.4.2 trans fer m ode.......................................................................................................... .....................603 15.4.3 termination of dma tr ansfer ............................................................................................ .............603 15.5 example of setting of dma controller ..................... .............................................................. 60 4 15.5.1 csi consec utive trans mission ........................................................................................... ............604 15.5.2 consecut ive capturing of a/d conversion results ........................................................................ ..606 15.5.3 uart consec utive reception + ack transmi ssion ........................................................................60 8 15.5.4 holding dma trans fer pending by dwaitn ................................................................................. ..610 15.5.5 forced terminat ion by so ftware ......................................................................................... ............611 15.6 cautions on using dma controller ........................................................................................ 6 12 chapter 16 interrupt functions ............................................................................................ 6 14 16.1 interrupt function types ................................................................................................. ........ 614 preliminary user?s manual u19291ej1v0ud 15 16.2 interrupt sources and configuration ..................................................................................... 6 14 16.3 registers controlling interrupt functions .............. .............................................................. 618 16.4 interrupt servicing operati ons ........................................................................................... .... 628 16.4.1 maskable interrupt request ackn owledgm ent.............................................................................. ..628 16.4.2 software interrupt request ack nowledg ment .............................................................................. ...631 16.4.3 multiple in terrupt se rvicing ........................................................................................... .................631 16.4.4 interrupt request hold ................................................................................................. ...................635 chapter 17 key interrupt function ..................................................................................... 636 17.1 functions of key interrupt ............................................................................................... ....... 636 17.2 configuration of key interrupt................................. .......................................................... ..... 636 17.3 register controlling key interrupt ........................... ............................................................ .. 638 chapter 18 standby function ................................................................................................ .. 639 18.1 standby function and conf iguration..................................................................................... 63 9 18.1.1 standby func tion ....................................................................................................... ....................639 18.1.2 registers contro lling standby function ................................................................................. .........640 18.2 standby function operation..................................... .......................................................... .... 643 18.2.1 ha lt m ode.............................................................................................................. .....................643 18.2.2 st op m ode .............................................................................................................. ....................648 chapter 19 reset function .................................................................................................. ..... 653 19.1 register for confirming reset source..................... .............................................................. 66 2 chapter 20 power-on-clear circuit ..................................................................................... 663 20.1 functions of power-on-clear circuit ....................... .............................................................. 6 63 20.2 configuration of power-on-clear circuit ............................................................................... 664 20.3 operation of power-on-clear circuit....................... ............................................................... 664 20.4 cautions for power-on-clear circuit ....................... ............................................................... 667 chapter 21 low-voltage detector ....................................................................................... 669 21.1 functions of low-voltage detector ........................... ............................................................ 6 69 21.2 configuration of low-voltage de tector ................................................................................. 670 21.3 registers controlling low-voltage detector .......... .............................................................. 670 21.4 operation of low-voltage detector.......................... .............................................................. 675 21.4.1 when us ed as re set ..................................................................................................... .................676 21.4.2 when used as interrupt ................................................................................................. ................682 21.5 cautions for low-voltage detector .......................... .............................................................. 688 preliminary user?s manual u19291ej1v0ud 16 chapter 22 regulator ........................................................................................................ ......... 692 22.1 regulator overview ............................................................................................................. ... 692 22.2 registers controlling regulator............................................................................................ 692 chapter 23 option byte..................................................................................................... .......... 694 23.1 functions of option by tes ................................................................................................ ...... 694 23.1.1 user option byte (000c0h to 000c2h/010c0h to 010c 2h) .........................................................694 23.1.2 on-chip debug option byte (000c 3h/ 010c 3h)............................................................................. 695 23.2 format of user option byte ............................................................................................... ..... 695 23.3 format of on-chip debug option byte......................... .......................................................... 697 23.4 setting of option byte ................................................................................................... .......... 698 chapter 24 flash memory .................................................................................................... ...... 699 24.1 writing with flash memory programmer ............................................................................... 699 24.2 programming environment .................................................................................................. ... 704 24.3 communication mode ....................................................................................................... ....... 704 24.4 connection of pins on board.............................................................................................. .... 705 24.4.1 fl md0 pin.............................................................................................................. .......................705 24.4.2 t ool0 pi n.............................................................................................................. .......................706 24.4.3 r eset pin .............................................................................................................. ......................706 24.4.4 po rt pins .............................................................................................................. ..........................707 24.4.5 re gc pin ............................................................................................................... .......................707 24.4.6 x1 an d x2 pins ......................................................................................................... .....................707 24.4.7 powe r suppl y........................................................................................................... ......................707 24.5 registers controlling flash memory............................ .......................................................... 7 08 24.6 programming method ....................................................................................................... ....... 708 24.6.1 controlli ng flash memory............................................................................................... ................708 26.6.2 flash memory programmi ng mode .......................................................................................... .....709 24.6.3 selecting communicati on mode ........................................................................................... .........709 24.6.4 communi cation co mmands................................................................................................. ..........710 24.7 security settings ........................................................................................................ .............. 711 24.8 flash memory programming by self-programming ... .......................................................... 713 24.8.1 boot swap func tion ..................................................................................................... ...................715 24.8.2 flash shield window f unction........................................................................................... ..............717 chapter 25 on-chip debug function ..................................................................................... 718 25.1 connecting qb-mini2 to 78k0r/kx3-l ............................ ..................................................... 718 25.2 on-chip debug security id .................................................................................................... 71 9 25.3 securing of user resources .................................................................................................. 719 preliminary user?s manual u19291ej1v0ud 17 chapter 26 bcd correction circuit ....................... .............................................................. 721 26.1 bcd correction circuit function .................................. ........................................................ 721 26.2 registers used by bcd correction circuit .............. ............................................................ 721 26.3 bcd correction circuit operation ........................................................................................ 722 chapter 27 instruction set .................................................................................................. ..... 724 27.1 conventions used in operation list........................ .............................................................. 7 24 27.1.1 operand identifiers and specificat ion me thods .......................................................................... ...724 27.1.2 description of operation column........................................................................................ ............725 27.1.3 description of flag operati on colu mn ................................................................................... ..........726 27.1.4 prefix instruct ion..................................................................................................... ...................726 27.2 operation list ........................................................................................................... ................ 727 chapter 28 electrical specifications (target) ............................................................. 744 chapter 29 package drawings................................................................................................. 793 29.1 78k0r/kc3-l (44-pin products) ................................ ............................................................ .. 793 29.2 78k0r/kc3-l (48-pin products) ................................ ............................................................ .. 794 29.3 78k0r/kd3-l.............................................................................................................. ............... 795 29.4 78k0r/ke3-l.............................................................................................................. ............... 796 appendix a development tools .............................................................................................. 8 00 a.1 software package.......................................................................................................... ............ 803 a.2 language processing software .. ............................................................................................ . 803 a.3 flash memory programming tools ................................ ......................................................... 804 a.3.1 when using flash memory programme r pg-fp5, fl-pr5, pg -fp4 and fl -pr4 ..........................804 a.3.2 when using on-chip debug emulator with programm ing function qb-mini2 ..................................804 a.4 debugging tools (hardwar e) ................................................................................................ ... 805 a.4.1 when using in-circuit emulator qb -78k0rix3.............................................................................. ..805 a.4.2 when using on-chip debug emulator with programm ing function qb-mini2 ..................................806 a.5 debugging tools (s oftware)................................................................................................ ..... 806 preliminary user?s manual u19291ej1v0ud 18 chapter 1 outline 1.1 features { minimum instruction execution time can be changed from high speed (0.05 s: @ 20 mhz operation with high- speed system clock) to ultra low-speed (61 s: @ 32.768 khz operation with subsystem clock) { general-purpose register: 8 bits 32 registers (8 bits 8 registers 4 banks) { rom, ram capacities 78k0r/kc3-l 78k0r/kd3-l 78k0r/ke3-l flash rom ram 44 pins 48 pins 52 pins 64 pins 64 kb 3 kb note 1 pd78f1003 note 2 pd78f1006 note 2 pd78f1009 note 2 48 kb 2 kb pd78f1002 note 2 pd78f1005 note 2 pd78f1008 note 2 32 kb 1.5 kb pd78f1001 note 2 pd78f1004 note 2 pd78f1007 note 2 16 kb 1 kb pd78f1000 note 2 ? ? ? notes 1. this is 2 kb when the self-programming function is used. 2. under development { on-chip internal high-speed oscillation clocks ? 20 mhz internal high-speed oscillation clock: 20 mhz 1 % (target) ? 8 mhz internal high-speed oscillation clock: 8 mhz 1 % (target) ? 1 mhz internal high-speed oscillation clock: 1 mhz 5 % { on-chip single-power-supply flash memory (with prohib ition of chip erase/block erase/writing function) { self-programming (with boot swap functi on/flash shield window function) { on-chip debug function { on-chip power-on-clear (poc) circuit and low-voltage detector (lvi) { on-chip watchdog timer (operable with the dedicated internal low-speed oscillation clock) { on-chip multiplier/divider (16 bits 16 bits, 32 bits 32 bits) { on-chip key interrupt function { on-chip clock output/buzzer output controller note { on-chip bcd adjustment { i/o ports: 37 to 55 (n-ch open drain: 2 note ) { timer: 10 channels ? 16-bit timer: 8 channels ? watchdog timer: 1 channel ? real-time counter: 1 channel { on-chip comparator/programmable gain amplifier function { serial interface ? csi: 2 channels/uart (lin-bus supported): 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? i 2 c: 1 channel note { 10-bit resolution a/d converter (av ref = 1.8 to 5.5 v): 10 to 12 channels { power supply voltage: v dd = 1.8 to 5.5 v { operating ambient temperature: t a = ? 40 to +85 c note this is not mounted onto 44-pi n products of the 78k0r/kc3-l. chapter 1 outline preliminary user?s manual u19291ej1v0ud 19 1.2 applications { audio visual equipment { home appliances { industrial equipment 1.3 ordering information ? flash memory version (lead-free product) 78k0r/kx3 microcontroller package part number 44-pin plastic lqfp (10 10) pd78f1000gb-gaf-ax note , 78f1001gb-gaf-ax note , 78f1002gb-gaf-ax note , 78f1003gb-gaf-ax note 78k0r/kc3-l 48-pin plastic tqfp (fine pitch) (7 7) pd78f1001ga-haa-ax note , 78f1002ga-haa-ax note , 78f1003ga-haa-ax note 78k0r/kd3-l 52-pin plastic lqfp (10 10) pd78f1004gb-gag-ax note , 78f1005gb-gag-ax note , 78f1006gb-gag-ax note 64-pin plastic lqfp (12 12) pd78f1007gk-gaj-ax note , 78f1008gk-gaj-ax note , 78f1009gk-gaj-ax note 64-pin plastic lqfp (fine pitch) (10 10) pd78f1007gb-gah-ax note , 78f1008gb-gah-ax note , 78f1009gb-gah-ax note 64-pin plastic tqfp (fine pitch) (7 7) pd78f1007ga-hab-ax note , 78f1008ga-hab-ax note , 78f1009ga-hab-ax note 78k0r/ke3-l 64-pin plastic fbga (5 5) pd78f1007f1-an1-a note , 78f1008f1-an1-a note , 78f1009f1-an1-a note note under development caution the 78k0r/kx3-l has an on-chip debug f unction, which is provided for development and evaluation. do not use the on-ch ip debug function in products designate d for mass production, because the guaranteed number of rewritable tim es of the flash memory may be exceeded when this function is used, and product reliability th erefore cannot be guaranteed. nec electronics is not liable for problems occurring when the on-chip debug function is used. chapter 1 outline preliminary user?s manual u19291ej1v0ud 20 1.4 pin configuration (top view) 1.4.1 78k0r/kc3-l ? 44-pin plastic lqfp (10 10) 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 p120/intp0/exlvi p20/ani0 p21/ani1 p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p150/ani8 p151/ani9 av ss av ref p80/cmp0p/intp3/pgai p81/cmp0m p82/cmp1p/intp7 p83/cmp1m p10/ti02/to02 p11/ti03/to03 p12/ti04/to04/rtcdiv/rtccl p13/ti05/to05 p50/ti06/to06 p41/tool1 p40/tool0 reset p124/xt2 p123/xt1 flmd0 p122/x2/exclk p121/x1 regc v ss v dd p30/so10/txd1 p31/si10/rxd1/sda10/intp1 p32/sck10/scl10/intp2 p75/kr5/sck00 p74/kr4/si00/rxd0 p73/kr3/so00/txd0 p72/kr2/sck01/intp6 p71/kr1/si01/intp5 p70/kr0/so01/intp4 p52/rtc1hz/slti/slto p51/ti07/to07 cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to vss via a capacitor (0.47 to 1 f: target). remark for pin identification, see 1.5 pin identification . chapter 1 outline preliminary user?s manual u19291ej1v0ud 21 ? 48-pin plastic tqfp (fine pitch) (7 7) 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 v dd v ss regc p121/x1 p122/x2/exclk flmd0 p123/xt1 p124/xt2 reset p40/tool0 p41/tool1 p120/intp0/exlvi p140/pclbuz0 p20/ani0 p21/ani1 p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p150/ani8 p151/ani9 p152/ani10 p51/ti07/to07 p50/ti06/to06 p13/ti05/to05 p12/ti04/to04/rtcdiv/rtccl p11/ti03/to03 p10/ti02/to02 p83/cmp1m p82/cmp1p/intp7 p81/cmp0m p80/cmp0p/intp3/pgai av ref av ss p60/scl0 p61/sda0 p30/so10/txd1 p31/si10/rxd1/sda10/intp1 p32/sck10/scl10/intp2 p75/kr5/sck00 p74/kr4/si00/rxd0 p73/kr3/so00/txd0 p72/kr2/sck01/intp6 p71/kr1/si01/intp5 p70/kr0/so01/intp4 p52/rtc1hz/slti/slto cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to vss via a capacitor (0.47 to 1 f: target). remark for pin identification, see 1.5 pin identification . chapter 1 outline preliminary user?s manual u19291ej1v0ud 22 1.4.2 78k0r/kd3-l ? 52-pin plastic lqfp (10 10) 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 52 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 22 23 24 25 26 p00/ti00 p01/to00 p20/ani0 p21/ani1 p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p150/ani8 p151/ani9 p152/ani10 p60/scl0 p61/sda0 p30/so10/txd1 p31/si10/rxd1/sda10/intp1 p32/sck10/scl10/intp2 p77/kr7 p76/kr6 p75/kr5/sck00 p74/kr4/si00/rxd0 p73/kr3/so00/txd0 p72/kr2/sck01/intp6 p71/kr1/si01/intp5 p70/kr0/so01/intp4 av ss av ref p80/cmp0p/intp3/pgai p81/cmp0m p82/cmp1p/intp7 p83/cmp1m p10/ti02/to02 p11/ti03/to03 p12/ti04/to04/rtcdiv/rtccl p13/ti05/to05 p50/ti06/to06 p51/ti07/to07 p52/rtc1hz/slti/slto p140/pclbuz0 p120/intp0/exlvi p41/tool1 p40/tool0 reset p124/xt2 p123/xt1 flmd0 p122/x2/exclk p121/x1 regc v ss v dd cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to vss via a capacitor (0.47 to 1 f: target). remark for pin identification, see 1.5 pin identification . chapter 1 outline preliminary user?s manual u19291ej1v0ud 23 1.4.3 78k0r/ke3-l ? 64-pin plastic lqfp (12 12) ? 64-pin plastic lqfp (fine pitch) (10 10) ? 64-pin plastic tqfp (fine pitch) (7 7) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p140/pclbuz0 p141/pclbuz1 p00/ti00 p01/to00 p20/ani0 p21/ani1 p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p150/ani8 p151/ani9 p152/ani10 p153/ani11 p60/scl0 p61/sda0 p30/so10/txd1 p31/si10/rxd1/sda10/intp1 p32/sck10/scl10/intp2 p33 p77/kr7 p76/kr6 p75/kr5/sck00 p74/kr4/si00/rxd0 p73/kr3/so00/txd0 p72/kr2/sck01/intp6 p71/kr1/si01/intp5 p70/kr0/so01/intp4 p53 p52/rtc1hz/slti/slto av ss av ref p80/cmp0p/intp3/pgai p81/cmp0m p82/cmp1p/intp7 p83/cmp1m p10/ti02/to02 p11/ti03/to03 p12/ti04/to04/rtcdiv/rtccl p13/ti05/to05 p14/ti06/to06 p15/ti07/to07 p16 p17 p50 p51 p120/intp0/exlvi p43 p42 p41/tool1 p40/tool0 reset p124/xt2 p123/xt1 flmd0 p122/x2/exclk p121/x1 regc v ss ev ss v dd ev dd 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 cautions 1. make av ss and ev ss the same potential as v ss . 2. make ev dd the same potential as v dd . 3. connect the regc pin to vss via a capacitor (0.47 to 1 f: target). remark for pin identification, see 1.5 pin identification . chapter 1 outline preliminary user?s manual u19291ej1v0ud 24 ? 64-pin plastic fbga (5 5) 1 hgfedcba 2 3 4 5 6 7 8 abcdefgh top view bottom view index mark pin no. name pin no. name pin no. name pin no. name a1 p17 c1 p82/cmp1p/intp7 e1 p153/ani11 g1 av ref a2 p16 c2 p83/cmp1m e2 p152/ani10 g2 p27/ani7 a3 p15/ti07/to07 c3 p11/ti03/to03 e3 p77/kr7 g3 p24/ani4 a4 p53 c4 p51 e4 p76/kr6 g4 p21/ani1 a5 p70/kr0/so01 /intp4 c5 p74/kr4/si00/rxd0 e5 p30/so10/txd1 g5 p32/sck10/scl10 /intp2 a6 p72/kr2/sck01 /intp6 c6 p60/scl0 e6 p41/tool1 g6 p00/ti00 a7 p61/sda0 c7 v ss e7 reset g7 p140/pclbuz0 a8 ev dd c8 p121/x1 e8 flmd0 g8 p124/xt2 b1 p14/ti06/to06 d1 p80/cmp0p /intp3/pgai f1 p151/ani9 h1 av ss b2 p13/ti05/to05 d2 p81/cmp0m f2 p150/ani8 h2 p26/ani6 b3 p12/ti04/to04 /rtcdiv/rtccl d3 p10/ti02/to02 f3 p23/ani3 h3 p25/ani5 b4 p52/rtc1hz/slti /slto d4 p50 f4 p20/ani0 h4 p22/ani2 b5 p71/kr1/si01/intp5 d5 p75/kr5/sck00 f5 p31/si10/rxd1 /sda10/intp1 h5 p33 b6 p73/kr3/so00/txd0 d6 p40/tool0 f6 p43 h6 p01/to00 b7 v dd d7 regc f7 p42 h7 p141/pclbuz1 b8 ev ss d8 p122/x2/exclk f8 p123/xt1 h8 p120/intp0/exlvi note under development cautions 1. make av ss and ev ss the same potential as v ss . 2. make ev dd the same potential as v dd . 3. connect the regc pin to v ss via a capacitor (0.47 to 1 f: target). remark for pin identification, see 1.5 pin identification . chapter 1 outline preliminary user?s manual u19291ej1v0ud 25 1.5 pin identification ani0 to ani11: analog input av ref : analog reference voltage av ss : analog ground cmp0m, cmp1m: comparator input (minus) cmp0p, cmp1p: comparator input (plus) ev dd : power supply for port ev ss : ground for port exclk: external clock input (main system clock) exlvi: external potential input for low-voltage detector flmd0: flash programming mode intp0 to intp7: external interrupt input kr0 to kr7: key return p00, p01: port 0 p10 to p17: port 1 p20 to p27: port 2 p30 to p33: port 3 p40 to p43: port 4 p50 to p53: port 5 p60, p61: port 6 p70 to p77: port 7 p80 to p83: port 8 p120 to p124: port 12 p140, p141: port 14 p150 to p153: port 15 pclbuz0, pclbuz1: programmable clock output/buzzer output pgai: programmable gain amplifier input regc: regulator capacitance reset: reset rtc1hz: real-time counter correction clock (1 hz) output rtccl: real-time counter clock (32 khz original oscillation) output rtcdiv: real-time counter clock (32 khz divided frequency) output rxd0, rxd1: receive data sck00, sck01, sck10: serial clock input/output scl0, scl10: serial clock input/output sda0, sda10: serial data input/output si00, si01, si10: serial data input slti: selectable timer input slto: selectable timer output so00, so01, so10: serial data output ti00, ti02 to ti07: timer input to00, to02 to to07: timer output tool0: data input/output for tool tool1: clock output for tool txd0, txd1: transmit data v dd : power supply v ss : ground x1, x2: crystal oscillat or (main system clock) xt1, xt2: crystal oscillator (subsystem clock) chapter 1 outline preliminary user?s manual u19291ej1v0ud 26 1.6 block diagram 1.6.1 78k0r/kc3-l ? 44-pin products port 1 p10 to p13 port 2 p20 to p27 8 port 3 p30 to p32 3 port 4 port 5 flmd0 4 port 12 p121 to p124 p40, p41 2 p50 to p52 3 voltage regulator regc interrupt control ram 78k0r cpu core flash memory window watchdog timer low-speed internal oscillator power on clear/ low voltage indicator poc/lvi control reset control exlvi/p120 pgai/p80 system control reset x1/p121 x2/exclk/p122 high-speed internal oscillator on-chip debug tool0/p40 tool1/p41 realtime counter serial array unit (4ch) uart0 uart1 iic10 rxd0/p74 txd0/p73 rxd1/p31 txd1/p30 scl10/p32 sda10/p31 timer array unit (8ch) ch2 ti02/to02/p10 ch3 ti03/to03/p11 ch0 ch1 ch4 ti04/to04/p12 ch5 ti05/to05/p13 ch6 ti06/to06/p50 ch7 intp4/p70, intp5/p71, intp6/p72 3 intp0/p120 intp3/p80, intp7/p82 intp1/p31, intp2/p32 2 rxd0/p74 (linsel) csi10 sck10/p32 so10/p30 si10/p31 rxd0/p74 (linsel) a/d converter 8 ani0/p20 to ani7/p27 av ref av ss 4 p120 port 8 p80 to p83 4 comparator programmable gain amplifier cmp0m/p81, cmp1m/p83 2 cmp0p/p80, cmp1p/p82 ti07/to07/p51 bcd adjustment 2 sck00/p75 so00/p73 si00/p74 csi00 v ss v dd 2 multiplier& divider linsel xt1/p123 xt2/p124 key return 6 kr0/p70 to kr5/p75 2 ani8/p150, ani9/p151 sck01/p72 so01/p70 si01/p71 csi01 direct memory access control port 7 p70 to p75 6 port 15 p150, p151 2 slti/slto/p52 rtcdiv/rtccl/p12 rtc1hz/p52 chapter 1 outline preliminary user?s manual u19291ej1v0ud 27 ? 48-pin products port 1 p10 to p13 port 2 p20 to p27 8 port 3 p30 to p32 3 port 4 port 5 flmd0 4 port 12 p121 to p124 p40, p41 2 p50 to p52 3 voltage regulator regc interrupt control ram 78k0r cpu core flash memory window watchdog timer low-speed internal oscillator power on clear/ low voltage indicator poc/lvi control reset control exlvi/p120 pgai/p80 system control reset x1/p121 x2/exclk/p122 high-speed internal oscillator on-chip debug tool0/p40 tool1/p41 realtime counter serial array unit (4ch) uart0 uart1 iic10 rxd0/p74 txd0/p73 rxd1/p31 txd1/p30 scl10/p32 sda10/p31 timer array unit (8ch) ch2 ti02/to02/p10 ch3 ti03/to03/p11 ch0 ch1 ch4 ti04/to04/p12 ch5 ti05/to05/p13 ch6 ti06/to06/p50 ch7 intp4/p70, intp5/p71, intp6/p72 3 intp0/p120 intp3/p80, intp7/p82 intp1/p31, intp2/p32 2 rxd0/p74 (linsel) csi10 sck10/p32 so10/p30 si10/p31 rxd0/p74 (linsel) a/d converter 8 ani0/p20 to ani7/p27 av ref av ss 4 p120 port 8 p80 to p83 4 comparator programmable gain amplifier cmp0m/p81, cmp1m/p83 2 cmp0p/p80, cmp1p/p82 ti07/to07/p51 bcd adjustment 2 sck00/p75 so00/p73 si00/p74 csi00 v ss v dd serial interface iica sda0/p61 scl0/p60 2 multiplier& divider linsel xt1/p123 xt2/p124 buzzer output pclbuz0/p140 clock output control key return 6 kr0/p70 to kr5/p75 3 ani8/p150 to ani10/p152 sck01/p72 so01/p70 si01/p71 csi01 direct memory access control port 6 port 7 p70 to p75 6 p60, p61 2 port 14 p140 port 15 p150-p152 3 slti/slto/p52 rtcdiv/rtccl/p12 rtc1hz/p52 chapter 1 outline preliminary user?s manual u19291ej1v0ud 28 1.6.2 78k0r/kd3-l port 1 p10 to p13 port 2 p20 to p27 8 port 3 p30 to p32 3 port 4 port 5 flmd0 4 port 12 p121 to p124 p40, p41 2 p50 to p52 3 voltage regulator regc interrupt control ram 78k0r cpu core flash memory window watchdog timer low-speed internal oscillator power on clear/ low voltage indicator poc/lvi control reset control exlvi/p120 pgai/p80 system control reset x1/p121 x2/exclk/p122 high-speed internal oscillator on-chip debug tool0/p40 tool1/p41 realtime counter serial array unit (4ch) uart0 uart1 iic10 rxd0/p74 txd0/p73 rxd1/p31 txd1/p30 scl10/p32 sda10/p31 timer array unit (8ch) ch2 ti02/to02/p10 ch3 ti03/to03/p11 ch0 ch1 ch4 ti04/to04/p12 ch5 ti05/to05/p13 ch6 ti06/to06/p50 ch7 intp4/p70, intp5/p71, intp6/p72 3 intp0/p120 intp3/p80, intp7/p82 intp1/p31, intp2/p32 2 rxd0/p74 (linsel) csi10 sck10/p32 so10/p30 si10/p31 rxd0/p74 (linsel) a/d converter 8 ani0/p20 to ani7/p27 av ref av ss 4 p120 port 8 p80 to p83 4 comparator programmable gain amplifier cmp0m/p81, cmp1m/p83 2 cmp0p/p80, cmp1p/p82 ti07/to07/p51 ti00/p00 to00/p01 bcd adjustment 2 sck00/p75 so00/p73 si00/p74 csi00 v ss v dd serial interface iica sda0/p61 scl0/p60 2 multiplier& divider linsel xt1/p123 xt2/p124 port 0 p00, p01 2 buzzer output pclbuz0/p140 clock output control key return 8 kr0/p70 to kr7/p77 3 ani8/p150 to ani10/p152 sck01/p72 so01/p70 si01/p71 csi01 direct memory access control port 6 port 7 p70 to p77 8 p60, p61 2 port 14 p140 port 15 p150 to p152 3 slti/slto/p52 rtcdiv/rtccl/p12 rtc1hz/p52 chapter 1 outline preliminary user?s manual u19291ej1v0ud 29 1.6.3 78k0r/ke3-l port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30 to p33 4 port 4 port 5 flmd0 8 port 12 p121 to p124 p40 to p43 4 p50 to p53 4 voltage regulator regc interrupt control ram 78k0r cpu core flash memory window watchdog timer low-speed internal oscillator power on clear/ low voltage indicator poc/lvi control reset control exlvi/p120 pgai/p80 system control reset x1/p121 x2/exclk/p122 high-speed internal oscillator on-chip debug tool0/p40 tool1/p41 realtime counter serial array unit (4ch) uart0 uart1 iic10 rxd0/p74 txd0/p73 rxd1/p31 txd1/p30 scl10/p32 sda10/p31 timer array unit (8ch) ch2 ti02/to02/p10 ch3 ti03/to03/p11 ch0 ch1 ch4 ti04/to04/p12 ch5 ti05/to05/p13 ch6 ti06/to06/p14 ch7 intp4/p70, intp5/p71 2 intp0/p120 intp3/p80, intp7/p82 intp1/p31, intp2/p32 2 rxd0/p74 (linsel) csi10 sck10/p32 so10/p30 si10/p31 rxd0/p74 (linsel) a/d converter 8 ani0/p20 to ani7/p27 av ref av ss 4 p120 port 8 p80 to p83 4 comparator programmable gain amplifier cmp0m/p81, cmp1m/p83 2 cmp0p/p80, cmp1p/p82 ti07/to07/p15 ti00/p00 to00/p01 bcd adjustment 2 sck00/p75 so00/p73 si00/p74 csi00 v ss , ev ss v dd , ev dd serial interface iica sda0/p61 scl0/p60 2 intp6/p72 multiplier& divider linsel xt1/p123 xt2/p124 port 0 p00, p01 2 buzzer output pclbuz0/p140, pclbuz1/p141 clock output control key return 8 kr0/p70 to kr7/p77 4 ani8/p150 to ani11/p153 sck01/p72 so01/p70 si01/p71 csi01 direct memory access control port 6 port 7 p70 to p77 8 p60, p61 2 port 14 p140 p141 port 15 p150 to p153 4 2 slti/slto/p52 rtcdiv/rtccl/p12 rtc1hz/p52 chapter 1 outline preliminary user?s manual u19291ej1v0ud 30 1.7 outline of functions (1/2) item 78k0r/kc3-l (44-pin) ( pd78f100y note 1 :y = 0 to 3 ) 78k0r/kc3-l (48-pin) ( pd78f100y note 1 :y = 1 to 3 ) 78k0r/kd3-l ( pd78f100y note 1 :y = 4 to 6 ) 78k0r/ke3-l ( pd78f100y note 1 :y = 7 to 9 ) flash memory (kb) 16 32 48 64 32 48 64 32 48 64 32 48 64 internal memory ram (kb) 1 1.5 2 3/2 note 2 1.5 2 3/2 note 2 1.5 2 3/2 note 2 1.5 2 3/2 note 2 memory space 1 mb high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) 2 to 20 mhz: v dd = 2.7 to 5.5 v, 2 to 5 mhz: v dd = 1.8 to 5.5 v internal high-speed oscillation clock internal oscillation 1 mhz 5%, 8 mhz 1% (target): v dd = 1.8 to 5.5 v main system clock 20 mhz internal high- speed oscillation clock internal oscillation 20 mhz 1% (target): v dd = 2.7 to 5.5 v subsystem clock xt1 (crystal) oscillation 32.768 khz (typ.): v dd = 1.8 to 5.5 v internal low-speed oscillation clock (dedicated to wdt) internal oscillation 30 khz (typ.): v dd = 1.8 to 5.5 v general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) 0.05 s (high-speed system clock: f mx = 20 mhz operation) minimum instruction execution time 61 s (subsystem clock: f sub = 32.768 khz operation) instruction set ? 8-bit operation, 16-bit operation ? multiplication (8 bits 8 bits) ? bit manipulation (set, reset, test, and boolean operation), etc. i/o port total 37 41 45 55 cmos i/o 33 34 38 48 cmos input 4 4 4 4 cmos output ? 1 1 1 n-ch open-drain i/o (6 v tolerance) ? 2 2 2 timer ? 16-bit timer: 8 channels ? watchdog timer: 1 channel ? real-time counter (rtc): 1 channel timer output 8 (pwm output: 7 note 3 ) rtc output 2 ? 1 hz (subsystem clock: f sub = 32.768 khz) ? 512 hz, 16.384 khz, or 32.768 khz (subsystem clock: f sub = 32.768 khz) notes 1. under development 2. this is 2 kb when the self-programming function is used. 3. the number of outputs varies , depending on the setting. chapter 1 outline preliminary user?s manual u19291ej1v0ud 31 (2/2) item 78k0r/kc3-l (44-pin) ( pd78f100y note 1 :y = 0 to 3 ) 78k0r/kc3-l (48-pin) ( pd78f100y note 1 :y = 1 to 3 ) 78k0r/kd3-l ( pd78f100y note 1 :y = 4 to 6 ) 78k0r/ke3-l ( pd78f100y note 1 :y = 7 to 9 ) ? 1 1 2 clock output/buzzer output ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (peripheral hardware clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) 10-bit resolution a/d converter (av ref = 1.8 to 5.5 v) 10 channels 11 channels 11 channels 12 channels serial interface ? csi: 2 channels/uart (lin-bus supported): 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel i 2 c bus ? 1 channel 1 channel 1 channel multiplier/divider ? 16 bits 16 bits = 32 bits (multiplication) ? 32 bits 32 bits = 32 bits (division) dma controller 2 channels internal 24 25 25 25 vectored interrupt sources external 9 key interrupt 6 channels (kr0 to kr5) 8 channels (kr0 to kr7) reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-clear ? internal reset by low-voltage detector ? internal reset by illegal instruction execution note 2 power-on-clear circuit ? power-on-reset: 1.61 0.09 v ? power-down-reset: 1.59 0.09 v low-voltage detector 1.91 v to 4.22 v (16 stages) on-chip debug function provided power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to +85 c notes 1. under development 2. the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction exec ution not issued by emulation with t he in-circuit emulator or on-chip debug emulator. preliminary user?s manual u19291ej1v0ud 32 chapter 2 pin functions 2.1 pin function list pin i/o buffer power supplies depend on the product. the relationship between t hese power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies (av ref , v dd ) ? 78k0r/kc3-l: 44-pin plastic lqfp (10x10) 48-pin plastic tqfp (fine pitch) (7x7) ? 78k0r/kd3-l: 52-pin plastic lqfp (10x10) power supply corresponding pins av ref p20 to p27, p150 to p152 note , p80 to p83 ev dd ? port pins other than p20 to p27, p150 to p152 note , p80 to p83 ? pins other than port pins note 44-pin products of the 78k0r/kc3-l do not have a p152 pin. table 2-2. pin i/o buffer power supplies (av ref , ev dd , v dd ) ? 78k0r/ke3-l: 64-pin plastic fbga (5x5) 64-pin plastic tqfp (fine pitch) (7x7) 64-pin plastic lqfp (fine pitch) (10x10) 64-pin plastic lqfp (12x12) power supply corresponding pins av ref p20 to p27, p150 to p153, p80 to p83 ev dd ? port pins other than p20 to p27, p150 to p153, p80 to p83, and p121 to p124 ? reset pin and flmd0 pin v dd ? p121 to p124 ? pins other than port pins (other than the reset pin and flmd0 pin) chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 33 2.1.1 78k0r/kc3-l (1) port functions (1/2): 78k0r/kc3-l function name i/o function after reset alternate function p10 ti02/to02 p11 ti03/to03 p12 ti04/to04/ rtcdiv/rtccl p13 i/o port 1. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti05/to05 p20 to p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. digital input port ani0 to ani7 p30 so10/txd1 p31 si10/rxd1/sda10/ intp1 p32 i/o port 3. 3-bit i/o port. input of p31 and p32 can be set to ttl buffer. output of p30 to p32 can be set to n-ch open-drain output (v dd tolerance). input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port sck10/scl10/ intp2 p40 note 1 tool0 p41 i/o port 4. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port tool1 p50 ti06/to06 p51 ti07/to07 p52 i/o port 5. 3-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port rtc1hz/slti/ slto p60 note 2 scl0 note 2 p61 note 2 i/o port 6. 2-bit i/o port. output of p60 and p61 is n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. input port sda0 note 2 p70 kr0/so01/intp4 p71 kr1/si01/intp5 p72 kr2/sck01/intp6 p73 kr3/so00/txd0 p74 kr4/si00/rxd0 p75 i/o port 7. 6-bit i/o port. input of p71, p72, p74, and p75 can be set to ttl buffer. output of p70, p72, p73, and p75 can be set to n-ch open-drain output (v dd tolerance). input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port kr5/sck00 notes 1. if on-chip debugging is enabled by using an option byte, be sure to pull up the p40/tool0 pin externally. 2. 48-pin products only. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 34 (1) port functions (2/2): 78k0r/kc3-l function name i/o function after reset alternate function p80 cmp0p/intp3/ pgai p81 cmp0m p82 cmp1p/intp7 p83 i/o port 8. 4-bit i/o port. inputs/output can be specified in 1-bit units. inputs of p80 to p83 can be set as comparator inputs or programmable gain amplifier inputs. analog input cmp1m p120 i/o intp0/exlvi p121 x1 p122 x2/exclk p123 xt1 p124 input port 12. 1-bit i/o port and 4-bit input port. for only p120, input/output can be specified in 1-bit units. for only p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2 p140 note output port 14. 1-bit output port. output port pclbuz0 note p150, p151, p152 note i/o port 15. 3-bit i/o port. input/output can be specified in 1-bit units. digital input port ani8, ani9, ani10 note note 48-pin products only. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 35 (2) non-port functions (1/3): 78k0r/kc3-l function name i/o function after reset alternate function ani0 to ani7 input p20 to p27 ani8, ani9, ani10 note input a/d converter analog input digital input port p150, p151, p152 note cmp0m input input voltage on the ( ? ) side of comparator 0 p81 cmp0p input input voltage on the (+) side of comparator 0 p80/intp3/pgai cmp1m input input voltage on the ( ? ) side of comparator 1 p83 cmp1p input input voltage on the (+) side of comparator 1 analog input p82/intp7 exlvi input potential input for external low-voltage detection input port p120/intp0 intp0 p120/exlvi intp1 p31/si10/rxd1/ sda10 intp2 input port p32/sck10/scl10 intp3 analog input p80/cmp0p/pgai intp4 p70/kr0/so01 intp5 p71/kr1/si01 intp6 input port p72/kr2/sck01 intp7 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified analog input p82/cmp1p kr0 p70/so01/intp4 kr1 p71/si01/intp5 kr2 p72/sck01/intp6 kr3 p73/so00/txd0 kr4 p74/si00/rxd0 kr5 input key interrupt input input port p75/sck00 pclbuz0 note output clock output/buzzer output output port p140 note pgai input programmable gain amplifier input analog input p80/cmp0p/intp3 regc ? connecting regulator output (2.4 v) stabilization capacitance for internal operation. connect to v ss via a capacitor (0.47 to 1 f: target). ? ? rtcdiv output real-time counter clock (32 khz division) output input port p12/ti04/to04/ rtccl rtccl output real-time counter clock (32 khz original oscillation) output input port p12/ti04/to04/ rtcdiv rtc1hz output real-time counter correction clock (1 hz) output input port p52/slti/slto reset input system reset input ? ? rxd0 serial data input to uart0 p74/kr4/si00 rxd1 input serial data input to uart1 input port p31/si10/sda10/ intp1 sck00 clock input/output for csi00 p75/kr5 sck01 clock input/output for csi01 p72/kr2/intp6 sck10 i/o clock input/output for csi10 input port p32/scl10/intp2 note 48-pin products only. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 36 (2) non-port functions (2/3): 78k0r/kc3-l function name i/o function after reset alternate function scl0 note i/o clock input/output for i 2 c input port p60 note scl10 i/o clock input/output for simplified i 2 c input port p32/sck10/intp2 sda0 note i/o serial data i/o for i 2 c input port p61 note sda10 i/o serial data i/o for simplified i 2 c input port p31/si10/rxd1/ intp1 si00 serial data input to csi00 p74/kr4/rxd0 si01 serial data input to csi01 p71/kr1/intp5 si10 input serial data input to csi10 input port p31/rxd1/sda10/ intp1 slti input 16-bit timer 00, 01 input input port p52/rtc1hz/slto slto output 16-bit timer 00, 01 output input port p52/rtc1hz/slti so00 serial data output from csi00 p73/kr3/txd0 so01 serial data output from csi01 p70/kr0/intp4 so10 output serial data output from csi10 input port p30/txd1 ti02 external count clock input to 16-bit timer 02 p10/to02 ti03 external count clock input to 16-bit timer 03 p11/to03 ti04 external count clock input to 16-bit timer 04 p12/to04/ rtcdiv/rtccl ti05 external count clock input to 16-bit timer 05 p13/to05 ti06 external count clock input to 16-bit timer 06 p50/to06 ti07 input external count clock input to 16-bit timer 07 input port p51/to07 to02 16-bit timer 02 output p10/ti02 to03 16-bit timer 03 output p11/ti03 to04 16-bit timer 04 output p12/ti04/ rtcdiv/rtccl to05 16-bit timer 05 output p13/ti05 to06 16-bit timer 06 output p50/ti06 to07 output 16-bit timer 07 output input port p51/ti07 txd0 serial data output from uart0 p73/kr3/so00 txd1 output serial data output from uart1 input port p30/so10 x1 ? input port p121 x2 ? resonator connection for main system clock input port p122/exclk xt1 ? input port p123 xt2 ? resonator connection for subsystem clock input port p124 exclk input external clock input for ma in system clock input port p122/x2 v dd ? positive power supply (port pins other than p20 to p27, p80 to p83, p150, p151, p152 note , and other than ports) ? ? av ref ? ? a/d converter and comparator reference voltage input ? positive power supply for p2 0 to p27, p150, p151, p152 note , p80 to p83, a/d converter, programmable gain amplifier, and comparator ? ? v ss ? ground potential (port pins other than p20 to p27, p80 to p83, p150, p151, p152 note , and other than ports) ? ? note 48-pin products only. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 37 (2) non-port functions (3/3): 78k0r/kc3-l function name i/o function after reset alternate function av ss ? ground potential for a/d converter, programmable gain amplifier, comparator, p20 to p27, p150, p151, p152 note and p80 to p83 ? ? flmd0 ? flash memory programming mode setting ? ? tool0 i/o data i/o for flash memory programmer/debugger input port p40 tool1 output clock output for debugger input port p41 note 48-pin products only. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 38 2.1.2 78k0r/kd3-l (1) port functions (1/2): 78k0r/kd3-l function name i/o function after reset alternate function p00 ti00 p01 i/o port 0. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port to00 p10 ti02/to02 p11 ti03/to03 p12 ti04/to04/ rtcdiv/rtccl p13 i/o port 1. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti05/to05 p20 to p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. digital input port ani0 to ani7 p30 so10/txd1 p31 si10/rxd1/sda10/ intp1 p32 i/o port 3. 3-bit i/o port. input of p31 and p32 can be set to ttl buffer. output of p30 to p32 can be set to n-ch open-drain output (v dd tolerance). input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port sck10/scl10/ intp2 p40 note tool0 p41 i/o port 4. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port tool1 p50 ti06/to06 p51 ti07/to07 p52 i/o port 5. 3-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port rtc1hz/slti/ slto p60 scl0 p61 i/o port 6. 2-bit i/o port. output of p60 and p61 is n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. input port sda0 note if on-chip debugging is enabled by using an option byte, be sure to pull up the p40/tool0 pin externally. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 39 (1) port functions (2/2): 78k0r/kd3-l function name i/o function after reset alternate function p70 kr0/so01/intp4 p71 kr1/si01/intp5 p72 kr2/sck01/intp6 p73 kr3/so00/txd0 p74 kr4/si00/rxd0 p75 kr5/sck00 p76 kr6 p77 i/o port 7. 8-bit i/o port. input of p71, p72, p74, and p75 can be set to ttl buffer. output of p70, p72, p73, and p75 can be set to n-ch open-drain output (v dd tolerance). input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port kr7 p80 cmp0p/intp3/ pgai p81 cmp0m p82 cmp1p/intp7 p83 i/o port 8. 4-bit i/o port. inputs/output can be specified in 1-bit units. inputs of p80 to p83 can be set as comparator inputs or programmable gain amplifier inputs. analog input cmp1m p120 i/o intp0/exlvi p121 x1 p122 x2/exclk p123 xt1 p124 input port 12. 1-bit i/o port and 4-bit input port. for only p120, input/output can be specified in 1-bit units. for only p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2 p140 output port 14. 1-bit output port. output port pclbuz0 p150 to p152 i/o port 15. 3-bit i/o port. input/output can be specified in 1-bit units. digital input port ani8 to ani10 chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 40 (2) non-port functions (1/3): 78k0r/kd3-l function name i/o function after reset alternate function ani0 to ani7 input p20 to p27 ani8 to ani10 input a/d converter analog input digital input port p150 to p152 cmp0m input input voltage on the ( ? ) side of comparator 0 p81 cmp0p input input voltage on the (+) side of comparator 0 p80/intp3/pgai cmp1m input input voltage on the ( ? ) side of comparator 1 p83 cmp1p input input voltage on the (+) side of comparator 1 analog input p82/intp7 exlvi input potential input for external low-voltage detection input port p120/intp0 intp0 p120/exlvi intp1 p31/si10/rxd1/ sda10 intp2 input port p32/sck10/scl10 intp3 analog input p80/cmp0p/pgai intp4 p70/kr0/so01 intp5 p71/kr1/si01 intp6 input port p72/kr2/sck01 intp7 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified analog input p82/cmp1p kr0 p70/so01/intp4 kr1 p71/si01/intp5 kr2 p72/sck01/intp6 kr3 p73/so00/txd0 kr4 p74/si00/rxd0 kr5 p75/sck00 kr6 p76 kr7 input key interrupt input input port p77 pclbuz0 output clock output/buzzer output output port p140 pgai input programmable gain amplifier input analog input p80/cmp0p/intp3 regc ? connecting regulator output (2.4 v) stabilization capacitance for internal operation. connect to v ss via a capacitor (0.47 to 1 f: target). ? ? rtcdiv output real-time counter clock (32 khz division) output input port p12/ti04/to04/ rtccl rtccl output real-time counter clock (32 khz original oscillation) output input port p12/ti04/to04/ rtcdiv rtc1hz output real-time counter correction clock (1 hz) output input port p52/slti/slto reset input system reset input ? ? chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 41 (2) non-port functions (2/3): 78k0r/kd3-l function name i/o function after reset alternate function rxd0 serial data input to uart0 p74/kr4/si00 rxd1 input serial data input to uart1 input port p31/si10/sda10/ intp1 sck00 clock input/output for csi00 p75/kr5 sck01 clock input/output for csi01 p72/kr2/intp6 sck10 i/o clock input/output for csi10 input port p32/scl10/intp2 scl0 i/o clock input/output for i 2 c input port p60 scl10 i/o clock input/output for simplified i 2 c input port p32/sck10/intp2 sda0 i/o serial data i/o for i 2 c input port p61 sda10 i/o serial data i/o for simplified i 2 c input port p31/si10/rxd1/ intp1 si00 serial data input to csi00 p74/kr4/rxd0 si01 serial data input to csi01 p71/kr1/intp5 si10 input serial data input to csi10 input port p31/rxd1/sda10/ intp1 slti input 16-bit timer 00, 01 input input port p52/rtc1hz/slto slto output 16-bit timer 00, 01 output input port p52/rtc1hz/slti so00 serial data output from csi00 p73/kr3/txd0 so01 serial data output from csi01 p70/kr0/intp4 so10 output serial data output from csi10 input port p30/txd1 ti00 external count clock input to 16-bit timer 00 p00 ti02 external count clock input to 16-bit timer 02 p10/to02 ti03 external count clock input to 16-bit timer 03 p11/to03 ti04 external count clock input to 16-bit timer 04 p12/to04/ rtcdiv/rtccl ti05 external count clock input to 16-bit timer 05 p13/to05 ti06 external count clock input to 16-bit timer 06 p50/to06 ti07 input external count clock input to 16-bit timer 07 input port p51/to07 to00 16-bit timer 00 output p01 to02 16-bit timer 02 output p10/ti02 to03 16-bit timer 03 output p11/ti03 to04 16-bit timer 04 output p12/ti04/ rtcdiv/rtccl to05 16-bit timer 05 output p13/ti05 to06 16-bit timer 06 output p50/ti06 to07 output 16-bit timer 07 output input port p51/ti07 txd0 serial data output from uart0 p73/kr3/so00 txd1 output serial data output from uart1 input port p30/so10 x1 ? input port p121 x2 ? resonator connection for main system clock input port p122/exclk xt1 ? input port p123 xt2 ? resonator connection for subsystem clock input port p124 exclk input external clock input for ma in system clock input port p122/x2 chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 42 (2) non-port functions (3/3): 78k0r/kd3-l function name i/o function after reset alternate function v dd ? positive power supply (port pins other than p20 to p27, p80 to p83, p150 to p152, and other than ports) ? ? av ref ? ? a/d converter and comparator reference voltage input ? positive power supply for p20 to p27, p150 to p152, p80 to p83, a/d converter, programmable gain amplifier, and comparator ? ? v ss ? ground potential (port pins other than p20 to p27, p80 to p83, p150 to p152, and other than ports) ? ? av ss ? ground potential for a/d converter, programmable gain amplifier, comparator, p20 to p27, p150 to p152 and p80 to p83 ? ? flmd0 ? flash memory programming mode setting ? ? tool0 i/o data i/o for flash memory programmer/debugger input port p40 tool1 output clock output for debugger input port p41 chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 43 2.1.3 78k0r/ke3-l (1) port functions (1/2): 78k0r/ke3-l function name i/o function after reset alternate function p00 ti00 p01 i/o port 0. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port to00 p10 ti02/to02 p11 ti03/to03 p12 ti04/to04/ rtcdiv/rtccl p13 ti05/to05 p14 ti06/to06 p15 ti07/to07 p16 ? p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p20 to p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. digital input port ani0 to ani7 p30 so10/txd1 p31 si10/rxd1/sda10/ intp1 p32 sck10/scl10/ intp2 p33 i/o port 3. 4-bit i/o port. input of p31 and p32 can be set to ttl buffer. output of p30 to p32 can be set to n-ch open-drain output (v dd tolerance). input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p40 note tool0 p41 tool1 p42 ? p43 i/o port 4. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p50 ? p51 ? p52 rtc1hz/slti/ slto p53 i/o port 5. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p60 scl0 p61 i/o port 6. 2-bit i/o port. output of p60 and p61 is n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. input port sda0 note if on-chip debugging is enabled by using an option byte, be sure to pull up the p40/tool0 pin externally. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 44 (1) port functions (2/2): 78k0r/ke3-l function name i/o function after reset alternate function p70 kr0/so01/intp4 p71 kr1/si01/intp5 p72 kr2/sck01/intp6 p73 kr3/so00/txd0 p74 kr4/si00/rxd0 p75 kr5/sck00 p76 kr6 p77 i/o port 7. 8-bit i/o port. input of p71, p72, p74, and p75 can be set to ttl buffer. output of p70, p72, p73, and p75 can be set to n-ch open-drain output (v dd tolerance). input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port kr7 p80 cmp0p/intp3/ pgai p81 cmp0m p82 cmp1p/intp7 p83 i/o port 8. 4-bit i/o port. inputs/output can be specified in 1-bit units. inputs of p80 to p83 can be set as comparator inputs or programmable gain amplifier inputs. analog input cmp1m p120 i/o intp0/exlvi p121 x1 p122 x2/exclk p123 xt1 p124 input port 12. 1-bit i/o port and 4-bit input port. for only p120, input/output can be specified in 1-bit units. for only p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2 p140 output output port pclbuz0 p141 i/o port 14. 1-bit output port and 1-bit i/o port. for only p141, input/output can be specified. for only p141, use of an on-chip pull-up resistor can be specified by a software setting. input port pclbuz1 p150 to p153 i/o port 15. 4-bit i/o port. input/output can be specified in 1-bit units. digital input port ani8 to ani11 chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 45 (2) non-port functions (1/3): 78k0r/ke3-l function name i/o function after reset alternate function ani0 to ani7 input p20 to p27 ani8 to ani11 input a/d converter analog input digital input port p150 to p153 cmp0m input input voltage on the ( ? ) side of comparator 0 p81 cmp0p input input voltage on the (+) side of comparator 0 p80/intp3/pgai cmp1m input input voltage on the ( ? ) side of comparator 1 p83 cmp1p input input voltage on the (+) side of comparator 1 analog input p82/intp7 exlvi input potential input for external low-voltage detection input port p120/intp0 intp0 p120/exlvi intp1 p31/si10/rxd1/ sda10 intp2 input port p32/sck10/scl10 intp3 analog input p80/cmp0p/pgai intp4 p70/kr0/so01 intp5 p71/kr1/si01 intp6 input port p72/kr2/sck01 intp7 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified analog input p82/cmp1p kr0 p70/so01/intp4 kr1 p71/si01/intp5 kr2 p72/sck01/intp6 kr3 p73/so00/txd0 kr4 p74/si00/rxd0 kr5 p75/sck00 kr6 p76 kr7 input key interrupt input input port p77 pclbuz0 output port p140 pclbuz1 output clock output/buzzer output input port p141 pgai input programmable gain amplifier input analog input p80/cmp0p/intp3 regc ? connecting regulator output (2.4 v) stabilization capacitance for internal operation. connect to v ss via a capacitor (0.47 to 1 f: target). ? ? rtcdiv output real-time counter clock (32 khz division) output input port p12/ti04/to04/ rtccl rtccl output real-time counter clock (32 khz original oscillation) output input port p12/ti04/to04/ rtcdiv rtc1hz output real-time counter correction clock (1 hz) output input port p52/slti/slto reset input system reset input ? ? chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 46 (2) non-port functions (2/3): 78k0r/ke3-l function name i/o function after reset alternate function rxd0 serial data input to uart0 p74/kr4/si00 rxd1 input serial data input to uart1 input port p31/si10/sda10/ intp1 sck00 clock input/output for csi00 p75/kr5 sck01 clock input/output for csi01 p72/kr2/intp6 sck10 i/o clock input/output for csi10 input port p32/scl10/intp2 scl0 i/o clock input/output for i 2 c input port p60 scl10 i/o clock input/output for simplified i 2 c input port p32/sck10/intp2 sda0 i/o serial data i/o for i 2 c input port p61 sda10 i/o serial data i/o for simplified i 2 c input port p31/si10/rxd1/ intp1 si00 serial data input to csi00 p74/kr4/rxd0 si01 serial data input to csi01 p71/kr1/intp5 si10 input serial data input to csi10 input port p31/rxd1/sda10/ intp1 slti input 16-bit timer 00, 01 input input port p52/rtc1hz/slto slto output 16-bit timer 00, 01 output input port p52/rtc1hz/slti so00 serial data output from csi00 p73/kr3/txd0 so01 serial data output from csi01 p70/kr0/intp4 so10 output serial data output from csi10 input port p30/txd1 ti00 external count clock input to 16-bit timer 00 p00 ti02 external count clock input to 16-bit timer 02 p10/to02 ti03 external count clock input to 16-bit timer 03 p11/to03 ti04 external count clock input to 16-bit timer 04 p12/to04/ rtcdiv/rtccl ti05 external count clock input to 16-bit timer 05 p13/to05 ti06 external count clock input to 16-bit timer 06 p14/to06 ti07 input external count clock input to 16-bit timer 07 input port p15/to07 to00 16-bit timer 00 output p01 to02 16-bit timer 02 output p10/ti02 to03 16-bit timer 03 output p11/ti03 to04 16-bit timer 04 output p12/ti04/ rtcdiv/rtccl to05 16-bit timer 05 output p13/ti05 to06 16-bit timer 06 output p14/ti06 to07 output 16-bit timer 07 output input port p15/ti07 txd0 serial data output from uart0 p73/kr3/so00 txd1 output serial data output from uart1 input port p30/so10 x1 ? input port p121 x2 ? resonator connection for main system clock input port p122/exclk xt1 ? input port p123 xt2 ? resonator connection for subsystem clock input port p124 exclk input external clock input for ma in system clock input port p122/x2 chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 47 (2) non-port functions (3/3): 78k0r/ke3-l function name i/o function after reset alternate function v dd ? positive power supply (p121 to p124 and other than ports (other than the reset pin and flmd0 pin)) ? ? ev dd ? positive power supply for ports (o ther than p20 to p27, p150 to p153, p80 to p83, and p121 to p124), reset pin, and flmd0 pin ? ? av ref ? ? a/d converter and comparator reference voltage input ? positive power supply for p20 to p27, p150 to p153, p80 to p83, a/d converter, programmable gain amplifier, and comparator ? ? v ss ? ground potential (p121 to p124 and other than ports (other than the reset pin and flmd0 pin)) ? ? ev ss ? ground potential for ports (other than p20 to p27, p150 to p153, and p121 to p124), reset pin, and flmd0 pin ? ? av ss ? ground potential for a/d converter, programmable gain amplifier, comparator, p20 to p27, p150 to p153 and p80 to p83 ? ? flmd0 ? flash memory programming mode setting ? ? tool0 i/o data i/o for flash memory programmer/debugger input port p40 tool1 output clock output for debugger input port p41 chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 48 2.2 description of pin functions remark the pins mounted depend on the product. see 1.4 pin configuration (top view) and 2.1 pin function list . 2.2.1 p00, p01 (port 0) p00 and p01 function as an i/o port. these pins also function as timer i/o. 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p00/ ti00 ? ? p11/to00 ? ? remark : mounted the following operation modes can be specified in 1-bit units. (1) port mode p00 and p01 function as an i/o port. p00 and p01 can be se t to input or output port in 1-bit units using port mode register 0 (pm0). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). (2) control mode p00 and p01 function as timer i/o. (a) ti00 this is the pin for inputting an external count clock/capture trigger to 16-bit timer 00. (b) to00 this is the timer output pin of 16-bit timer 00. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 49 2.2.2 p10 to p17 (port 1) p10 to p17 function as an i/o port. these pins also f unction as timer i/o and real-time counter clock output. 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p10/ti02/to02 p11/to00/ti03/ to03 p12/ti04/to04/ rtcdiv/rtccl p13/ti05/to05 p14/ti06/to06 ? note ? note ? note p15/ti07/to07 ? note ? note ? note p16 ? ? ? p17 ? ? ? note ti06/to06 and ti07/to07 are s hared with p50 and p51, respectively, in products other than the 78k0r/ke3-l. remark : mounted the following operation modes can be specified in 1-bit units. (1) port mode p10 to p17 function as an i/o port. p10 to p17 can be set to input or output port in 1- bit units using port mode register 1 (pm1). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1). (2) control mode p10 to p17 function as timer i/o and real-time counter clock output. (a) ti02 to ti07 these are the pins for inputting an external count clock/capture trigger to 16-bit timers 02 to 07. (b) to02 to to07 these are the timer output pins of 16-bit timers 02 to 07. (c) rtcdiv this is the real-time counter clo ck (32 khz division) output pin. (d) rtccl this is the real-time counter clock ( 32 khz original oscillation) output pin. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 50 2.2.3 p20 to p27 (port 2) p20 to p27 function as an i/o port. these pins also function as a/d converter analog input. 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p20/ani0 p21/ani1 p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 remark : mounted the following operation modes can be specified in 1-bit units. (1) port mode p20 to p27 function as an i/o port. p20 to p27 can be set to input or output port in 1- bit units using port mode register 2 (pm2). (2) control mode p20 to p27 function as a/d converter analog input pins (ani0 to ani7). when using these pins as analog input pins, see 11.6 (5) ani0/p20 to ani7/ p27, ani8/p150 to ani11/p153 . caution ani0/p20 to ani7/p27 are set in the digital input (general-purpose port) mode after release of reset. 2.2.4 p30 to p33 (port 3) p30 to p33 function as an i/o port. these pins also func tion as serial interface data i/o, clock i/o, and external interrupt request input. input to the p30 and p31 pins can be s pecified through a normal input buffer or a ttl input buffer in 1-bit units, using port input mode register 3 (pim3). output from the p30 to p32 pins can be specified as normal cmos output or n-ch open-drain output (v dd tolerance) in 1-bit units, using port output mode register 3 (pom3). chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 51 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p30/so10/txd1 p31/si10/rxd1/ sda10/intp1 p32/sck10/ scl10/intp2 p33 ? ? ? remark : mounted the following operation modes can be specified in 1-bit units. (1) port mode p30 to p33 function as an i/o port. p30 to p33 can be set to input or output port in 1- bit units using port mode register 3 (pm3). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). (2) control mode p30 to p33 function as serial interface data i/o, clock i/o, and external interrupt request input. (a) si10 this is a serial data input pi n of serial interface csi10. (b) so10 this is a serial data output pin of serial interface csi10. (c) sck10 this is a serial clock i/o pin of serial interface csi10. (d) txd1 this is a serial data output pin of serial interface uart1. (e) rxd1 this is a serial data input pi n of serial interface uart1. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 52 (f) sda10 this is a serial data i/o pin of serial interface for simplified i 2 c. (g) scl10 this is a serial clock i/o pin of serial interface for simplified i 2 c. (h) intp1, intp2 these are the external interrupt request input pins fo r which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. caution to use p30/so10/txd1 an d p32/sck10/scl10/intp2 as general-purpose ports, set serial communication operation setting register 02 (scr0 2) to the default status (0087h). in addition, clear port output mode register 3 (pom3) to 00h. 2.2.5 p40 to p43 (port 4) p40 to p43 function as an i/o port. these pins also fu nction as data i/o for a flas h memory programmer/debugger and clock output. 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p40/tool0 p41/tool1 p42 ? ? ? p43 ? ? ? remark : mounted the following operation modes can be specified in 1-bit units. (1) port mode p40 to p43 function as an i/o port. p40 to p43 can be set to input or output port in 1- bit units using port mode register 4 (pm4). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (pu4). be sure to connect an external pull-up resistor to p40 when on-chip debugging is enabled (by using an option byte). (2) control mode p40 to p43 function as data i/o for a flash memory programmer/debugger and clock output. (a) tool0 this is a data i/o pin for a flash memory programmer/debugger. be sure to pull up this pin externally when on-chip debugging is enabled (pulling it down is prohibited). chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 53 (b) tool1 this is a clock output pin for a debugger. when the on-chip debug function is used, p41/tool1 pin can be used as follows by the mode setting on the debugger. 1-line mode: can be used as a port (p41). 2-line mode: used as a tool1 pin a nd cannot be used as a port (p41). caution the function of the p40/tool0 pin var ies as described in (a) to (c) below. in the case of (b) or (c), make the specified connection. (a) in normal operation mode and when on-chi p debugging is disabled (ocdenset = 0) by an option byte (000c3h) => use this pin as a port pin (p40). (b) in normal operation mode and when on-chip debugging is enabled (ocdenset = 1) by an option byte (000c3h) => connect this pin to v dd via an external resistor, and a lways input a high level to the pin before reset release. (c) when on-chip debug functi on is used, or in write mode of flash memory programmer => use this pin as tool0. directly connect this pin to the on-c hip debug emulator or a flash memory programmer, or pull it up by connecting it to v dd via an external resistor. 2.2.6 p50 to p53 (port 5) p50 to p53 function as an i/o port. these pins also functi on as real-time counter correction clock output and timer i/o. 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p50/ti06/to06 p50 note p51/ti07/to07 p51 note p52/rtc1hz/ slti/slto p53 ? ? ? note ti06/to06 and ti07/to07 are shared only in the 78k0r/kc3-l and 78k0r/kd3-l. the 78k0r/ke3-l does not have a sharing function. remark : mounted the following operation modes can be specified in 1-bit units. (1) port mode p50 to p53 function as an i/o port. p50 to p53 can be set to input or output port in 1- bit units using port mode register 5 (pm5). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (pu5). chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 54 (2) control mode p50 to p53 function as real-time counter correction clock output and timer i/o. (a) rtc1hz this is the real-time counter co rrection clock (1 hz) output pin. (b) slti this is used as a pin for inputting an external count clock or a capture trigger to 16-bit timers 00 and 01, by setting the input switching control register (isc). (c) slto this is used as a timer output pin of 16-bit timers 00 and 01, by setting the input switching control register (isc). (d) ti06, ti07 these are the pins for inputting an external count clock/capture trigger to 16-bit timers 06 and 07. (e) to06, to07 these are the timer output pins of 16-bit timers 06 and 07. 2.2.7 p60 and p61 (port 6) p60 and p61 function as an i/o port. these pins also function as serial interface iica data i/o and clock i/o. 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p60/scl0 ? p61/sda0 ? remark : mounted the following operation modes can be specified in 1-bit units. (1) port mode p60 and p61 function as an i/o port. p60 and p61 can be se t to input port or output port in 1-bit units using port mode register 6 (pm6). output of p60 and p61 is n-ch open- drain output (6 v tolerance). (2) control mode p60 and p61 function as serial interface iica data i/o and clock i/o. (a) sda0 this is a serial data i/o pin of serial interface iica. (b) scl0 this is a serial clock i/o pi n of serial interface iica. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 55 2.2.8 p70 to p77 (port 7) p70 to p77 function as an i/o port. these pins also functi on as key interrupt input, se rial interface data i/o, clock i/o, and external inte rrupt request input. input to the p71, p72, p74, and p75 pins can be specified through a normal input buffer or a ttl input buffer in 1- bit units, using port input mode register 7 (pim7). output from the p70, p72, p73, and p75 pins can be spec ified as normal cmos output or n-ch open-drain output (v dd tolerance) in 1-bit units, using port output mode register 7 (pom7). 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p70/kr0/so01/ intp4 p71/kr1/si01/ intp5 p72/kr2/ sck01/intp6 p73/kr3/so00/ txd0 p74/kr4/si00/ rxd0 p75/kr5/sck00 p76/kr6 ? ? p77/kr7 ? ? remark : mounted the following operation modes can be specified in 1-bit units. (1) port mode p70 to p77 function as an i/o port. p70 to p77 can be set to input or output port in 1- bit units using port mode register 7 (pm7). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (pu7). (2) control mode p70 to p77 function as key interrupt input, serial interf ace data i/o, clock i/o, and extern al interrupt request input. (a) kr0 to kr7 these are key interrupt input pins. (b) si00, si01 these are the serial data input pin of serial interface csi00 and csi01. (c) so00, so01 these are the serial data output pin of serial interface csi00 and csi01. (d) sck00, sck01 these are the serial clock i/o pins of serial interface csi00 and csi01. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 56 (e) rxd0 this is a serial data input pi n of serial interface uart0. (f) txd0 this is a serial data output pin of serial interface uart0. (g) intp4 to intp6 these are the external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. caution to use p70/kr0/so01/intp4, p72/kr2/sck 01/intp6, p73/kr3/so00/txd0, and p75/kr5/sck00 as general-purpose ports, set serial communicat ion operation setting registers 00 and 01 (scr00 and scr01) to the default status (0087h ). in addition, cl ear port output mode register 7 (pom7) to 00h. 2.2.9 p80 to p83 (port 8) p80 to p83 function as an i/o port. these pins also functi on as input voltages on the (+) side of com parators 0 and 1, input voltages on the ( ? ) side of comparators 0 and 1, external in terrupt request inputs, and programmable gain amplifier inputs. inputs to the p80 to p83 pins must be enabled or disabled in 1-bit units using port input mode register 8 (pim8). 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p80/cmp0p/ intp3/pgai p81/cmp0m p82/cmp1p/ intp7 p83/cmp1m remark : mounted the following operation modes can be specified in 1-bit units. (1) port mode p80 to p83 function as an i/o port. p80 to p83 can be set to input port or output port in 1-bit units using port mode register 8 (pm8). (2) control mode p80 to p83 function as input voltages on the (+) si de of comparators 0 and 1, input voltages on the ( ? ) side of comparators 0 and 1, external interrupt request inputs, and programmable gain amplifier inputs. (a) cmp0p, cmp1p these are the input voltage pins on t he (+) sides of comparators 0 and 1. (b) cmp0m, cmp1m these are the input vo ltage pins on the ( ? ) sides of comparators 0 and 1. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 57 (c) intp3, intp7 these are the external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (d) pgai this is a programmable gain amplifier input pin. 2.2.10 p120 to p124 (port 12) p120 functions as an i/o port. p121 to p124 function as ant input port. these pins also function as external interrupt request input, potential input fo r external low-voltage det ection, connecting resonator for main system clock, connecting resonator for subsystem clock, and exte rnal clock input for main system clock. 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p120/intp0/ exlvi p121/x1 p122/x2/ exclk p123/xt1 p124/xt2 remark : mounted the following operation modes can be specified in 1-bit units. (1) port mode p120 functions as an i/o port. p120 can be set to input or output port using port mode register 12 (pm12). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). p121 to p124 function as an input port. (2) control mode p120 to p124 function as external interrupt request in put, potential input for exter nal low-voltage detection, connecting resonator for main system clock, connecting re sonator for subsystem clock, and external clock input for main system clock. (a) intp0 this is an external interrupt request input pin for whic h the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) exlvi this is a potential input pin for external low-voltage detection. (c) x1, x2 these are the pins for connecting a resonator for main system clock. (d) exclk this is an external clock inpu t pin for main system clock. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 58 (e) xt1, xt2 these are the pins for connecting a resonator for subsystem clock. 2.2.11 p140, p141 (port 14) p140 functions as a 1-bit output port. p141 functions as a 1-bit i/o port. these pins also function as clock/buzzer output. 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p140/pclbuz0 ? p141/pclbuz1 ? ? ? remark : mounted the following operation modes can be specified in 1-bit units. (1) port mode p140 functions as a 1-bit output port. p141 functions as a 1-bit i/o port. p141 can be set to input or output port in 1-bit units using port mode register 14 (pm14). use of an on-chip pull-up resistor can be spec ified by pull-up resistor option register 14 (pu14). (2) control mode p140 and p141 function as clock/buzzer output. (a) pclbuz0, pclbuz1 these are clock/buzzer output pins. 2.2.12 p150 to p153 (port 15) p150 to p153 function as an i/o port. these pins also function as a/d converter analog input. 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p150/ani8 p151/ani9 p152/ani10 ? p153/ani11 ? ? ? remark : mounted the following operation modes can be specified in 1-bit units. (1) port mode p150 to p153 function as an i/o port. p150 to p153 can be set to input or output port in 1-bit units using port mode register 15 (pm15). chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 59 (2) control mode p150 to p153 function as a/d converter analog input pi ns (ani8 to ani11). when using these pins as analog input pins, see 11.6 (5) ani0/p20 to ani7/ p27 and ani8/p150 to ani11/p153 . caution ani8/p150 to ani11/p153 are set in the digital input (general- purpose port) mode after release of reset. 2.2.13 av ref , av ss , v dd , ev dd , v ss , ev ss 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) av ref av ss v dd ev dd ? ? ? v ss ev ss ? ? ? (1) av ref this is the a/d converter and comparator reference voltage input pin and the positive power supply pin of p20 to p27, p150 to p153, p80 to p83, a/d converter, programmable gain amplifier, and comparator. when all pins of port 2, port 15, and port 8 are us ed as the analog port pins, make the potential of av ref be such that 1.8 v av ref v dd . when one or more of the pins of port 2, port 15, and port 8 are used as the digital port pins or when the a/d converter, programmable gain amplifier, and comparator are not used, make av ref the same potential as ev dd or v dd . (2) av ss this is the ground potential pin of a/ d converter, programmable gain amplifie r, comparator, p20 to p27, p150 to p153, and p80 to p83. even when the a/d converter, pr ogrammable gain amplifier, and comparator are not used, always use this pin with the same potential as ev ss or v ss . (3) v dd , ev dd v dd is the positive power supply pin for p121 to p124 and other than ports (other than the reset pin and flmd0 pin) note . ev dd is the positive power supply pin for ports other than those of p20 to p 27, p150 to p153, p80 to p83, and p121 to p124, as well as for the reset pin and flmd0 pin. note with products not provided with an ev dd pin, use v dd as the positive power supply pin for port pins other than p20 to p27, p150 to p153, and p80 to p83, as well as for pins other than those of ports. (4) v ss , ev ss v ss is the ground potential pin for p121 to p124 and other than ports (other than the reset pin and flmd0 pin) note . ev ss is the ground potential pin for ports other than those of p20 to p27, p150 to p153, p80 to p83, and p121 to p124, as well as for the reset pin and flmd0 pin. note with products not provided with an ev ss pin, use v ss as the ground potential pin for port pins other than p20 to p27, p150 to p153, p80 to p83, as well as for pins other than those of ports. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 60 2.2.14 reset this is the active-low system reset input pin. 2.2.15 regc this is the pin for connecting regulator output (2.4 v) stabilization capacitance for internal operation. connect this pin to v ss via a capacitor (0.47 to 1 f: target). however, when using the stop mode that has been entered since operation of the internal high-speed oscillation clock and external main system clock, 0.47 f is recommended. also, use a capacitor with good characteristics, si nce it is used to stabilize internal voltage. regc v ss caution keep the wiring length as short as possible for the broken- line part in the above figure. 2.2.16 flmd0 this is a pin for setting flash memory programming mode. perform either of the following processing. (a) in normal operation mode it is recommended to leave this pin open during normal operation. the flmd0 pin must always be kept at the v ss level before reset release but does not have to be pulled down externally because it is internally pulled down by reset. however, pulling it down must be kept selected (i.e., flmdpup = ?0?, default value) by using bit 7 (flmdpup) of the backgroun d event control register (bectl) (see 24.5 (1) back ground event control register ). to pull it down externally, use a resistor of 200 k or smaller. self programming and the rewriting of flash memory with the programmer can be prohibited using hardware, by directly connecting this pin to the v ss pin. (b) in self programming mode it is recommended to leave this pin open when using the self programming function. to pull it down externally, use a resistor of 100 k to 200 k . in the self programming mode, the setting is swit ched to pull up in the self programming library. (c) in flash memory programming mode directly connect this pin to a flash memory progr ammer when data is written by the flash memory programmer. this supplies a writing voltage of the v dd level to the flmd0 pin. the flmd0 pin does not have to be pulled down externally because it is internally pulled down by reset. to pull it down externally, use a resistor of 1 k to 200 k . chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 61 2.3 pin i/o circuits and recommended connection of unused pins table 2-3 shows the types of pin i/o circuits and the recommended connections of unused pins. table 2-3. connection of unused pins (1/3) pin name i/o circuit type i/o recommended connection of unused pins p00/ti00 8-r p01/to00 5-ag p10/ti02/to02 p11/ti03/to03 p12/ti04/to04/rtcdiv/ rtccl p13/ti05/to05 p14/ti06/to06 note 1 p15/ti07/to07 note 1 p16 p17 8-r input: independently connect to ev dd or ev ss via a resistor. output: leave open. p20/ani0 to p27/ani7 note 2 11-g input: independently connect to av ref or av ss via a resistor. output: leave open. p30/so10/txd1 5-ag p31/si10/rxd1/sda10/ intp1 p32/sck10/scl10/intp2 5-an input: independently connect to ev dd or ev ss via a resistor. output: leave open. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 62 table 2-3. connection of unused pins (2/3) pin name i/o circuit type i/o recommended connection of unused pins p60/scl0 p61/sda0 13-r input: independently connect to ev dd or ev ss via a resistor. output ? set the port output latch to 0: leave open. ? set the port output latch to 1: independently connect to ev dd or ev ss via a resistor. p70/kr0/so01/intp4 8-r input: independently connect to ev dd or ev ss via a resistor. output: leave open. chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 63 table 2-2. connection of unused pins (3/3) pin name i/o circuit type i/o recommended connection of unused pins p80/cmp0p/intp3/pgai 11-j p81/cmp0m 11-h p82/cmp1p/intp7 11-i p83/cmp1m 11-h input: independently connect to av ref or av ss via a resistor. output: leave open. p120/intp0/exlvi 8-r i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. p121/x1 note 1 p122/x2/exclk note 1 37-c p123/xt1 note 1 p124/xt2 note 1 37-b input independently connect to ev dd or ev ss via a resistor. p140/pclbuz0 3-c output leave open. p141/pclbuz1 5-ag input: independently connect to ev dd or ev ss via a resistor. output: leave open. p150/ani8 to p153/ani11 note 2 11-g i/o input: independently connect to av ref or av ss via a resistor. output: leave open. av ref ? ? chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 64 figure 2-1. pin i/o circuit list (1/3) type 2 type 2-w schmitt-triggered input with hysteresis characteristics in in pll-down enable n-ch pull-up enable p-ch ev dd ev ss schmitt-triggered input with hysteresis characteristics type 3-c type 5-ag ev dd p-ch n-ch data out ev ss pull-up enable data output disable input enable ev dd p-ch ev dd ev ss p-ch in/out n -ch type 5-an type 8-r pull-up enable data output disable p-ch ev dd ev dd ev ss p-ch in/out n -ch cmos ttl input characteristic data output disable ev dd p-ch in/out n-ch ev ss pull-up enable ev dd p-ch chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 65 figure 2-1. pin i/o circuit list (2/3) type 11-g type 11-h data output disable av ref p-ch in/out n-ch p-ch n-ch input enable + _ av ss av ss comparator series resistor string voltage data output disable av ref p-ch in/out n-ch voltage generated by internal amplifier or cmp0p (pin level) internally generated reference voltage input enable + _ av ss p-ch n-ch p-ch n-ch comparator type 11-i type 11-j data output disable av ref p-ch in/out n-ch p-ch n-ch input enable + _ av ss p-ch n-ch comparator voltage generated by internal amplifier or cmp1m (pin level) voltage generated by internal amplifier data output disable av ref p-ch n-ch p-ch n-ch + _ input enable av ss p-ch n-ch p-ch n-ch op amp + _ av ss p-ch n-ch + _ cmp1p (pin level) internally generated voltage or cmp1m (pin level) internally generated voltage or cmp0m (pin level) v ref (threshold voltage) chapter 2 pin functions preliminary user?s manual u19291ej1v0ud 66 figure 2-1. pin i/o circuit list (3/3) type 13-r type 37-b in/out n -ch data output disable ev ss xt1 input enable input enable p-ch n-ch xt2 amp enable type 37-c x1 input enable input enable p-ch n-ch x2 amp enable preliminary user?s manual u19291ej1v0ud 67 chapter 3 cpu architecture 3.1 memory space products in the 78k0r/kx3-l can access a 1 mb memory space. figures 3-1 to 3-4 show the memory maps. figure 3-1. memory map ( pd78f1000) special function register (sfr) 256 bytes general-purpose register 32 bytes ram 1 kb note 1 mirror 12 kb reserved reserved special function register (2nd sfr) 2 kb reserved flash memory 16 kb data memory space program memory space 00000h effffh f0000h f0fffh f1000h f3fffh f4000h ffa1fh ffe20h ffaffh ffb00h ffedfh ffee0h ffeffh fff00h fffffh 03fffh 04000h f07ffh f0800h 00000h 0007fh 00080h 000bfh 000c0h 000c3h 000c4h 00fffh 01000h 0107fh 01080h 010bfh 010c0h 010c3h 010c4h 03fffh vector table area 128 bytes callt table area 64 bytes program area option byte area note 2 4 bytes vector table area 128 bytes callt table area 64 bytes option byte area note 2 4 bytes program area on-chip debug security id setting area note 2 10 bytes 01fffh boot cluster 0 note 3 boot cluster 1 010cdh 010ceh on-chip debug security id setting area note 2 10 bytes 000cdh 000ceh notes 1. use of the area ffe20h to ffedfh is prohibited when using the self-programming function. since this area is used for self-programming library. 2. when boot swap is not used: set the option by tes to 000c0h to 000c3h, and the on-chip debug security ids to 000c4h to 000cdh. when boot swap is used: set the option bytes to 000c0h to 000c3h and 010c0h to 010c3h, and the on-chip debug security ids to 000c4h to 000cdh and 010c4h to 010cdh. 3. writing boot cluster 0 can be prohibited depending on the setting of security (see 24.7 security setting ). chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 68 figure 3-2. memory map ( pd78f1001, 78f1004, 78f1007) data memory space program memory space 00000h effffh f0000h f0fffh f1000h f8000h f7fffh ff8ffh ff900h ffe1fh ffe20h ffedfh ffee0h ffeffh fff00h fffffh 07fffh 08000h f07ffh f0800h 00000h 0007fh 00080h 000bfh 000c0h 000c3h 000c4h 00fffh 01000h 0107fh 01080h 010bfh 010c0h 010c3h 010c4h 07fffh vector table area 128 bytes callt table area 64 bytes program area option byte area note 2 4 bytes vector table area 128 bytes callt table area 64 bytes option byte area note 2 4 bytes program area on-chip debug security id setting area note 2 10 bytes 01fffh boot cluster 0 note 3 boot cluster 1 010cdh 010ceh on-chip debug security id setting area note 2 10 bytes 000cdh 000ceh special function register (sfr) 256 bytes general-purpose register 32 bytes ram 1.5 kb note 1 mirror 28 kb reserved reserved special function register (2nd sfr) 2 kb reserved flash memory 32 kb notes 1. use of the area ffe20h to ffedfh is prohibited when using the self-programming function. since this area is used for self-programming library. 2. when boot swap is not used: set the option by tes to 000c0h to 000c3h, and the on-chip debug security ids to 000c4h to 000cdh. when boot swap is used: set the option bytes to 000c0h to 000c3h and 010c0h to 010c3h, and the on-chip debug security ids to 000c4h to 000cdh and 010c4h to 010cdh. 3. writing boot cluster 0 can be prohibited depending on the setting of security (see 24.7 security setting ). chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 69 figure 3-3. memory map ( pd78f1002, 78f1005, 78f1008) data memory space program memory space 00000h effffh f0000h f0fffh f1000h fc000h fbfffh ff6ffh ff700h ffedfh ffee0h ffe1fh ffe20h ffeffh fff00h fffffh 0bfffh 0c000h f07ffh f0800h 00000h 0007fh 00080h 000bfh 000c0h 000c3h 000c4h 00fffh 01000h 0107fh 01080h 010bfh 010c0h 010c3h 010c4h 0bfffh vector table area 128 bytes callt table area 64 bytes program area option byte area note 2 4 bytes vector table area 128 bytes callt table area 64 bytes option byte area note 2 4 bytes program area on-chip debug security id setting area note 2 10 bytes 01fffh boot cluster 0 note 3 boot cluster 1 010cdh 010ceh on-chip debug security id setting area note 2 10 bytes 000cdh 000ceh special function register (sfr) 256 bytes general-purpose register 32 bytes ram 2 kb note 1 mirror 44 kb reserved reserved special function register (2nd sfr) 2 kb reserved flash memory 48 kb notes 1. use of the area ffe20h to ffedfh is prohibited when using the self-programming function. since this area is used for self-programming library. 2. when boot swap is not used: set the option by tes to 000c0h to 000c3h, and the on-chip debug security ids to 000c4h to 000cdh. when boot swap is used: set the option bytes to 000c0h to 000c3h and 010c0h to 010c3h, and the on-chip debug security ids to 000c4h to 000cdh and 010c4h to 010cdh. 3. writing boot cluster 0 can be prohibited depending on the setting of security (see 24.7 security setting ). chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 70 figure 3-4. memory map ( pd78f1003, 78f1006, 78f1009) data memory space program memory space 00000h effffh f0000h f0fffh f1000h ff300h ff2ffh ff700h ff6ffh ffedfh ffee0h ffe1fh ffe20h ffeffh fff00h fffffh 0ffffh 10000h f07ffh f0800h 00000h 0007fh 00080h 000bfh 000c0h 000c3h 000c4h 00fffh 01000h 0107fh 01080h 010bfh 010c0h 010c3h 010c4h 0ffffh vector table area 128 bytes callt table area 64 bytes program area option byte area note 2 4 bytes vector table area 128 bytes callt table area 64 bytes option byte area note 2 4 bytes program area on-chip debug security id setting area note 2 10 bytes 01fffh boot cluster 0 note 3 boot cluster 1 010cdh 010ceh on-chip debug security id setting area note 2 10 bytes 000cdh 000ceh special function register (sfr) 256 bytes general-purpose register 32 bytes ram 3 kb note 1 note 1 mirror 56.75 kb reserved special function register (2nd sfr) 2 kb reserved flash memory 64 kb notes 1. use of the area ffe20h to ffedfh and ff300h to ff6ffh are prohibited when using the self- programming function. since this area is used for self-programming library. 2. when boot swap is not used: set the option by tes to 000c0h to 000c3h, and the on-chip debug security ids to 000c4h to 000cdh. when boot swap is used: set the option bytes to 000c0h to 000c3h and 010c0h to 010c3h, and the on-chip debug security ids to 000c4h to 000cdh and 010c4h to 010cdh. 3. writing boot cluster 0 can be prohibited depending on the setting of security (see 24.7 security setting ). chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 71 remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-1 correspondence between address va lues and block numbers in flash memory . block 00h block 01h block 3fh 1 kb 003ffh 00400h 00000h 007ffh 0fbffh 0fc00h 0ffffh chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 72 correspondence between the address values and block numbers in the flash memory are shown below. table 3-1. correspondence between address values and block number s in flash memory address value block number address value block number address value block number address value block number 00000h to 003ffh 00h 04000h to 043ffh 10h 08000h to 083ffh 20h 0c000h to 0c3ffh 30h 00400h to 007ffh 01h 04400h to 047ffh 11h 08400h to 087ffh 21h 0c400h to 0c7ffh 31h 00800h to 00bffh 02h 04800h to 04bffh 12h 08800h to 08bffh 22h 0c800h to 0cbffh 32h 00c00h to 00fffh 03h 04c00h to 04fffh 13h 08c00h to 08fffh 23h 0cc00h to 0cfffh 33h 01000h to 013ffh 04h 05000h to 053ffh 14h 09000h to 093ffh 24h 0d000h to 0d3ffh 34h 01400h to 017ffh 05h 05400h to 057ffh 15h 09400h to 097ffh 25h 0d400h to 0d7ffh 35h 01800h to 01bffh 06h 05800h to 05bffh 16h 09800h to 09bffh 26h 0d800h to 0dbffh 36h 01c00h to 01fffh 07h 05c00h to 05fffh 17h 09c00h to 09fffh 27h 0dc00h to 0dfffh 37h 02000h to 023ffh 08h 06000h to 063ffh 18h 0a000h to 0a3ffh 28h 0e000h to 0e3ffh 38h 02400h to 027ffh 09h 06400h to 067ffh 19h 0a400h to 0a7ffh 29h 0e400h to 0e7ffh 39h 02800h to 02bffh 0ah 06800h to 06bffh 1ah 0a800h to 0abffh 2ah 0e800h to 0ebffh 3ah 02c00h to 02fffh 0bh 06c00h to 06fffh 1bh 0ac00h to 0afffh 2bh 0ec00h to 0efffh 3bh 03000h to 033ffh 0ch 07000h to 073ffh 1ch 0b000h to 0b3ffh 2ch 0f000h to 0f3ffh 3ch 03400h to 037ffh 0dh 07400h to 077ffh 1dh 0b400h to 0b7ffh 2dh 0f400h to 0f7ffh 3dh 03800h to 03bffh 0eh 07800h to 07bffh 1eh 0b800h to 0bbffh 2eh 0f800h to 0fbffh 3eh 03c00h to 03fffh 0fh 07c00h to 07fffh 1fh 0bc00h to 0bfffh 2fh 0fc00h to 0ffffh 3fh remark pd78f1000: block numbers 00h to 0fh pd78f1001, 78f1004, 78f1007: block numbers 00h to 1fh pd78f1002, 78f1005, 78f1008: block numbers 00h to 2fh pd78f1003, 78f1006, 78f1009: block numbers 00h to 3fh chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 73 3.1.1 internal program memory space the internal program memory space stores the program and table data. 78k0r/kx3-l products incorporate internal rom (flash memory), as shown below. table 3-2. intern al rom capacity internal rom part number structure capacity pd78f1000 16384 8 bits (00000h to 03fffh) pd78f1001, 78f1004, 78f1007 32768 8 bits (00000h to 07fffh) pd78f1002, 78f1005, 78f1008 49152 8 bits (00000h to 0bfffh) pd78f1003, 78f1006, 78f1009 flash memory 65536 8 bits (00000h to 0ffffh) the internal program memory space is divided into the following areas. (1) vector table area the 128-byte area 00000h to 0007fh is reserved as a ve ctor table area. the pr ogram start addresses for branch upon reset or generation of each interrupt r equest are stored in the vector table area. of the 16-bit address, the lower 8 bits are stored at ev en addresses and the higher 8 bits are stored at odd addresses. table 3-3. vector table vector table address interrupt source vector table address interrupt source 00026h intsr1 00000h reset input, poc, lvi, wdt, trap 00028h intsre1 00004h intwdti 0002ah intiica note 00006h intlvi 0002ch inttm00 00008h intp0 0002eh inttm01 0000ah intp1 00030h inttm02 0000ch intp2 00032h inttm03 0000eh intp3 00034h intad 00010h intp4 00036h intrtc 00012h intp5 00038h intrtci 00016h intcmp0 0003ah intkr 00018h intcmp1 00040h intmd 0001ah intdma0 00042h inttm04 0001ch intdma1 00044h inttm05 0001eh intst0/intcsi00 00046h inttm06 00020h intsr0/intcsi01 00048h inttm07 00022h intsre0 0004ah intp6 00024h intst1/intcsi10/intiic10 0004ch intp7 note this is not mounted onto 44-pi n products of the 78k0r/kc3-l. chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 74 (2) callt instruction table area the 64-byte area 00080h to 000bfh can st ore the subroutine entry address of a 2-byte call instruction (callt). set the subroutine entry addr ess to a value in a range of 00000h to 0ffffh (becaus e an address code is of 2 bytes). to use the boot swap function, set a callt instruction table also at 01080h to 010bfh. (3) option byte area a 4-byte area of 000c0h to 000c3h can be used as an opt ion byte area. set the option byte at 010c0h to 010c3h when the boot swap is used. for details, see chapter 23 option byte . (4) on-chip debug security id setting area a 10-byte area of 000c4h to 000cdh and 010c4h to 010cdh can be used as an on-chip debug security id setting area. set the on-chip debug security id of 10 bytes at 000c4h to 000cdh when the boot swap is not used and at 000c4h to 000cdh and 010c4h to 010c dh when the boot swap is used. for details, see chapter 25 on-chip debug function . chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 75 3.1.2 mirror area the 78k0r/kx3-l mirrors the data flash ar ea of 00000h to 0ffffh, to f0000h to fffffh. by reading data from f0000h to fffffh , the contents of the data flash c an be read with the shorter code. however, the data flash area is not mirrored to the sfr, extended sfr, ra m, and use prohibited areas. the mirror area can only be read and no instruction can be fetched from this area. the following show examples. example pd78f1001, 78f1004, 78f1007 (flash memory: 32 kb, ram: 1.5 kb) special function register (sfr) 256 bytes ram 1.5 kb general-purpose register 32 bytes special function register (2nd sfr) 2 kb reserved reserved reserved mirror flash memory (same data as 01000h to 07fffh) flash memory flash memory fffffh fff00h ffeffh ffee0h ffedfh ff900h ff8ffh f8000h f7fffh f1000h f0fffh f0800h f07ffh f0000h effffh 08000h 07fffh 01000h 00fffh 00000h chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 76 3.1.3 internal data memory space 78k0r/kx3-l products incorporate the following rams. table 3-4. internal ram capacity part number internal ram pd78f1000 1024 8 bits (ffb00h to ffeffh) pd78f1001, 78f1004, 78f1007 1536 8 bits (ff900h to ffeffh) pd78f1002, 78f1005, 78f1008 2048 8 bits (ff700h to ffeffh) pd78f1003, 78f1006, 78f1009 3072 8 bits (ff300h to ffeffh) the 32-byte area ffee0h to ffeffh is assigned to four g eneral-purpose register banks consisting of eight 8-bit registers per bank. this area can be used as a program ar ea where instructions are written and executed. however, executing instructions is disabled in the general-purpose register. the internal high-speed ram can also be used as a stack memory. cautions 1. it is prohibited to use the general- purpose register (ffee0h to ffeffh) space for fetching instructions or as a stack area. 2. while using the self-programming function, the area ffe20h to ffeffh cannot be used as stack memory. furthermore, the area ff300h to ff6ffh al so cannot be used as stack memory with the pd78f1003, 78f1006, and 78f1009. chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 77 3.1.4 special function register (sfr) area on-chip peripheral hardware s pecial function registers (sfrs) are allo cated in the area fff00h to fffffh (see table 3-5 in 3.2.4 special function registers (sfrs) ). caution do not access addresses to which sfrs are not assigned. 3.1.5 extended special function register (2 nd sfr: 2nd special function register) area on-chip peripheral hardware special function registers (2 nd sfrs) are allocated in the area f0000h to f07ffh (see table 3-6 in 3.2.5 extended special function register s (2nd sfrs: 2nd special function registers) ). sfrs other than those in th e sfr area (fff00h to fffffh) are allocated to this area. an instruction that accesses the extended sfr area, however, is 1 byte l onger than an instruction t hat accesses the sfr area. caution do not access addresses to wh ich extended sfrs are not assigned. chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 78 3.1.6 data memory addressing addressing refers to the method of specifying the address of the instruction to be ex ecuted next or the address of the register or memory relevant to the execution of instructions. several addressing modes are provided for addressing the memo ry relevant to the executi on of instructions for the 78k0r/kx3-l, based on operability and other considerations. for areas containing data memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general-purpose registers are available for use. figures 3-5 to 3-8 show co rrespondence between data memory and addressing. figure 3-5. correspondence between data memory and addressing ( pd78f1000) special function register (sfr) 256 bytes general-purpose register 32 bytes ram note 1 kb mirror 12 kb reserved reserved special function register (2nd sfr) 2 kb reserved flash memory 16 kb 00000h effffh f0000h f0fffh f1000h f3fffh f4000h ffaffh ffb00h ffedfh ffee0h ffeffh fff00h fffffh 03fffh 04000h f07ffh f0800h direct addressing register indirect addressing based addressing based indexed addressing short direct addressing sfr addressing register addressing ffe1fh ffe20h fff1fh fff20h note use of the area ffe20h to ffedfh is prohibited when using the self-programming function. since this area is used for self-programming library. chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 79 figure 3-6. correspondence between data memory and addressing ( pd78f1001, 78f1004, 78f1007) 00000h effffh f0000h f0fffh f1000h f8000h f7fffh ff8ffh ff900h ffedfh ffee0h ffeffh fff00h fffffh 07fffh 08000h f07ffh f0800h special function register (sfr) 256 bytes general-purpose register 32 bytes ram note 1.5 kb mirror 28 kb reserved reserved special function register (2nd sfr) 2 kb reserved flash memory 32 kb direct addressing register indirect addressing based addressing based indexed addressing short direct addressing sfr addressing register addressing fff1fh fff20h ffe1fh ffe20h note use of the area ffe20h to ffedfh is prohibited when using the self-programming function. since this area is used for self-programming library. chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 80 figure 3-7. correspondence between data memory and addressing ( pd78f1002, 78f1005, 78f1008) 00000h effffh f0000h f0fffh f1000h fc000h fbfffh ff6ffh ff700h ffedfh ffee0h ffeffh fff00h fffffh 0bfffh 0c000h f07ffh f0800h special function register (sfr) 256 bytes general-purpose register 32 bytes ram note 2 kb mirror 44 kb reserved reserved special function register (2nd sfr) 2 kb reserved flash memory 48 kb direct addressing register indirect addressing based addressing based indexed addressing short direct addressing sfr addressing register addressing fff1fh fff20h ffe1fh ffe20h note use of the area ffe20h to ffedfh is prohibited when using the self-programming function. since this area is used for self-programming library. chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 81 figure 3-8. correspondence between data memory and addressing ( pd78f1003, 78f1006, 78f1009) 00000h effffh f0000h f0fffh f1000h ff300h ff2ffh ffedfh ffee0h ffeffh fff00h fffffh 0ffffh 10000h f07ffh f0800h special function register (sfr) 256 bytes general-purpose register 32 bytes ram note 3 kb mirror 56.75 kb reserved special function register (2nd sfr) 2 kb reserved flash memory 64 kb direct addressing register indirect addressing based addressing based indexed addressing short direct addressing sfr addressing register addressing fff1fh fff20h ffe1fh ffe20h note use of the area ffe20h to ffedfh and ff300h to ff6ffh are prohibited when using the self- programming function. since this area is used for self-programming library. chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 82 3.2 processor registers the 78k0r/kx3-l products incorporat e the following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 20-bit regist er that holds the address information of the next program to be executed. in normal operation, pc is automatically incremented acco rding to the number of byte s of the instruction to be fetched. when a branch instruction is execut ed, immediate data and regi ster contents are set. reset signal generation sets the reset vector table va lues at addresses 0000h and 0001h to the program counter. figure 3-9. format of program counter 19 pc 0 (2) program status word (psw) the program status word is an 8-bit r egister consisting of various flags set/reset by instruction execution. program status word contents are st ored in the stack area upon vectored in terrupt request is acknowledged or push psw instruction execution and are restored upon ex ecution of the retb, reti and pop psw instructions. reset signal generation sets psw to 06h. figure 3-10. format of program status word ie z rbs1 ac rbs0 isp0 cy 70 isp1 psw (a) interrupt enable flag (ie) this flag controls the interrupt reques t acknowledge operations of the cpu. when 0, the ie flag is set to the interrupt disabled (di) state, and all maskable interrupt requests are disabled. when 1, the ie flag is set to the interrupt enabled (ei) state and interrupt request acknowledgment is controlled with an in-service priority flag (isp1, isp0 ), an interrupt mask flag for various interrupt sources, and a priority specification flag. the ie flag is reset (0) upon di instruction executi on or interrupt acknowledgment and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is se t (1). it is reset (0 ) in all other cases. (c) register bank select flags (rbs0, rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information that indicates t he register bank selected by sel rbn instruction execution is stored. chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 83 (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bi t 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flags (isp1, isp0) this flag manages the priority of acknowledgeable maskabl e vectored interrupts. vectored interrupt requests specified lower than the value of i sp0 and isp1 by a priority specif ication flag register (prn0l, prn0h, prn1l, prn1h, prn2l, prn2h) (see 16.3 (3) ) can not be acknowledged. actual request acknowledgment is controlled by the interrupt enable flag (ie). remark n = 0, 1 (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal ram area can be set as the stack area. figure 3-11. format of stack pointer 15 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. each stack operation saves data as shown in figure 3-12. caution 1. since reset signal generation makes the sp c ontents undefined, be sure to initialize the sp before using the stack. 2. it is prohibited to use the general-purpose register (ffee0 h to ffeffh) space as a stack area. 3. while using the self-programming function, the area ffe20h to ffeffh cannot be used as stack memory. furthermore, the area ff300h to ff6ffh also cannot be used as stack memory with the pd78f1003, 78f1006, and 78f1009. chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 84 figure 3-12. data to be saved to stack memory pc7 to pc0 pc15 to pc8 pc19 to pc16 psw interrupt, brk instruction sp sp ? 4 sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp call, callt instructions register pair lower register pair higher push rp instruction sp sp ? 2 sp ? 2 sp ? 1 sp (4-byte stack) (4-byte stack) pc7 to pc0 pc15 to pc8 pc19 to pc16 00h sp sp ? 4 sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp 00h psw push rp instruction sp sp ? 2 sp ? 2 sp ? 1 sp 3.2.2 general-purpose registers general-purpose registers are mapped at particular addresses (ffee0h to ffeffh) of the data memory. the general-purpose registers consists of 4 bank s, each bank consisting of eight 8-bit r egisters (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, and two 8-bit r egisters can also be used in a pair as a 16-bit register (ax, bc, de, and hl). these registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instructi on execution are set by the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program ca n be created by switching between a register for normal processing and a register for interrupts for each bank. caution it is prohibited to u se the general-purpose register (ff ee0h to ffeffh) space for fetching instructions or as a stack area. chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 85 figure 3-13. configuration of general-purpose registers (a) function name register bank 0 register bank 1 register bank 2 register bank 3 ffeffh ffef8h ffee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing ffef0h ffee8h (b) absolute name register bank 0 register bank 1 register bank 2 register bank 3 ffeffh ffef8h ffee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing ffef0h ffee8h chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 86 3.2.3 es and cs registers the es register is used for data acce ss and the cs register is used to specify the higher address when a branch instruction is executed. the default value of the es register after reset is 0fh, and that of the cs register is 00h. figure 3-14. configuration of es and cs registers 0 0 0 0 es3 es2 es1 es0 70 es 6 5 4 3 21 0 0 0 0 cs3 cp2 cp1 cp0 70 cs 6 5 4 3 21 chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 87 3.2.4 special function registers (sfrs) unlike a general-purpose register, each sfr has a special function. sfrs are allocated to the fff00h to fffffh area. sfrs can be manipulated like general-purpose regist ers, using operation, transfer, and bit manipulation instructions. the manipulable bit units, 1, 8, and 16, depe nd on the sfr type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved by the assembler for t he 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved by the assembler for t he 16-bit manipulation instruction operand (sfrp). when specifying an address, describe an even address. table 3-5 gives a list of the sfrs. the meani ngs of items in the table are as follows. ? symbol symbol indicating the address of a special function register. it is a reserved word in the ra78k0r, and is defined as an sfr variable using the #pragma sfr di rective in the cc78k0r. when using the ra78k0r, id78k0r-qb, and sm+ for 78k0r, symbols c an be written as an instruction operand. ? r/w indicates whether the corresponding sfr can be read or written. r/w: read/write enable r: read only w: write only ? manipulable bit units ? ? indicates the manipulable bit unit (1, 8, or 16). ? ? ? indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset signal generation. caution do not access addresses to wh ich extended sfrs are not assigned. remark for extended sfrs (2nd sfrs), see 3.2.5 extended special functi on registers (2nd sfrs: 2nd special function registers) . chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 88 table 3-5. sfr list (1/4) manipulable bit range address special function regist er (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/kc3-l (44-pin) 78k0r/kc3-l (48-pin) 78k0r/kd3-l 78k0r/ke3-l fff00h port register 0 p0 r/w ? 00h ? ? fff01h port register 1 p1 r/w ? 00h fff02h port register 2 p2 r/w ? 00h fff03h port register 3 p3 r/w ? 00h fff04h port register 4 p4 r/w ? 00h fff05h port register 5 p5 r/w ? 00h fff06h port register 6 p6 r/w ? 00h ? fff07h port register 7 p7 r/w ? 00h fff08h port register 8 p8 r/w ? 00h fff0ch port register 12 p12 r/w ? undefined fff0eh port register 14 p14 r/w ? 00h ? fff0fh port register 15 p15 r/w ? 00h fff10h txd0/ sio00 ? fff11h serial data register 00 ? sdr00 r/w ? ? 0000h fff12h rxd0/ sio01 ? fff13h serial data register 01 ? sdr01 r/w ? ? 0000h fff18h fff19h timer data register 00 tdr00 r/w ? ? 0000h fff1ah fff1bh timer data register 01 tdr01 r/w ? ? 0000h fff1eh 10-bit a/d conversion result register adcr r ? ? 0000h fff1fh 8-bit a/d conversion result register adcrh r ? ? 00h fff20h port mode register 0 pm0 r/w ? ffh ? ? fff21h port mode register 1 pm1 r/w ? ffh fff22h port mode register 2 pm2 r/w ? ffh fff23h port mode register 3 pm3 r/w ? ffh fff24h port mode register 4 pm4 r/w ? ffh fff25h port mode register 5 pm5 r/w ? ffh fff26h port mode register 6 pm6 r/w ? ffh ? fff27h port mode register 7 pm7 r/w ? ffh fff28h port mode register 8 pm8 r/w ? ffh fff2ch port mode register 12 pm12 r/w ? ffh fff2eh port mode register 14 pm14 r/w ? feh ? ? ? fff2fh port mode register 15 pm15 r/w ? ffh fff30h a/d converter mode register adm r/w ? 00h chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 89 table 3-5. sfr list (2/4) manipulable bit range address special function regi ster (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/kc3-l (44-pin) 78k0r/kc3-l (48-pin) 78k0r/kd3-l 78k0r/ke3-l fff31h analog input channel specification register ads r/w ? 00h fff37h key return mode register krm r/w ? 00h fff38h external interrupt rising edge enable register 0 egp0 r/w ? 00h fff39h external interrupt falling edge enable register 0 egn0 r/w ? 00h fff3ch input switch control register isc r/w ? 00h fff3eh timer input select register 0 tis0 r/w ? 00h fff44h txd1/ sio10 sdr02 ? fff45h serial data register 02 ? r/w ? ? 0000h fff46h rxd1 sdr03 ? fff47h serial data register 03 ? r/w ? ? 0000h fff50h iica shift register iica r/w ? ? 00h ? fff51h iica status register iics r ? 00h ? fff52h iica flag register iicf r/w ? 00h ? fff64h fff65h timer data register 02 tdr02 r/w ? ? 0000h fff66h fff67h timer data register 03 tdr03 r/w ? ? 0000h fff68h fff69h timer data register 04 tdr04 r/w ? ? 0000h fff6ah fff6bh timer data register 05 tdr05 r/w ? ? 0000h fff6ch fff6dh timer data register 06 tdr06 r/w ? ? 0000h fff6eh fff6fh timer data register 07 tdr07 r/w ? ? 0000h fff90h fff91h sub-count register rsubc r ? ? 0000h fff92h second count register sec r/w ? ? 00h fff93h minute count register min r/w ? ? 00h fff94h hour count register hour r/w ? ? 12h note fff95h week count register week r/w ? ? 00h fff96h day count register day r/w ? ? 01h fff97h month count register month r/w ? ? 01h note the value of this register is 00h if the ampm bit (bit 3 of the rtcc0 register) is set to 1 after reset. chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 90 table 3-5. sfr list (3/4) manipulable bit range address special function regist er (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/kc3-l (44-pin) 78k0r/kc3-l (48-pin) 78k0r/kd3-l 78k0r/ke3-l fff98h year count register year r/w ? ? 00h fff99h watch error correction register subcud r/w ? ? 00h fff9ah alarm minute register alarmwm r/w ? ? 00h fff9bh alarm hour register alarmwh r/w ? ? 12h fff9ch alarm week register alarmww r/w ? ? 00h fff9dh real-time counter control register 0 rtcc0 r/w ? 00h fff9eh real-time counter control register 1 rtcc1 r/w ? 00h fff9fh real-time counter control register 2 rtcc2 r/w ? 00h fffa0h clock operation mode control register cmc r/w ? ? 00h fffa1h clock operation status control register csc r/w ? c0h fffa2h oscillation stabilization time counter status register ostc r ? 00h fffa3h oscillation stabilization time select register osts r/w ? ? 07h fffa4h clock control register ckc r/w ? 09h fffa5h clock output select register 0 cks0 r/w ? 00h fffa6h clock output select register 1 cks1 r/w ? 00h fffa8h reset control flag register resf r ? ? undefined note 1 fffa9h low-voltage detection register lvim r/w ? 00h note 2 fffaah low-voltage detection level select register lvis r/w ? 0eh note 3 fffabh watchdog timer enable register wdte r/w ? ? 1a/9a note 4 fffb0h dma sfr address register 0 dsa0 r/w ? ? 00h fffb1h dma sfr address register 1 dsa1 r/w ? ? 00h fffb2h dma ram address register 0l dra0l dra0 r/w ? 00h fffb3h dma ram address register 0h dra0h r/w ? 00h fffb4h dma ram address register 1l dra1l dra1 r/w ? 00h fffb5h dma ram address register 1h dra1h r/w ? 00h fffb6h dma byte count register 0l dbc0l dbc0 r/w ? 00h fffb7h dma byte count register 0h dbc0h r/w ? 00h fffb8h dma byte count register 1l dbc1l dbc1 r/w ? 00h fffb9h dma byte count register 1h dbc1h r/w ? 00h fffbah dma mode control register 0 dmc0 r/w ? 00h fffbbh dma mode control register 1 dmc1 r/w ? 00h fffbch dma operation control register 0 drc0 r/w ? 00h fffbdh dma operation control register 1 drc1 r/w ? 00h notes 1. the reset value of resf varies depending on the reset source. 2. the reset value of lvim varies depending on the reset source and the setting of the option byte. 3. the reset value of lvis varies depending on the reset source. 4. the reset value of wdte is determined by the setting of the option byte. chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 91 table 3-5. sfr list (4/4) manipulable bit range address special function regi ster (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/kc3-l (44-pin) 78k0r/kc3-l (48-pin) 78k0r/kd3-l 78k0r/ke3-l fffbeh back ground event control register bectl r/w ? 00h fffc0h ? pfcmd note ? ? ? ? undefined fffc2h ? pfs note ? ? ? ? undefined fffc4h ? flpmc note ? ? ? ? undefined fffd0h if2l if2 fffd1h interrupt request flag register 2 ? r/w ? ? 0000h fffd4h mk2l mk2 fffd5h interrupt mask flag register 2 ? r/w ? ? ffffh fffd8h pr02l pr02 fffd9h priority specificati on flag register 02 ? r/w ? ? ffffh fffdch pr12l pr12 fffddh priority specificati on flag register 12 ? r/w ? ? ffffh fffe0h interrupt request flag register 0l if0l if0 r/w 00h fffe1h interrupt request flag register 0h if0h r/w 00h fffe2h interrupt request flag register 1l if1l if1 r/w 00h fffe3h interrupt request flag register 1h if1h r/w 00h fffe4h interrupt mask flag register 0l mk0l mk0 r/w ffh fffe5h interrupt mask flag register 0h mk0h r/w ffh fffe6h interrupt mask flag register 1l mk1l mk1 r/w ffh fffe7h interrupt mask flag register 1h mk1h r/w ffh fffe8h priority specification flag register 00l pr00l pr00 r/w ffh fffe9h priority specification flag register 00h pr00h r/w ffh fffeah priority specification flag register 01l pr01l pr01 r/w ffh fffebh priority specification flag register 01h pr01h r/w ffh fffech priority specification flag register 10l pr10l pr10 r/w ffh fffedh priority specification flag register 10h pr10h r/w ffh fffeeh priority specification flag register 11l pr11l pr11 r/w ffh fffefh priority specification flag register 11h pr11h r/w ffh ffff0h ffff1h multiplication/division data register a (l) mdal/mula r/w ? ? 0000h ffff2h ffff3h multiplication/division data register a (h) mdah/mulb r/w ? ? 0000h ffff4h ffff5h multiplication/division data register b (h) mdbh/muloh r/w ? ? 0000h ffff6h ffff7h multiplication/division data register b (l) mdbl/mulol r/w ? ? 0000h note do not directly operate this sfr, because it is to be used in the self programming library. remark for extended sfrs (2nd sfrs), see table 3-6 extended sfr (2nd sfr) list . chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 92 3.2.5 extended special function registers (2nd sfrs: 2nd special function registers) unlike a general-purpose register, each extended sfr (2nd sfr) has a special function. extended sfrs are allocated to the f0 000h to f07ffh area. sfrs other than those in the sfr area (fff00h to fffffh) are allocated to this area. an instruction that accesse s the extended sfr area, however, is 1 byte longer than an instruction that accesses the sfr area. extended sfrs can be manipulated like general-purpose regist ers, using operation, trans fer, and bit manipulation instructions. the manipulable bit units, 1, 8, and 16, depe nd on the sfr type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved by the assembler for the 1- bit manipulation instruction operand (!addr16.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved by the assembler for t he 8-bit manipulation instruction operand (!addr16). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (!addr16). when specifying an address, describe an even address. table 3-6 gives a list of the ext ended sfrs. the meanings of item s in the table are as follows. ? symbol symbol indicating the address of an extended sfr. it is a reserved word in the ra78k0r, and is defined as an sfr variable using the #pragma sfr di rective in the cc78k0r. when using the ra78k0r, id78k0r-qb, and sm+ for 78k0r, symbols can be written as an instruction operand. ? r/w indicates whether the corresponding extended sfr can be read or written. r/w: read/write enable r: read only w: write only ? manipulable bit units ? ? indicates the manipulable bit unit (1, 8, or 16). ? ? ? indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset signal generation. caution do not access addresses to wh ich extended sfrs are not assigned. remark for sfrs in the sfr area, see 3.2.4 special functi on registers (sfrs) . chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 93 table 3-6. extended sfr (2nd sfr) list (1/4) manipulable bit range address special function regi ster (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/kc3-l (44-pin) 78k0r/kc3-l (48-pin) 78k0r/kd3-l 78k0r/ke3-l f0017h a/d port configuration register adpc r/w ? ? 10h f0030h pull-up resistor option register 0 pu0 r/w ? 00h ? ? f0031h pull-up resistor option register 1 pu1 r/w ? 00h f0033h pull-up resistor option register 3 pu3 r/w ? 00h f0034h pull-up resistor option register 4 pu4 r/w ? 00h f0035h pull-up resistor option register 5 pu5 r/w ? 00h f0037h pull-up resistor option register 7 pu7 r/w ? 00h f003ch pull-up resistor option register 12 pu12 r/w ? 00h f003eh pull-up resistor option register 14 pu14 r/w ? 00h ? ? ? f0043h port input mode register 3 pim3 r/w ? 00h f0047h port input mode register 7 pim7 r/w ? 00h f0048h port input mode register 8 pim8 r/w ? 00h f0053h port output mode register 3 pom3 r/w ? 00h f0057h port output mode register 7 pom7 r/w ? 00h f0060h noise filter enable register 0 nfen0 r/w ? 00h f0061h noise filter enable register 1 nfen1 r/w ? 00h f0062h noise filter enable register 2 nfen2 r/w ? 00h f00e0h multiplication/division data register c (l) mdcl r ? ? 0000h f00e2h multiplication/division data register c (h) mdch r ? ? 0000h f00e8h multiplication/division control register mduc r/w ? 00h f00f0h peripheral enable register 0 per0 r/w ? 00h f00f1h peripheral enable register 1 per1 r/w ? 00h f00f2h peripheral enable register 2 per2 r/w ? 00h f00f3h operation speed mode control register osmc r/w ? ? 00h f00f4h regulator mode control register rmc r/w ? ? 00h f00f6h 20 mhz internal high-speed oscillation control register dscctl r/w ? 00h f00feh bcd adjust result register bcdadj r ? ? 00h f0100h ssr00l ? f0101h serial status register 00 ? ssr00 r ? ? 0000h f0102h ssr01l ? f0103h serial status register 01 ? ssr01 r ? ? 0000h f0104h ssr02l ? f0105h serial status register 02 ? ssr02 r ? ? 0000h f0106h ssr03l ? f0107h serial status register 03 ? ssr03 r ? ? 0000h f0108h sir00l ? f0109h serial flag clear trigger register 00 ? sir00 r/w ? ? 0000h f010ah sir01l ? f010bh serial flag clear trigger register 01 ? sir01 r/w ? ? 0000h chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 94 table 3-6. extended sfr (2nd sfr) list (2/4) manipulable bit range address special function regist er (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/kc3-l (44-pin) 78k0r/kc3-l (48-pin) 78k0r/kd3-l 78k0r/ke3-l f010ch sir02l ? f010dh serial flag clear trigger register 02 ? sir02 r/w ? ? 0000h f010eh sir03l ? f010fh serial flag clear trigger register 03 ? sir03 r/w ? ? 0000h f0110h f0111h serial mode register 00 smr00 r/w ? ? 0020h f0112h f0113h serial mode register 01 smr01 r/w ? ? 0020h f0114h f0115h serial mode register 02 smr02 r/w ? ? 0020h f0116h f0117h serial mode register 03 smr03 r/w ? ? 0020h f0118h f0119h serial communication operation setting register 00 scr00 r/w ? ? 0087h f011ah f011bh serial communication operation setting register 01 scr01 r/w ? ? 0087h f011ch f011dh serial communication operation setting register 02 scr02 r/w ? ? 0087h f011eh f011fh serial communication operation setting register 03 scr03 r/w ? ? 0087h f0120h se0l f0121h serial channel enable status register 0 ? se0 r ? ? 0000h f0122h ss0l f0123h serial channel start register 0 ? ss0 r/w ? ? 0000h f0124h st0l f0125h serial channel stop register 0 ? st0 r/w ? ? 0000h f0126h sps0l ? f0127h serial clock select register 0 ? sps0 r/w ? ? 0000h f0128h f0129h serial output register 0 so0 r/w ? ? 0f0fh f012ah soe0l f012bh serial output enable register 0 ? soe0 r/w ? ? 0000h f0134h sol0l ? f0135h serial output level register 0 ? sol0 r/w ? ? 0000h f0180h f0181h timer counter register 00 tcr00 r ? ? ffffh f0182h f0183h timer counter register 01 tcr01 r ? ? ffffh f0184h f0185h timer counter register 02 tcr02 r ? ? ffffh chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 95 table 3-6. extended sfr (2nd sfr) list (3/4) manipulable bit range address special function regi ster (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/kc3-l (44-pin) 78k0r/kc3-l (48-pin) 78k0r/kd3-l 78k0r/ke3-l f0186h f0187h timer counter register 03 tcr03 r ? ? ffffh f0188h f0189h timer counter register 04 tcr04 r ? ? ffffh f018ah f018bh timer counter register 05 tcr05 r ? ? ffffh f018ch f018dh timer counter register 06 tcr06 r ? ? ffffh f018eh f018fh timer counter register 07 tcr07 r ? ? ffffh f0190h f0191h timer mode register 00 tmr00 r/w ? ? 0000h f0192h f0193h timer mode register 01 tmr01 r/w ? ? 0000h f0194h f0195h timer mode register 02 tmr02 r/w ? ? 0000h f0196h f0197h timer mode register 03 tmr03 r/w ? ? 0000h f0198h f0199h timer mode register 04 tmr04 r/w ? ? 0000h f019ah f019bh timer mode register 05 tmr05 r/w ? ? 0000h f019ch f019dh timer mode register 06 tmr06 r/w ? ? 0000h f019eh f019fh timer mode register 07 tmr07 r/w ? ? 0000h f01a0h f01a1h timer status register 00 tsr00 r ? ? 0000h f01a2h f01a3h timer status register 01 tsr01 r ? ? 0000h f01a4h f01a5h timer status register 02 tsr02 r ? ? 0000h f01a6h f01a7h timer status register 03 tsr03 r ? ? 0000h f01a8h f01a9h timer status register 04 tsr04 r ? ? 0000h f01aah f01abh timer status register 05 tsr05 r ? ? 0000h f01ach f01adh timer status register 06 tsr06 r ? ? 0000h chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 96 table 3-6. extended sfr (2nd sfr) list (4/4) manipulable bit range address special function regist er (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/kc3-l (44-pin) 78k0r/kc3-l (48-pin) 78k0r/kd3-l 78k0r/ke3-l f01aeh f01afh timer status register 07 tsr07 r ? ? 0000h f01b0h f01b1h timer channel enable status register 0 te0 r ? ? 0000h f01b2h f01b3h timer channel start register 0 ts0 r/w ? ? 0000h f01b4h f01b5h timer channel stop register 0 tt0 r/w ? ? 0000h f01b6h f01b7h timer clock select register 0 tps0 r/w ? ? 0000h f01b8h f01b9h timer output register 0 to0 r/w ? ? 0000h f01bah f01bbh timer output enable register 0 toe0 r/w ? ? 0000h f01bch f01bdh timer output level register 0 tol0 r/w ? ? 0000h f01beh f01bfh timer output mode register 0 tom0 r/w ? ? 0000h f0230h iica control register 0 iicctl0 r/w ? 00h ? f0231h iica control register 1 iicctl1 r/w ? 00h ? f0232h iica low-level width setting register iicwl r/w ? ? ffh ? f0233h iica high-level width setting register iicwh r/w ? ? ffh ? f0234h slave address register sva r/w ? ? 00h ? f0240h programmable gain amplifier control register oam r/w ? 00h f0241h comparator 0 control register c0ctl r/w ? 00h f0242h comparator 0 internal reference voltage setting register c0rvm r/w ? 00h f0243h comparator 1 control register c1ctl r/w ? 00h f0244h comparator 1 internal reference voltage setting register c1rvm r/w ? 00h remark for sfrs in the sfr area, see table 3-5 sfr list . chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 97 3.3 instruction address addressing 3.3.1 relative addressing [function] relative addressing stores in the progr am counter (pc) the result of adding a displacement value included in the instruction word (signed complement data: ? 128 to +127 or ? 32768 to +32767) to the program counter (pc)?s value (the start address of the next instruction), and s pecifies the program address to be used as the branch destination. relative addressing is applied only to branch instructions. figure 3-15. outline of relative addressing op code pc displace 8/16 bits 3.3.2 immediate addressing [function] immediate addressing stores immediate da ta of the instruction word in t he program counter, and specifies the program address to be used as the branch destination. for immediate addressing, call !!addr20 or br !!addr20 is used to specify 20-bit addresses and call !addr16 or br !addr16 is used to specify 16-bit addresses. 0000 is set to the higher 4 bits when specifying 16-bit addresses. figure 3-16. example of call !!addr20/br !!addr20 op code pc low addr. high addr. seg addr. figure 3-17. example of call !addr16/br !addr16 op code pc s low addr. high addr. pc pc h pc l 0000 chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 98 3.3.3 table indirect addressing [function] table indirect addressing specifies a table address in the callt table area (0080h to 00bfh) with the 5-bit immediate data in the instruction word, stores the cont ents at that table address a nd the next address in the program counter (pc) as 16-bit data, and specifies the program address. table indirect addressing is applied only for callt instructions. in the 78k0r microcontrollers, branc hing is enabled only to the 64 kb space from 00000h to 0ffffh. figure 3-18. outline of table indirect addressing low addr. high addr. 0 0000 op code 00000000 10 table address pc s pc pc h pc l memory chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 99 3.3.4 register direct addressing [function] register direct addressing stores in the program counter (pc) the cont ents of a general-purpose register pair (ax/bc/de/hl) and cs register of the current register bank specified with t he instruction word as 20-bit data, and specifies the program address. regi ster direct addressing can be applied only to the call ax, bc, de, hl, and br ax instructions. figure 3-19. outline of register direct addressing op code pc s pc pc h pc l cs rp chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 100 3.4 addressing for processing data addresses 3.4.1 implied addressing [function] instructions for accessing registers (such as accumulators ) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word. [operand format] because implied addressing can be automatically empl oyed with an instruction, no particular operand format is necessary. implied addressing can be applied only to mulu x. figure 3-20. outline of implied addressing a register op code memory 3.4.2 register addressing [function] register addressing accesses a general-purpose register as an operand. the instruction word of 3-bit long is used to select an 8-bit register and the instruction word of 2-bit long is used to select a 16-bit register. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl figure 3-21. outline of register addressing register op code memory chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 101 3.4.3 direct addressing [function] direct addressing uses immediate data in the instructio n word as an operand address to directly specify the target address. [operand format] identifier description addr16 label or 16-bit immediate dat a (only the space from f0000h to fffffh is specifiable) es: addr16 label or 16-bit immediate data (higher 4- bit addresses are specified by the es register) figure 3-22. example of addr16 target memory op code memory low addr. high addr. fffffh f0000h figure 3-23. example of es:addr16 op code memory low addr. high addr. fffffh 00000h target memory es chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 102 3.4.4 short direct addressing [function] short direct addressing directly specif ies the target addresses using 8-bit data in the instruction word. this type of addressing is applied only to the space from ffe20h to fff1fh. [operand format] identifier description saddr label, ffe20h to fff1fh immediate data, or 0fe20h to 0ff1fh immediate data (only the space from ffe20h to fff1fh is specifiable) saddrp label, ffe20h to fff1fh immediate data, or 0f e20h to 0ff1fh immediate data (even address only) (only the space from ffe20h to fff1fh is specifiable) figure 3-24. outline of short direct addressing op code memory saddr fff1fh ffe20h saddr remark saddr and saddrp are used to describe the values of addresses fe20h to ff1fh with 16-bit immediate data (higher 4 bits of actual address ar e omitted), and the values of addresses ffe20h to fff1fh with 20-bit immediate data. regardless of whether saddr or saddrp is used, addresses within the space from ffe20h to fff1fh are specified for the memory. chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 103 3.4.5 sfr addressing [function] sfr addressing directly specifies the target sfr addresses us ing 8-bit data in the instruction word. this type of addressing is applied only to t he space from fff00h to fffffh. [operand format] identifier description sfr sfr name sfrp 16-bit-manipulatable sf r name (even address only) figure 3-25. outline of sfr addressing op code memory sfr fffffh fff00h sfr chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 104 3.4.6 register indirect addressing [function] register indirect addressing directly specifies the target addresses using the contents of t he register pair specified with the instruction word as an operand address. [operand format] identifier description ? [de], [hl] (only the space from f0000h to fffffh is specifiable) ? es:[de], es:[hl] (higher 4-bit addresses are specified by the es register) figure 3-26. example of [de], [hl] target memory op code memory rp fffffh f0000h figure 3-27. example of es:[de], es:[hl] op code memory fffffh 00000h target memory es rp chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 105 3.4.7 based addressing [function] based addressing uses the contents of a register pair specifi ed with the instruction word as a base address, and 8-bit immediate data or 16-bit immediate data as offset dat a. the sum of these val ues is used to specify the target address. [operand format] identifier description ? [hl + byte], [de + byte], [sp + byte] (only the space from f0000h to fffffh is specifiable) ? word[b], word[c] (only the space from f0000h to fffffh is specifiable) ? word[bc] (only the space from f0 000h to fffffh is specifiable) ? es:[hl + byte], es:[de + byte] (higher 4-bit addresses are specified by the es register) ? es:word[b], es:word[c] (higher 4-bit addresses are specified by the es register) ? es:word[bc] (higher 4-bit addresses are specified by the es register) figure 3-28. example of [sp+byte] target memory op code memory byte fffffh f0000h sp chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 106 figure 3-29. example of [hl + byte], [de + byte] target memory op code memory byte fffffh f0000h rp (hl/de) figure 3-30. example of word[b], word[c] target memory memory fffffh f0000h r (b/c) op code low addr. high addr. figure 3-31. example of word[bc] target memory memory fffffh f0000h rp (bc) op code low addr. high addr. chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 107 figure 3-32. example of es :[hl + byte], es:[de + byte] op code byte rp (hl/de) memory fffffh 00000h target memory es figure 3-33. example of es:word[b], es:word[c] r (b/c) memory fffffh 00000h target memory es op code low addr. high addr. figure 3-34. example of es:word[bc] rp (bc) memory fffffh 00000h target memory es op code low addr. high addr. chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 108 3.4.8 based indexed addressing [function] based indexed addressing uses the content s of a register pair specified with the instruction word as the base address, and the content of the b regist er or c register similarly specified with the instruction word as offset address. the sum of these values is used to specify the target address. [operand format] identifier description ? [hl+b], [hl+c] (only the space from f0000h to fffffh is specifiable) ? es:[hl+b], es:[hl+c] (higher 4-bit addres ses are specified by the es register) figure 3-35. example of [hl+b], [hl+c] target memory memory fffffh f0000h r (b/c) rp (hl) op code figure 3-36. example of es:[hl+b], es:[hl+c] r (b/c) op code rp (hl) es memory fffffh 00000h target memory chapter 3 cpu architecture preliminary user?s manual u19291ej1v0ud 109 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing is automatically employed when the push, pop, subrout ine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. stack addressing is applied only to the internal ram area. [operand format] identifier description ? push ax/bc/de/hl pop ax/bc/de/hl call/callt ret brk retb (interrupt request generated) reti preliminary user?s manual u19291ej1v0ud 110 chapter 4 port functions 4.1 port functions pin i/o buffer power supplies depend on the product. the relationship between t hese power supplies and the pins is shown below. table 4-1. pin i/o buffer power supplies (av ref , v dd ) ? 78k0r/kc3-l: 44-pin plastic lqfp (10x10) 48-pin plastic tqfp (fine pitch) (7x7) ? 78k0r/kd3-l: 52-pin plastic lqfp (10x10) power supply corresponding pins av ref p20 to p27, p150 to p152 note , p80 to p83 v dd ? port pins other than p20 to p27, p150 to p152 note , p80 to p83 ? pins other than port pins note 44-pin products of the 78k0r/kc3-l do not have a p152 pin. table 4-2. pin i/o buffer power supplies (av ref , ev dd , v dd ) ? 78k0r/ke3-l: 64-pin plastic fbga (5x5) 64-pin plastic tqfp (fine pitch) (7x7) 64-pin plastic lqfp (fine pitch) (10x10) 64-pin plastic lqfp (12x12) power supply corresponding pins av ref p20 to p27, p150 to p153, p80 to p83 ev dd ? port pins other than p20 to p27, p150 to p153, p80 to p83, and p121 to p124 ? reset pin and flmd0 pin v dd ? p121 to p124 ? pins other than port pins (other than the reset pin and flmd0 pin) 78k0r/kx3-l microcontrollers are provided with digital i/o ports, which enable variety of control operations. the functions of each port are shown in table 4-3. in addition to the func tion as digital i/o ports, these ports have several alternate f unctions. for details of the alternate functions, see chapter 2 pin functions . chapter 4 port functions preliminary user?s manual u19291ej1v0ud 111 table 4-2. port functions (1/2) kc3-l (44-pin) kc3-l (48-pin) kd3-l ke3-l function name i/o function after reset alternate function ? ? p00 ti00 ? ? p01 i/o port 0. i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port to00 p10 ti02/to02 p11 ti03/to03 p12 ti04/to04/ rtcdiv/rtccl p13 ti05/to05 ? ? ? p14 ti06/to06 ? ? ? p15 ti07/to07 ? ? ? p16 ? ? ? ? p17 i/o port 1. i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p20 to p27 i/o port 2. i/o port. input/output can be specified in 1-bit units. digital input port ani0 to ani7 p30 so10/txd1 p31 si10/rxd1/sda10 /intp1 p32 sck10/scl10/ intp2 ? ? ? p33 i/o port 3. i/o port. input of p31 and p32 can be set to ttl buffer. output of p30 to p32 can be set to n-ch open- drain output (v dd tolerance). input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p40 note 2 tool0 p41 tool1 ? ? ? p42 ? ? ? ? p43 i/o port 4. i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? p50 ti06/to06 note 1 p51 ti07/to07 note 1 p52 rtc1hz/slti/ slto ? ? ? p53 i/o port 5. i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ? notes 1. ti06/to06 and ti07/to07 ar e shared only in the 78k0r/kc3-l and 78k0r/kd3-l. the 78k0r/ke3-l does not have a sharing function. 2. if on-chip debugging is enabled by using an option by te, be sure to pull up the p40/tool0 pin externally (see caution in 2.2.5 p40 to p43 (port 4) ). chapter 4 port functions preliminary user?s manual u19291ej1v0ud 112 table 4-2. port functions (2/2) kc3-l (44-pin) kc3-l (48-pin) kd3-l ke3-l function name i/o function after reset alternate function ? p60 scl0 ? p61 i/o port 6. i/o port. output of p60 and p61 is n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. input port sda0 p70 kr0/so01/intp4 p71 kr1/si01/intp5 p72 kr2/sck01/ intp6 p73 kr3/so00/txd0 p74 kr4/si00/rxd0 p75 kr5/sck00 ? ? p76 kr6 ? ? p77 i/o port 7. i/o port. input of p71, p72, p74, and p75 can be set to ttl buffer. output of p70, p72, p73, and p75 can be set to n-ch open-drain output (v dd tolerance). input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port kr7 p80 cmp0p/intp3/ pgai p81 cmp0m p82 cmp1p/intp7 p83 i/o port 8. i/o port. inputs/output can be specified in 1-bit units. inputs of p80 to p83 can be set as comparator inputs or programmable gain amplifier inputs. analog input cmp1m p120 i/o intp0/exlvi p121 x1 p122 x2/exclk p123 xt1 p124 input port 12. i/o port and input port. for only p120, input/output can be specified in 1- bit units. for only p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2 ? p140 outpu t output port pclbuz0 ? ? ? p141 i/o port 14. output port and i/o port. for only p141, input/output can be specified. for only p141, use of an on-chip pull-up resistor can be specified by a software setting. input port pclbuz1 p150 ani8 p151 ani9 ? p152 ani10 ? ? ? p153 i/o port 15. i/o port. input/output can be specified in 1-bit units. digital input port ani11 chapter 4 port functions preliminary user?s manual u19291ej1v0ud 113 4.2 port configuration ports include the following hardware. table 4-4. port configuration item configuration control registers ? 78k0r/kc3-l (44-pin products) port mode registers (pm1 to pm5, pm7, pm8, pm12, pm15) port registers (p1 to p5, p7, p8, p12, p15) pull-up resistor option registers (pu1, pu3 to pu5, pu7, pu12) port input mode registers (pim3, pim7, pim8) port output mode registers (pom3, pom7) a/d port configuration register (adpc) ? 78k0r/kc3-l (48-pin products) port mode registers (pm1 to pm8, pm12, pm15) port registers (p1 to p8, p12, p14, p15) pull-up resistor option registers (pu1, pu3 to pu5, pu7, pu12) port input mode registers (pim3, pim7, pim8) port output mode registers (pom3, pom7) a/d port configuration register (adpc) ? 78k0r/kd3-l port mode registers (pm0 to pm8, pm12, pm15) port registers (p0 to p8, p12, p14, p15) pull-up resistor option registers (pu0, pu1, pu3 to pu5, pu7, pu12) port input mode registers (pim3, pim7, pim8) port output mode registers (pom3, pom7) a/d port configuration register (adpc) ? 78k0r/ke3-l port mode registers (pm0 to pm8, pm12, pm14, pm15) port registers (p0 to p8, p12, p14, p15) pull-up resistor option registers (pu0, pu1, pu3 to pu5, pu7, pu12, pu14) port input mode registers (pim3, pim7, pim8) port output mode registers (pom3, pom7) a/d port configuration register (adpc) port ? 78k0r/kc3-l (44-pin products) total: 37 (cmos i/o: 33, cmos input: 4) ? 78k0r/kc3-l (48-pin products) total: 41 (cmos i/o: 34, cmos input: 4, cmos output: 1, n-ch open drain i/o: 2) ? 78k0r/kd3-l total: 45 (cmos i/o: 38, cmos input: 4, cmos output: 1, n-ch open drain i/o: 2) ? 78k0r/ke3-l total: 55 (cmos i/o: 48, cmos input: 4, cmos output: 1, n-ch open drain i/o: 2) pull-up resistor ? 78k0r/kc3-l (44-pin products) total: 19 ? 78k0r/kc3-l (48-pin products) total: 19 ? 78k0r/kd3-l total: 23 ? 78k0r/ke3-l total: 32 chapter 4 port functions preliminary user?s manual u19291ej1v0ud 114 4.2.1 port 0 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p00/ti00 ? ? p11/to00 ? ? port 0 is an i/o port with an output latch. port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (pm0). when the p00 and p01 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (pu0). this port can also be used for timer i/o. reset signal generation sets port 0 to input mode. figures 4-1 and 4-2 show block diagrams of port 0. caution to use p01/to00 as a general-purpose port, set bi t 0 (to00) of timer output register 0 (to0) and bit 0 (toe00) of timer output enab le register 0 (toe0) to ?0?, which is the same as their default status setting. figure 4-1. block diagram of p00 p00/ti00 wr pu rd pu0 pm0 wr port wr pm pu00 output latch (p00) pm00 ev dd p-ch p0 selector internal bus alternate function p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wrxx: write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . chapter 4 port functions preliminary user?s manual u19291ej1v0ud 115 figure 4-2. block diagram of p01 p01/to00 wr pu rd wr port wr pm pu01 output latch (p01) pm01 ev dd p-ch pu0 pm0 p0 selector internal bus alternate function p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wrxx: write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . chapter 4 port functions preliminary user?s manual u19291ej1v0ud 116 4.2.2 port 1 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p10/ti02/to02 p11/ti03/to03 p12/ti04/to04/ rtcdiv/rtccl p13/ti05/to05 p14/ti06/to06 ? note ? note ? note p15/ti07/to07 ? note ? note ? note p16 ? ? ? p17 ? ? ? note ti06/to06 and ti07/to07 are shared with p50 and p51, respectively, in products other than the 78k0r/ke3-l. remark : mounted port 1 is an i/o port with an output latch. port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (pm1). when the p10 to p17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (pu1). this port can also be used for timer i/o and real-time counter clock output. reset signal generation sets port 1 to input mode. figures 4-3 and 4-4 show block diagrams of port 1. caution to use p10/ti02/to02, p11/ ti03/to03, p12/ti04/to04/ rtcdiv/rtccl, p 13/ti05/to05, p14/ti06/to06, or p15/ti07/to07 as a general-purpose port, set bi ts 2 to 7 (to02 to to07) of timer output register 0 (to0) and bits 2 to 7 (toe02 to toe07) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting. chapter 4 port functions preliminary user?s manual u19291ej1v0ud 117 figure 4-3. block diagram of p10 to p15 p10/ti02/to02, p11/ti03/to03, p12/ti04/to04/rtcdiv/rtccl, p13/ti05/to05, p14/ti06/to06, p15/ti07/to07 wr pu rd wr port wr pm pu10 to pu15 pm10 to pm15 ev dd p-ch pm1 pu1 p1 output latch (p10 to p15) selector internal bus alternate function alternate function p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . chapter 4 port functions preliminary user?s manual u19291ej1v0ud 118 figure 4-4. block diagram of p16 and p17 p16, p17 wr pu rd pu1 pm1 wr port wr pm pu16, pu17 output latch (p16, p17) pm16, pm17 ev dd p-ch p1 selector internal bus p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 4 port functions preliminary user?s manual u19291ej1v0ud 119 4.2.3 port 2 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p20/ani0 p21/ani1 p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 remark : mounted port 2 is an i/o port with an output latch. port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (pm2). this port can also be used for a/d converter analog input. to use p20/ani0 to p27/ani7 as di gital input pins, set them in the di gital i/o mode by using the a/d port configuration register (adpc) and in the input mode by using pm2. use t hese pins starting from the lower bit. to use p20/ani0 to p27/ani7 as digi tal output pins, set them in the di gital i/o mode by using adpc and in the output mode by using pm2. to use p20/ani0 to p27/ani7 as analog input pins, se t them in the analog input mode by using the a/d port configuration register (adpc) and in the input mode by using pm2. use t hese pins starting from the upper bit. table 4-5. setting functions of p20/ani0 to p27/ani7 pins adpc pm2 ads p20/ani0 to p27/ani7 pins input mode ? digital input digital i/o selection output mode ? digital output selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited all p20/ani0 to p27/ani7 are set in the digi tal input mode when the reset signal is generated. figure 4-5 shows a block diagram of port 2. caution make the av ref pin the same potential as the v dd pin when port 2 is used as a digital port. chapter 4 port functions preliminary user?s manual u19291ej1v0ud 120 figure 4-5. block diagram of p20 to p27 p20/ani0 to p27/ani7 rd wr port wr pm pm20 to pm27 pm2 p2 output latch (p20 to p27) selector internal bus a/d converter p2: port register 2 pm2: port mode register 2 rd: read signal wr : write signal chapter 4 port functions preliminary user?s manual u19291ej1v0ud 121 4.2.4 port 3 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p30/so10/txd1 p31/si10/rxd1/ sda10/intp1 p32/sck10/ scl10/intp2 p33 ? ? ? remark : mounted port 3 is an i/o port with an output latch. port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (pm3). when the p30 to p33 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (pu3). input to the p31 and p32 pins can be specified through a normal input buffer or a ttl input buffer in 1-bit units using port input mode register 3 (pim3). output from the p30 to p32 pins can be specified as n-ch open-drain output (v dd tolerance) in 1-bit units using port output mode register 3 (pom3). this port can also be used for serial interface dat a i/o, clock i/o, and external interrupt request input. reset signal generation sets port 3 to input mode. figures 4-6 to 4-8 show block diagrams of port 3. caution to use p30/so10/txd1, p 31/si10/rxd1/sda10/intp1, p32/sck10/scl10/intp2 as a general- purpose port, note the serial array unit setting. for details, refer to table 12-7 relationship between register settings and pi ns (channel 2: csi10, uart1 tr ansmission, iic10) and table 12-8 relationship between register settings and pins (channel 3: uart1 reception). chapter 4 port functions preliminary user?s manual u19291ej1v0ud 122 figure 4-6. block diagram of p30 p30/so10/txd1 wr pu rd wr port wr pm pu30 pm30 ev dd p-ch pu3 pm3 p3 pom30 pom3 wr pom output latch (p30) selector internal bus alternate function p3: port register 3 pu3: pull-up resistor option register 3 pom3: port output mode register 3 pm3: port mode register 3 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . chapter 4 port functions preliminary user?s manual u19291ej1v0ud 123 figure 4-7. block diagram of p31 and p32 p31/si10/rxd1/sda10/intp1, p32/sck10/scl10/intp2 wr pu rd wr port pu31, pu32 ev dd p-ch pu3 p3 wr pm pm3 pom31, pom32 pom3 wr pom pm31, pm32 cmos ttl pim3 pim31, pim32 wr pim selector internal bus alternate function output latch (p31, p32) alternate function p3: port register 3 pu3: pull-up resistor option register 3 pim3: port input mode register 3 pom3: port output mode register 3 pm3: port mode register 3 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . chapter 4 port functions preliminary user?s manual u19291ej1v0ud 124 figure 4-8. block diagram of p33 p33 wr pu pu3 pm3 wr port wr pm pu33 output latch (p33) pm33 ev dd p-ch p3 rd selector internal bus p3: port register 3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal chapter 4 port functions preliminary user?s manual u19291ej1v0ud 125 4.2.5 port 4 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p40/tool0 p41/ tool1 p42 ? ? ? p43 ? ? ? remark : mounted port 4 is an i/o port with an output latch. port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (pm4). when the p40 to p43 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (pu4) note . this port can also be used for flash memory programmer/debugger data i/o and clock output. reset signal generation sets port 4 to input mode. figures 4-9 and 4-10 show block diagrams of port 4. note when a tool is connected, the p40 and p41 pi ns cannot be connected to a pull-up resistor. caution when a tool is connected, th e p40 pin cannot be used as a port pin. when the on-chip debug function is used, p41 pin can be used as follows by the mode setting on the debugger. 1-line mode: can be used as a port (p41). 2-line mode: used as a tool1 pin a nd cannot be used as a port (p41). chapter 4 port functions preliminary user?s manual u19291ej1v0ud 126 figure 4-9. block diagram of p40 and p41 p40/tool0, p41/tool1 rd wr port wr pm pm4 p4 wr pu ev dd p-ch pu4 pm40, pm41 pu40, pu41 selector internal bus alternate function output latch (p40, p41) alternate function selector p4: port register 4 pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . chapter 4 port functions preliminary user?s manual u19291ej1v0ud 127 figure 4-10. block diagram of p42 and p43 p42, p43 wr pu pu4 pm4 wr port wr pm pu42, pu43 output latch (p42, p43) pm42, pm43 ev dd p-ch p4 rd selector internal bus p4: port register 4 pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal chapter 4 port functions preliminary user?s manual u19291ej1v0ud 128 4.2.6 port 5 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p50/ti06/to06 p50 note p51/ti07/to07 p51 note p52/rtc1hz/ slti/slto p53 ? ? ? note ti06/to06 and ti07/to07 are shared only in the 78k0r/kc3-l and 78k0r/kd3-l. the 78k0r/ke3-l does not have a sharing function. remark : mounted port 5 is an i/o port with an output latch. port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (pm5). when the p50 to p53 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (pu5). this port can also be used for real-time co unter correction clock output and timer i/o. reset signal generation sets port 5 to input mode. figures 4-11 to 4-13 show block diagrams of port 5. caution 1. to use p50/ti06/to06 an d p51/ti07/to07 as a general-purpose port, set bits 6 and 7 (to06 and to07) of timer output register 0 (to0) and bi ts 6 and 7 (toe06 and toe07) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting. 2. to use p52/rtc1hz/slti/slto as a general-pur pose port, check which timer i/o pin of which channel n is selected in the input switching c ontrol register (isc) setting. also, set bit n (to0n) of timer output register 0 (to0) and bi t n (toe0n) of timer output enable register 0 (toe0) to ?0?, which is the same se tting as in the initial state of each. remark n = 0, 1 chapter 4 port functions preliminary user?s manual u19291ej1v0ud 129 figure 4-11. block diagram of p50 and p51 (1) 78k0r/ke3-l p50, p51 wr pu rd wr port wr pm pu50, pu51 pm50, pm51 ev dd p-ch pu5 pm5 p5 selector internal bus output latch (p50, p51) (2) products other than the 78k0r/ke3-l p50/ti06/to06, p51/ti07/to07 wr pu rd wr port wr pm pu50 and pu51 pm50 and pm51 v dd p-ch pm5 pu5 p5 output latch (p50 and p51) selector internal bus alternate function alternate function p5: port register 5 pu5: pull-up resistor option register 5 pm5: port mode register 5 rd: read signal wr : write signal chapter 4 port functions preliminary user?s manual u19291ej1v0ud 130 figure 4-12. blo ck diagram of p52 p52/rtc1hz/slti/slto rd wr port wr pm output latch (p52) pm5 p5 wr pu ev dd p-ch pu5 pm52 pu52 channel 0 of taus channel 1 of taus isc2 isc2 isc selector internal bus alternate function selector selector channel 0 of taus channel 1 of taus p5: port register 5 pu5: pull-up resistor option register 5 pm5: port mode register 5 rd: read signal wr : write signal isc: input switch control register remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . chapter 4 port functions preliminary user?s manual u19291ej1v0ud 131 figure 4-13. blo ck diagram of p53 p53 wr pu pu5 pm5 wr port wr pm pu53 output latch (p53) pm53 ev dd p-ch p5 rd selector internal bus p5: port register 5 pu5: pull-up resistor option register 5 pm5: port mode register 5 rd: read signal wr : write signal chapter 4 port functions preliminary user?s manual u19291ej1v0ud 132 4.2.7 port 6 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p60/scl0 ? p61/sda0 ? remark : mounted port 6 is an i/o port with an output latch. port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (pm6). the output of the p60 and p61 pins is n-ch open-drain output (6 v tolerance). this port can also be used for serial interface data i/o and clock i/o. reset signal generation sets port 6 to input mode. figure 4-14 shows block diagram of port 6. caution when using p60/scl0 or p61/sda0 as a general-purpose port, st op the operation of serial interface iica. figure 4-14. block diagram of p60 and p61 p60/scl0, p61/sda0 rd wr port wr pm pm60, pm61 pm6 p6 output latch (p60, p61) selector internal bus alternate function alternate function p6: port register 6 pm6: port mode register 6 rd: read signal wr : write signal chapter 4 port functions preliminary user?s manual u19291ej1v0ud 133 4.2.8 port 7 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p70/kr0/so01/ intp4 p71/kr1/si01/ intp5 p72/kr2/ sck01/intp6 p73/kr3/so00/ txd0 p74/kr4/si00/ rxd0 p75/kr5/sck00 p76/kr6 ? ? p77/kr7 ? ? remark : mounted port 7 is an i/o port with an output latch. port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (pm7). when the p70 to p77 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (pu7). input to the p71, p72, p74, and p75 pins can be specified through a normal input buffer or a ttl input buffer in 1- bit units using port input mode register 7 (pim7). output from the p70, p72, p 73, and p75 pins can be specifi ed as n-ch open-drain output (v dd tolerance) in 1-bit units using port output mode register 7 (pom7). this port can also be used for key return input, serial interface data i/o, clock i/o, and external interrupt request input. reset signal generation sets port 7 to input mode. figures 4-15 to 4-18 show block diagrams of port 7. caution to use p70/kr0/so01/intp4, p71/kr1/si01/intp5, p72/kr2/sck0 1/intp6, p73/kr3/so00/txd0, p74/kr4/si00/rxd0, p75/kr5/sck00 as a general-purpo se port, note the serial array unit setting. for details, refer to table 12-5 relationship be tween register settings and pins (channel 0: csi00, uart0 transmission) and table 12-6 relationship between register settings and pins (channel 1: csi01, uart0 reception). chapter 4 port functions preliminary user?s manual u19291ej1v0ud 134 figure 4-15. block diagram of p70 and p73 p70/kr0/so01/intp4, p73/kr3/so00/txd0 wr pu rd wr port wr pm pu70, pu73 pm70, pm73 ev dd p-ch pu7 pm7 p7 pom70, pom73 pom7 wr pom selector internal bus output latch (p70, p73) alternate function alternate function p7: port register 7 pu7: pull-up resistor option register 7 pom7: port output mode register 7 pm7: port mode register 7 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . chapter 4 port functions preliminary user?s manual u19291ej1v0ud 135 figure 4-16. block diagram of p71 and p74 p71/kr1/si01/intp5, p74/kr4/si00/rxd0 wr pu rd wr port pu71, pu74 ev dd p-ch pu7 p7 cmos ttl pim7 pim71, pim74 wr pim wr pm pm7 pm71, pm74 selector internal bus output latch (p71, p74) alternate function p7: port register 7 pu7: pull-up resistor option register 7 pm7: port mode register 7 pim7: port input mode register 7 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . chapter 4 port functions preliminary user?s manual u19291ej1v0ud 136 figure 4-17. block diagram of p72 and p75 p72/kr2/sck01/intp6, p75/kr5/sck00 wr pu rd wr port pu72, pu75 ev dd p-ch pu7 p7 cmos ttl pim7 pim72, pim75 wr pim wr pm pm7 pom72, pom75 pom7 wr pom pm72, pm75 selector internal bus output latch (p72, p75) alternate function alternate function p7: port register 7 pu7: pull-up resistor option register 7 pm7: port mode register 7 pim7: port input mode register 7 pom7: port output mode register 7 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . chapter 4 port functions preliminary user?s manual u19291ej1v0ud 137 figure 4-18. block diagram of p76 and p77 p76/kr6, p77/kr7 wr pu rd pu7 pm7 wr port wr pm pu76, pu77 output latch (p76, p77) pm76, pm77 ev dd p-ch p7 selector internal bus alternate function p7: port register 7 pu7: pull-up resistor option register 7 pm7: port mode register 7 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . chapter 4 port functions preliminary user?s manual u19291ej1v0ud 138 4.2.9 port 8 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p80/cmp0p/ intp3/pgai p81/cmp0m p82/cmp1p/ intp7 p83/cmp1m remark : mounted port 8 is an i/o port with an output latch. port 8 can be set to the input mode or output mode in 1-bit units using port mode register 8 (pm8). inputs to the p80 to p83 pins must be enabled or disabled in 1-bit units using port input mode register 8 (pim8). this port can also be used for an input voltage on the (+) sides of comparators 0 and 1, an input voltage on the ( ? ) sides of comparators 0 and 1, an external interrupt request input, and a programmable gain amplifier input. reset signal generation sets port 8 to input mode. figures 4-19 to 4-21 show block diagrams of port 8. figure 4-19. block diagram of p80 rd wr port wr pm pm80 pm8 p8 p80/cmp0p/intp3/pgai selector internal bus alternate function output latch (p80) comparator, programmable gain amplifier p8: port register 8 pm8: port mode register 8 rd: read signal wr : write signal chapter 4 port functions preliminary user?s manual u19291ej1v0ud 139 figure 4-20. block diagram of p81 and p83 p81/cmp0m, p83/cmp1m rd wr port wr pm pm81, pm83 pm8 p8 selector internal bus output latch (p81, p83) comparator p8: port register 8 pm8: port mode register 8 rd: read signal wr : write signal chapter 4 port functions preliminary user?s manual u19291ej1v0ud 140 figure 4-21. block diagram of p82 rd wr port wr pm pm82 pm8 p8 p82/cmp1p/intp7 selector internal bus output latch (p82) comparator alternate function p8: port register 8 pm8: port mode register 8 rd: read signal wr : write signal chapter 4 port functions preliminary user?s manual u19291ej1v0ud 141 4.2.10 port 12 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p120/intp0/ exlvi p121/x1 p122/x2/ exclk p123/xt1 p124/xt2 remark : mounted p120 is an i/o port with an output latch. port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (pm12). when used as an input port, us e of an on-chip pull-up resistor can be specified by pull- up resistor option register 12 (pu12). p121 to p124 are input ports. this port can also be used for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting res onator for subsystem clock, and external clock input for main system clock. reset signal generation sets port 12 to input mode. figures 4-22 to 4-24 show block diagrams of port 12. caution the function setting on p1 21 to p124 is available only once after the reset release. the port once set for connection to an oscillato r cannot be used as an input port unless the reset is performed. chapter 4 port functions preliminary user?s manual u19291ej1v0ud 142 figure 4-22. blo ck diagram of p120 p120/intp0/exlvi wr pu rd wr port wr pm pu120 pm120 ev dd p-ch pu12 pm12 p12 selector internal bus output latch (p120) alternate function p12: port register 12 pu12: pull-up resistor option register 12 pm12: port mode register 12 rd: read signal wr : write signal remark with products not provided with an ev dd or ev ss pin, replace ev dd with v dd , or replace ev ss with v ss . chapter 4 port functions preliminary user?s manual u19291ej1v0ud 143 figure 4-23. block di agram of p121 and p122 p122/x2/exclk rd exclk, oscsel cmc oscsel cmc clock generator p121/x1 rd internal bus cmc: clock operation m ode control register rd: read signal chapter 4 port functions preliminary user?s manual u19291ej1v0ud 144 figure 4-24. block di agram of p123 and p124 p124/xt2 rd oscsels cmc oscsels cmc p123/xt1 rd internal bus clock generator cmc: clock operation m ode control register rd: read signal chapter 4 port functions preliminary user?s manual u19291ej1v0ud 145 4.2.11 port 14 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p140/pclbuz0 ? p141/ pclbuz1 ? ? ? remark : mounted p140 is a port dedicated to output and is provided with an output latch. p141 is an i/o port with an output latch. p141 can be set to the input m ode or output mode in 1-bit units using port mode register 14 (pm14). when the p141 pin is used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (pu14). this port can also be used for clock/buzzer output. reset signal generation sets p141 to input mode. figures 4-25 and 4-26 show block diagrams of port 14. caution to use p140/pclbuz0 and p141/pclbuz1 as ge neral-purpose ports, set bit 7 of clock output select registers 0 and 1 (cks0, cks1) to ?0?, wh ich is the same as their default status setting. figure 4-25. blo ck diagram of p140 rd wr port p140/pclbuz0 p140 internal bus output latch (p140) alternate function p14: port register 14 rd: read signal wr : write signal remark the p140 pin outputs a low level when it is used as a po rt function pin and a reset is effected. if p140 is set to output a high level, the output signal of p140 can be dummy-output as the cpu reset signal. p140 set by software reset signal chapter 4 port functions preliminary user?s manual u19291ej1v0ud 146 figure 4-26. blo ck diagram of p141 rd p141/pclbuz1 p-ch wr pu wr port wr pm pu141 output latch (p141) pm141 ev dd pu14 pm14 p14 selector internal bus alternate function p14: port register 14 pu14: pull-up resistor option register 14 pm14: port mode register 14 rd: read signal wr : write signal chapter 4 port functions preliminary user?s manual u19291ej1v0ud 147 4.2.12 port 15 78k0r/kc3-l (44-pin) ( pd78f100y: y = 0 to 3) 78k0r/kc3-l (48-pin) ( pd78f100y: y = 1 to 3) 78k0r/kd3-l ( pd78f100y: y = 4 to 6) 78k0r/ke3-l ( pd78f100y: y = 7 to 9) p150/ani8 p151/ani9 p152/ani10 ? p153/ani11 ? ? ? remark : mounted port 15 is an i/o port with an output latch. port 15 can be set to the input mode or output mode in 1-bit units using port mode register 15 (pm15). this port can also be used for a/d converter analog input. to use p150/ani8 to p153/ani11 as digital input pins, set them in the digital i/o mode by using the a/d port configuration register (adpc) and in the input mode by using pm15. use t hese pins starting from the lower bit. to use p150/ani8 to p153/ani11 as digital output pins, se t them in the digital i/o mode by using adpc and in the output mode by using pm15. table 4-6. setting functions of p150/ani8 to p153/ani11 pins adpc pm15 ads p150/ani8 to p153/ani11 pins input mode ? digital input digital i/o selection output mode ? digital output selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited all p150/ani8 to p153/ani11 are set in the digita l input mode when the reset signal is generated. figure 4-27 shows block diagram of port 15. caution make the av ref pin the same potential as the v dd pin when port 15 is used as a digital port. chapter 4 port functions preliminary user?s manual u19291ej1v0ud 148 figure 4-27. block di agram of p150 to p153 p150/ani8 to p153/ani11 rd wr port wr pm pm150 to pm153 pm15 p15 selector internal bus output latch (p150 to p153) a/d converter p15: port register 15 pm15: port mode register 15 rd: read signal wr : write signal chapter 4 port functions preliminary user?s manual u19291ej1v0ud 149 4.3 registers controlling port function port functions are controlled by t he following six types of registers. ? port mode registers (pmxx) ? port registers (pxx) ? pull-up resistor option registers (puxx) ? port input mode registers (pim3, pim7, pim8) ? port output mode registers (pom3, pom7) ? a/d port configuration register (adpc) (1) port mode registers (pmxx) these registers specify input or output mode for the port in 1-bit units. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these regi sters to ffh (pm13 is set to feh). when port pins are used as alternate-function pi ns, set the port mode register by referencing 4.5 settings of port mode register and output latch when using alternate function . chapter 4 port functions preliminary user?s manual u19291ej1v0ud 150 figure 4-28. format of port mode register (78k0r/kc3-l) symbol 7 6 5 4 3 2 1 0 address after reset r/w pm1 1 1 1 1 pm13 pm12 pm11 pm10 fff21h ffh r/w pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 fff22h ffh r/w pm3 1 1 1 1 1 pm32 pm31 pm30 fff23h ffh r/w pm4 1 1 1 1 1 1 pm41 pm40 fff24h ffh r/w pm5 1 1 1 1 1 pm52 pm51 pm50 fff25h ffh r/w pm6 note 1 1 1 1 1 1 pm61 note pm60 note fff26h ffh r/w pm7 1 1 pm75 pm74 pm73 pm72 pm71 pm70 fff27h ffh r/w pm8 1 1 1 1 pm83 pm82 pm81 pm80 fff28h ffh r/w pm12 1 1 1 1 1 1 1 pm120 fff2ch ffh r/w pm15 1 1 1 1 1 pm152 note pm151 pm150 fff2fh ffh r/w pmmn pmn pin i/o mode selection (m = 1 to 8, 12, 15; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) note 48-pin products only. caution be sure to set bits 4 to 7 of pm1, bits 3 to 7 of pm3, bits 2 to 7 of pm4, bits 3 to 7 of pm5, bits 2 to 7 of pm6, bits 6 and 7 of pm7, bits 4 to 7 of pm8, bits 1 to 7 of pm12, and bits 1 to 7 of pm15 to 1. chapter 4 port functions preliminary user?s manual u19291ej1v0ud 151 figure 4-29. format of port mode register (78k0r/kd3-l) symbol 7 6 5 4 3 2 1 0 address after reset r/w pm0 1 1 1 1 1 1 pm01 pm00 fff20h ffh r/w pm1 1 1 1 1 pm13 pm12 pm11 pm10 fff21h ffh r/w pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 fff22h ffh r/w pm3 1 1 1 1 1 pm32 pm31 pm30 fff23h ffh r/w pm4 1 1 1 1 1 1 pm41 pm40 fff24h ffh r/w pm5 1 1 1 1 1 pm52 pm51 pm50 fff25h ffh r/w pm6 1 1 1 1 1 1 pm61 pm60 fff26h ffh r/w pm7 pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 fff27h ffh r/w pm8 1 1 1 1 pm83 pm82 pm81 pm80 fff28h ffh r/w pm12 1 1 1 1 1 1 1 pm120 fff2ch ffh r/w pm15 1 1 1 1 1 pm152 pm151 pm150 fff2fh ffh r/w pmmn pmn pin i/o mode selection (m = 0 to 8, 12, 15; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) caution be sure to set bits 2 to 7 of pm0, bits 4 to 7 of pm1, bits 3 to 7 of pm3, bits 2 to 7 of pm4, bits 3 to 7 of pm5, bits 2 to 7 of pm6, bits 4 to 7 of pm8, bits 1 to 7 of pm12, and bits 3 to 7 of pm15 to 1. chapter 4 port functions preliminary user?s manual u19291ej1v0ud 152 figure 4-30. format of port mode register (78k0r/ke3-l) symbol 7 6 5 4 3 2 1 0 address after reset r/w pm0 1 1 1 1 1 1 pm01 pm00 fff20h ffh r/w pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 fff21h ffh r/w pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 fff22h ffh r/w pm3 1 1 1 1 pm33 pm32 pm31 pm30 fff23h ffh r/w pm4 1 1 1 1 pm43 pm42 pm41 pm40 fff24h ffh r/w pm5 1 1 1 1 pm53 pm52 pm51 pm50 fff25h ffh r/w pm6 1 1 1 1 1 1 pm61 pm60 fff26h ffh r/w pm7 pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 fff27h ffh r/w pm8 1 1 1 1 pm83 pm82 pm81 pm80 fff28h ffh r/w pm12 1 1 1 1 1 1 1 pm120 fff2ch ffh r/w pm14 1 1 1 1 1 1 pm141 0 fff2eh feh r/w pm15 1 1 1 1 pm153 pm152 pm151 pm150 fff2fh ffh r/w pmmn pmn pin i/o mode selection (m = 0 to 8, 12, 14, 15; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) caution be sure to set bits 2 to 7 of pm0, bits 4 to 7 of pm3, bits 4 to 7 of pm4, bits 4 to 7 of pm5, bits 2 to 7 of pm6, bits 4 to 7 of pm8, bits 1 to 7 of pm12, bits 2 to 7 of pm14, and bits 4 to 7 of pm15 to 1. also, be sure to set bit 0 of pm14 to 0. chapter 4 port functions preliminary user?s manual u19291ej1v0ud 153 (2) port registers (pxx) these registers set the output latch value of a port. if the data is read in the input mode, the pin level is read. if it is read in the output mode, the output latch value is read note . these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. note it is always 0 and never a pin level that is read out if a port is read during the input mode when p2 and p15 are set to function as an analog input for a a/d converter. figure 4-31. format of port register (78k0r/kc3-l) symbol 7 6 5 4 3 2 1 0 address after reset r/w p1 0 0 0 0 p13 p12 p11 p10 fff01h 00h (output latch) r/w p2 p27 p26 p25 p24 p23 p22 p21 p20 fff02h 00h (output latch) r/w p3 0 0 0 0 0 p32 p31 p30 fff03h 00h (output latch) r/w p4 0 0 0 0 0 0 p41 p40 fff04h 00h (output latch) r/w p5 0 0 0 0 0 p52 p51 p50 fff05h 00h (output latch) r/w p6 note1 0 0 0 0 0 0 p61 note1 p60 note1 fff06h 00h (output latch) r/w p7 0 0 p75 p74 p73 p72 p71 p70 fff07h 00h (output latch) r/w p8 0 0 0 0 p83 p82 p81 p80 fff08h 00h (output latch) r/w p12 0 0 0 p124 p123 p122 p121 p120 fff0ch undefined r/w note2 p14 note1 0 0 0 0 0 0 0 p140 note1 fff0eh 00h (output latch) r/w p15 0 0 0 0 0 p152 note1 p151 p150 fff0fh 00h (output latch) r/w m = 1 to 8, 12, 14, 15 ; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level notes 1. p121 to p124 are read-only. 2. 48-pin products only. chapter 4 port functions preliminary user?s manual u19291ej1v0ud 154 figure 4-32. format of port register (78k0r/kd3-l) symbol 7 6 5 4 3 2 1 0 address after reset r/w p0 0 0 0 0 0 0 p01 p00 fff00h 00h (output latch) r/w p1 0 0 0 0 p13 p12 p11 p10 fff01h 00h (output latch) r/w p2 p27 p26 p25 p24 p23 p22 p21 p20 fff02h 00h (output latch) r/w p3 0 0 0 0 0 p32 p31 p30 fff03h 00h (output latch) r/w p4 0 0 0 0 0 0 p41 p40 fff04h 00h (output latch) r/w p5 0 0 0 0 0 p52 p51 p50 fff05h 00h (output latch) r/w p6 0 0 0 0 0 0 p61 p60 fff06h 00h (output latch) r/w p7 p77 p76 p75 p74 p73 p72 p71 p70 fff07h 00h (output latch) r/w p8 0 0 0 0 p83 p82 p81 p80 fff08h 00h (output latch) r/w p12 0 0 0 p124 p123 p122 p121 p120 fff0ch undefined r/w note p14 0 0 0 0 0 0 0 p140 fff0eh 00h (output latch) r/w p15 0 0 0 0 0 p152 p151 p150 fff0fh 00h (output latch) r/w m = 0 to 8, 12, 14, 15 ; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level note p121 to p124 are read-only. chapter 4 port functions preliminary user?s manual u19291ej1v0ud 155 figure 4-33. format of port register (78k0r/ke3-l) symbol 7 6 5 4 3 2 1 0 address after reset r/w p0 0 0 0 0 0 0 p01 p00 fff00h 00h (output latch) r/w p1 p17 p16 p15 p14 p13 p12 p11 p10 fff01h 00h (output latch) r/w p2 p27 p26 p25 p24 p23 p22 p21 p20 fff02h 00h (output latch) r/w p3 0 0 0 0 p33 p32 p31 p30 fff03h 00h (output latch) r/w p4 0 0 0 0 p43 p42 p41 p40 fff04h 00h (output latch) r/w p5 0 0 0 0 p53 p52 p51 p50 fff05h 00h (output latch) r/w p6 0 0 0 0 0 0 p61 p60 fff06h 00h (output latch) r/w p7 p77 p76 p75 p74 p73 p72 p71 p70 fff07h 00h (output latch) r/w p8 0 0 0 0 p83 p82 p81 p80 fff08h 00h (output latch) r/w p12 0 0 0 p124 p123 p122 p121 p120 fff0ch undefined r/w note p14 0 0 0 0 0 0 p141 p140 fff0eh 00h (output latch) r/w p15 0 0 0 0 p153 p152 p151 p150 fff0fh 00h (output latch) r/w m = 0 to 8, 12, 14, 15 ; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level note p121 to p124 are read-only. chapter 4 port functions preliminary user?s manual u19291ej1v0ud 156 (3) pull-up resistor option registers (puxx) these registers specify whet her the on-chip pull-up resistors are to be used or not. on-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in these registers. on-chip pull-up resistors cannot be connected to bits set to output mode and bits used as alternate-function output pins, regar dless of the settings of these registers. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 4-34. format of pull-up resistor option register (78k0r/kc3-l) symbol 7 6 5 4 3 2 1 0 address after reset r/w pu1 0 0 0 0 pu13 pu12 pu11 pu10 f0031h 00h r/w pu3 0 0 0 0 0 pu32 pu31 pu30 f0033h 00h r/w pu4 0 0 0 0 0 0 pu41 pu40 f0034h 00h r/w pu5 0 0 0 0 0 pu52 pu51 pu50 f0035h 00h r/w pu7 0 0 pu75 pu74 pu73 pu72 pu71 pu70 f0037h 00h r/w pu12 0 0 0 0 0 0 0 pu120 f003ch 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 1, 3 to 5, 7, 12 ; n = 0 to 5) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected chapter 4 port functions preliminary user?s manual u19291ej1v0ud 157 figure 4-35. format of pull-up resistor option register (78k0r/kd3-l) symbol 7 6 5 4 3 2 1 0 address after reset r/w pu0 0 0 0 0 0 0 pu01 pu00 f0030h 00h r/w pu1 0 0 0 0 pu13 pu12 pu11 pu10 f0031h 00h r/w pu3 0 0 0 0 0 pu32 pu31 pu30 f0033h 00h r/w pu4 0 0 0 0 0 0 pu41 pu40 f0034h 00h r/w pu5 0 0 0 0 0 pu52 pu51 pu50 f0035h 00h r/w pu7 pu77 pu76 pu75 pu74 pu73 pu72 pu71 pu70 f0037h 00h r/w pu12 0 0 0 0 0 0 0 pu120 f003ch 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 5, 7, 12 ; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected chapter 4 port functions preliminary user?s manual u19291ej1v0ud 158 figure 4-36. format of pull-up resistor option register (78k0r/ke3-l) symbol 7 6 5 4 3 2 1 0 address after reset r/w pu0 0 0 0 0 0 0 pu01 pu00 f0030h 00h r/w pu1 pu17 pu16 pu15 pu14 pu13 pu12 pu11 pu10 f0031h 00h r/w pu3 0 0 0 0 pu33 pu32 pu31 pu30 f0033h 00h r/w pu4 0 0 0 0 pu43 pu42 pu41 pu40 f0034h 00h r/w pu5 0 0 0 0 pu53 pu52 pu51 pu50 f0035h 00h r/w pu7 pu77 pu76 pu75 pu74 pu73 pu72 pu71 pu70 f0037h 00h r/w pu12 0 0 0 0 0 0 0 pu120 f003ch 00h r/w pu14 0 0 0 0 0 0 p141 0 f003eh 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 5, 7, 12, 14 ; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected chapter 4 port functions preliminary user?s manual u19291ej1v0ud 159 (4) port input mode regi sters (pim3, pim7, pim8) pim3 and pim7 registers set the input buffer of p31, p32, p71, p72, p74, or p75 in 1-bit units. ttl input buffer can be selected during serial communication with an external device of the different potential. pim8 is used to enable or disable the digital inputs to p 80 to p83 in 1-bit units. when using a comparator or a programmable gain amplifier, the digita l inputs are disabled (used as analog input) by software processing. to use port functions and alternative functions, the digita l inputs must be enabled, because they are disabled (used as analog input) by default. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 4-37. format of port input mode register symbol 7 6 5 4 3 2 1 0 address after reset r/w pim3 0 0 0 0 0 pim32 pim31 0 f0043h 00h r/w pim7 0 0 pim75 pim74 0 pim72 pim71 0 f0047h 00h r/w pim8 0 0 0 0 pim83 pim82 pim81 pim80 f0048h 00h r/w pimmn pmn pin input buffer selection (m = 3 and 7; n = 1, 2, 4, 5) 0 normal input buffer 1 ttl input buffer pim8n p8n pin digital input buffer selection (n = 0 to 3) 0 disables digital input (used as analog input) 1 enables digital input chapter 4 port functions preliminary user?s manual u19291ej1v0ud 160 (5) port output mode registers (pom3, pom7) these registers set the output mode of p30 to p32, p70, p72, p73, or p75 in 1-bit units. n-ch open drain output (v dd tolerance) mode can be selected during serial communication with an external device of the different potential, and for the sda10 pin during simplified i 2 c communication with an external device of the same potential. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 4-38. format of port output mode register symbol 7 6 5 4 3 2 1 0 address after reset r/w pom3 0 0 0 0 0 pom32 pom31 pom30 f0053h 00h r/w pom7 0 0 pom75 0 pom73 po m72 0 pom70 f0057h 00h r/w pommn pmn pin output mode selection (m = 3 and 7; n = 0 to 3 and 5) 0 normal output mode 1 n-ch open-drain output (v dd tolerance) mode chapter 4 port functions preliminary user?s manual u19291ej1v0ud 161 (6) a/d port configuration register (adpc) this register switches the ani0/p20 to ani7/p27 and ani8 /p150 to ani11/p153 pins to digital i/o of port or analog input of a/d converter. adpc can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 10h. figure 4-39. format of a/d port configuration register (adpc) address: f0017h after reset: 10h r/w symbol 7 6 5 4 3 2 1 0 adpc 0 0 0 adpc4 adpc3 adpc2 adpc1 adpc0 analog input (a)/digita l i/o (d) switching port 15 port 2 adpc4 adpc3 adpc2 adpc1 adpc0 ani11 /p153 ani10 /p152 ani9 /p151 ani8 /p150 ani7 /p27 ani6 /p26 ani5 /p25 ani4 /p24 ani3 /p23 ani2 /p22 ani1 /p21 ani0 /p20 0 0 0 0 0 a a a a a a a a a a a a 0 0 0 0 1 a a a a a a a a a a a d 0 0 0 1 0 a a a a a a a a a a d d 0 0 0 1 1 a a a a a a a a a d d d 0 0 1 0 0 a a a a a a a a d d d d 0 0 1 0 1 a a a a a a a d d d d d 0 0 1 1 0 a a a a a a d d d d d d 0 0 1 1 1 a a a a a d d d d d d d 0 1 0 0 0 a a a a d d d d d d d d 0 1 0 0 1 a a a d d d d d d d d d 0 1 0 1 0 a a d d d d d d d d d d 0 1 0 1 1 a d d d d d d d d d d d 1 0 0 0 0 d d d d d d d d d d d d other than the above setting prohibited cautions 1. set a channel to be used for a/d conversion in the input mode by using port mode register 2 and 15 (pm2, pm15). 2. do not set the pin that is set by adpc as digital i/o by analog input channel specification register (ads). remark p20/ani0-p27/ani7, p150/ani8, and p151/ani9: 78k0r/kc3-l (44-pin) p20/ani0-p27/ani7, p150/ani8 to p152/ ani10: 78k0r/kc3-l (48-pin), 78k0r/kd3-l p20/ani0-p27/ani7, p150/ani8 to p153/ani11: 78k0r/ke3-l chapter 4 port functions preliminary user?s manual u19291ej1v0ud 162 4.4 port function operations port operations differ depending on whether the inpu t or output mode is set, as shown below. 4.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instruct ion, and the output latch content s are output from the pin. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. 4.4.2 reading from i/o port (1) output mode the output latch contents ar e read by a transfer instruction. t he output latch content s do not change. (2) input mode the pin status is read by a transfer instruct ion. the output latch c ontents do not change. 4.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is wr itten to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. (2) input mode the pin level is read and an operation is performed on its cont ents. the result of the op eration is written to the output latch, but since the output buffer is off, the pin status does not change. the data of the output latch is clear ed when a reset signal is generated. chapter 4 port functions preliminary user?s manual u19291ej1v0ud 163 4.4.4 connecting to external device with di fferent power potential (2.5 v, 3 v) when ports 3 and 7 operate with v dd = 4.0 v to 5.5 v, i/o connections wit h an external device that operates on a 2.5v or 3 v power supply voltage are possible. regarding inputs, normal input (cmos)/ttl switching is possi ble on a bit-by-bit basis by port input mode registers 3 and 7 (pim3 and pim7). moreover, regarding outputs, different power potentials can be supported by s witching the output buffer to the n-ch open drain (v dd withstand voltage) by the port output m ode registers 3 and 7 (pom3 and pom7). (1) setting procedure when using i/o pins of uart0, uart1 csi00, csi01, and csi10 functions (a) use as 2.5v or 3 v input port <1> after reset release, the port mode is the input mode (hi-z). <2> if pull-up is needed, externally pull up the pin to be used (on-chip pull-up resistor cannot be used). in case of uart0: p74 in case of uart1: p31 in case of csi00: p74, p75 in case of csi01: p71, p72 in case of csi10: p31, p32 <3> set the corresponding bit of the pim3 and pim7 regist ers to 1 to switch to the ttl input buffer. <4> v ih /v il operates on a 2.5v or 3 v operating voltage. (b) use as 2.5v or 3 v output port <1> after reset release, the port mode changes to the input mode (hi-z). <2> pull up externally the pin to be used ( on-chip pull-up resistor cannot be used). in case of uart0: p73 in case of uart1: p30 in case of csi00: p73, p75 in case of csi01: p70, p72 in case of csi10: p30, p32 <3> set the output latch of the corresponding port to 1. <4> set the corresponding bit of the pom3 and pom7 registers to 1 to set the n-ch open drain output (v dd withstand voltage) mode. <5> set the output mode by manipulat ing the pm3 and pm7 registers. at this time, the output data is high level, so the pin is in the hi-z state. <6> communication is started by setting the serial array unit. chapter 4 port functions preliminary user?s manual u19291ej1v0ud 164 (2) setting procedure when using i/o pins of simplified iic10 functions <1> after reset release, the port mode is the input mode (hi-z). <2> externally pull up the pin to be used (o n-chip pull-up resistor cannot be used). in case of simplified iic10: p31, p32 <3> set the output latch of the corresponding port to 1. <4> set the corresponding bit of the pom3 regist er to 1 to set the n-ch open drain output (v dd withstand voltage) mode. <5> set the corresponding bit of the pm3 register to the output mode (data i/o is possible in the output mode). at this time, the output data is high level, so the pin is in the hi-z state. <6> enable the operation of the serial arra y unit and set the mode to the simplified i 2 c mode. chapter 4 port functions preliminary user?s manual u19291ej1v0ud 165 4.5 settings of port mode register and output latch when using alternate function to use the alternate function of a por t pin, set the port mode register and output latch as shown in table 4-7. table 4-7. settings of port mode register a nd output latch when using alternate function (1/2) alternate function pin name function name i/o pm p p00 ti00 input 1 p01 to00 output 0 0 ti02 input 1 p10 to02 output 0 0 ti03 input 1 p11 to03 output 0 0 ti04 input 1 to04 output 0 0 rtcdiv output 0 0 p12 rtccl output 0 0 ti05 input 1 p13 to05 output 0 0 ti06 note 1 input 1 p14 note 1 to06 note 1 output 0 0 ti07 note 1 input 1 p15 note 1 to07 note 1 output 0 0 p20 to p27 note 2 ani0 to ani7 note 2 input 1 so10 output 0 1 p30 txd1 output 0 1 si10 input 1 rxd1 input 1 sda10 i/o 0 1 p31 intp1 input 1 input 1 sck10 output 0 1 scl10 i/o 0 1 p32 intp2 input 1 p40 tool0 i/o p41 tool1 output ti06 note 1 input 1 p50 note 1 to06 note 1 output 0 0 ti07 note 1 input 1 p51 note 1 to07 note 1 output 0 0 remark : don?t care pm : port mode register p : port output latch ( note is listed on the next page after next.) chapter 4 port functions preliminary user?s manual u19291ej1v0ud 166 table 4-7. settings of port mode register a nd output latch when using alternate function (2/2) alternate function pin name function name i/o pm p rtc1hz output 0 0 slti input 1 p52 slto output 0 0 p60 scl0 i/o 0 0 p61 sda0 i/o 0 0 kr0 input 1 so01 output 0 1 p70 intp4 input 1 kr1 input 1 si01 input 1 p71 intp5 input 1 kr2 input 1 input 1 sck01 output 0 1 p72 intp6 input 1 kr3 input 1 so00 output 0 1 p73 txd0 output 0 1 kr4 input 1 si00 input 1 p74 rxd0 input 1 kr5 input 1 input 1 p75 sck00 output 0 1 p76 kr6 input 1 p77 kr7 input 1 cmp0p input 1 intp3 input 1 p80 note 2 pgai note 2 input 1 p81 cmp0m input 1 cmp1p input 1 p82 intp7 input 1 p83 cmp1m input 1 intp0 input 1 p120 exlvi input 1 p140 pclbuz0 output 0 0 p141 pclbuz1 output 0 0 p150 to p153 note 2 ani8 to ani11 note 2 input 1 remark : don?t care pm : port mode register p : port output latch ( note is listed on the next page.) chapter 4 port functions preliminary user?s manual u19291ej1v0ud 167 notes 1. the ports with which ti06/to06 and ti07/to07 pins are shared differ depending on the product. 78k0r/kc3-l, 78k0r/kd3-l : p50/ti06/to06, p51/ti07/to07 78k0r/ke3-l: p 14/ti06/to06, p15/ti07/to07 2. the function of the ani0/p20 to ani7/p27, ani8 /p150 to ani11/p153, and pgai/p80 pins can be selected by using the a/d port c onfiguration register (adpc), the analog input channel specification register (ads), pm2, pm15, and pm8. table 4-8. setting functions of ani0/p20 to ani7/ p27, ani8/p150 to ani11/ p153, and pgai/p80 pins adpc pm2, pm15, pm8 ads ani0/p20 to ani7/p27, ani8/p150 to ani11/p153, and pgai/p80 pins input mode ? digital input digital i/o selection output mode ? digital output selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited remark p20/ani0-p27/ani7, p150/ani8, and p151/ani9: 78k0r/kc3-l (44-pin) p20/ani0-p27/ani7, p150/ani8 to p152/an i10: 78k0r/kc3-l (48-pin), 78k0r/kd3-l p20/ani0-p27/ani7, p150/ani8 to p153/ani11: 78k0r/ke3-l chapter 4 port functions preliminary user?s manual u19291ej1v0ud 168 4.6 cautions on 1-bit manipulation in struction for port register n (pn) when a 1-bit manipulation instruction is executed on a por t that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. preliminary user?s manual u19291ej1v0ud 169 chapter 5 clock generator 5.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following three kinds of system clo cks and clock oscillators are selectable. (1) main system clock <1> x1 oscillator this circuit oscillates a clock of f x = 2 to 20 mhz by connecting a resonator to x1 and x2. oscillation can be stopped by executing the stop instru ction or setting of mstop (bit 7 of the clock operation status control register (csc)). <2> internal high-speed oscillator note this circuit oscillates clocks of f ih = 1 and 8 mhz (typ.). after a rese t release, the cpu always starts operating with this internal high-speed oscillation cl ock. oscillation can be stopped by executing the stop instruction or setting hiostop (bit 0 of csc). <3> 20 mhz internal high-sp eed oscillation clock oscillator note this circuit oscillates a clock of f ih20 = 20 mhz (typ.). oscillation can be started by setting bit 0 (dscon) of the 20 mhz internal high-speed oscillation control register (dscctl) to 1 with v dd 2.7 v. oscillation can be stopped by setting dscon to 0. note to use the 1, 8, or 20 mhz internal high-speed oscillation clock, use the option byte to set the frequency in advance (for details, see chapter 23 option byte ). also, the internal high- speed oscillator automatically st arts oscillating after reset release. to use the 20 mhz internal high-speed oscillator to operate the microcontroller, oscillation is started by setting bit 0 (dscon) of the 20 mhz internal high-speed oscillati on control register (dscctl) to 1. an external main system clock (f ex = 2 to 20 mhz) can also be supplied from the exclk/x2/p122 pin. an external main system clock input can be disabled by executing the stop instruct ion or setting of mstop. as the main system clock, a high-spee d system clock (x1 clock or external ma in system clock) or internal high- speed oscillation clock can be selected by setting of mcm0 (bit 4 of the syst em clock control register (ckc)). (2) subsystem clock ? xt1 clock oscillator this circuit oscillates a clock of f sub = 32.768 khz by connecting a 32.768 khz resonator to xt1 and xt2. oscillation can be stopped by se tting xtstop (bit 6 of csc). remark f x : x1 clock oscillation frequency f ih : internal high-speed oscillation clock frequency f ih20 : 20 mhz internal high-speed oscillation clock frequency f ex : external main system clock frequency f sub : subsystem clock frequency chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 170 (3) internal low-speed oscillation clo ck (clock dedicated to watchdog timer) ? internal low-speed oscillator this circuit oscillates a clock of f il = 30 khz (typ.). the internal low-speed oscillation clock cannot be used as the cpu clock. the only hardware that operates with the internal low-speed oscillation clock is the watchdog timer. oscillation is stopped when the watchdog timer stops. remarks 1. f il : internal low-speed oscillation clock frequency 2. the watchdog timer stops in the following cases. ? when bit 4 (wdton) of an option byte (000c0h) = 0 ? if the halt or stop instruction is executed when bit 4 (wdton) of an option byte (000c0h) = 1 and bit 0 (wdstbyon) = 0 5.2 configuration of clock generator the clock generator includes the following hardware. table 5-1. configuration of clock generator item configuration control registers clock operation mode control register (cmc) clock operation status control register (csc) oscillation stabilization time counter status register (ostc) oscillation stabilization time select register (osts) system clock control register (ckc) 20 mhz internal high-speed oscilla tion control register (dscctl) peripheral enable registers 0, 1, 2 (per0, per1, per2) operation speed mode control register (osmc) oscillators x1 oscillator xt1 oscillator internal high-speed oscillator internal low-speed oscillator chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 171 figure 5-1. block diag ram of clock generator xt1/p123 xt2//p124 f sub watchdog timer real-time counter, clock output/buzzer output note f clk system clock control register (ckc) css cls x1 oscillation stabilization time counter osts1 osts0 osts2 oscillation stabilization time select register (osts) 3 most 18 most 17 most 15 most 13 most 11 oscillation stabilization time counter status register (ostc) mstop stop mode signal exclk oscsel amph clock operation mode control register (cmc) 4 clock operation status control register (csc) internal bus f mx subsystem clock oscillator f xt high-speed system clock oscillator crystal/ceramic oscillation external input clock x1/p121 x2/exclk /p122 f x f ex mcm0 mcs md iv2 md iv1 md iv0 cpu clock and peripheral hardware clock source selection cpu clock output/ buzzer output note f main /2 5 f main /2 4 f main /2 3 f main /2 2 f main /2 f main 1 most 10 most 9 most 8 sau0 en iica en note adc en rtc en peripheral enable register 0 (per0) timer array unit taus serial array unit a/d converter programmable gain amplifier/comparator real-time counter f sub /2 oacmp en peripheral enable register 1 (per1) tau0 en peripheral enable register 2 (per2) serial interface iica note clock operation status control register (csc) xtstop hiostop clock operation mode control register (cmc) cls f ih20 f ih 20 mhz internal high-speed oscillation control register (dscctl) dscs dscon seldsc amphs1 amphs0 f main internal high-speed oscillator internal high-speed oscillation (1 mhz (typ.)) crystal oscillation option byte (000c1h) frqsel2, frqsel1 f ih1 f ih8 internal high-speed oscillation (8 mhz (typ.)) 20 mhz internal high-speed oscillator internal high-speed oscillation (20 mhz (typ.)) f ih20 main system clock source selector internal low-speed oscillator internal low-speed oscillation (30 khz (typ.)) option byte (000c0h) wdton wdstbyon f il halt/stop mode signal standby controller halt mode stop mode normal operation mode internal bus prescaler selector controller oscsels ( note and remark are listed on the next page.) chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 172 note this is not mounted onto 44-pin products of the 78k0r/kc3-l. remark f x : x1 clock oscillation frequency f ih : internal high-speed oscillation clock frequency f ih20 : 20 mhz internal high-speed oscillation clock frequency f ex : external main system clock frequency f mx : high-speed system clock frequency f main : main system clock frequency f xt : xt1 clock oscillation frequency f sub : subsystem clock frequency f clk : cpu/peripheral hardware clock frequency f il : internal low-speed oscillation clock frequency 5.3 registers controlling clock generator the following eight registers are us ed to control the clock generator. ? clock operation mode control register (cmc) ? clock operation status control register (csc) ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) ? system clock control register (ckc) ? 20 mhz internal high-speed oscillation control register (dscctl) ? peripheral enable registers 0, 1, 2 (per0, per1, per2) ? operation speed mode control register (osmc) (1) clock operation mode control register (cmc) this register is used to set the operation mode of t he x1/p121, x2/exclk/p122, xt 1/p123, and xt2/p124 pins, and to select a gain of the oscillator. cmc can be written only once by an 8-bit memory manipulati on instruction after reset release. this register can be read by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 173 figure 5-2. format of clock operat ion mode control register (cmc) address: fffa0h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 cmc exclk oscsel 0 oscsels 0 amphs1 amphs0 amph exclk oscsel high-speed system clock pin operation mode x1/p121 pin x2/exclk/p122 pin 0 0 input port mode input port 0 1 x1 oscillation mode crystal/ceramic resonator connection 1 0 input port mode input port 1 1 external clock input mode input port external clock input oscsels subsystem clock pin operat ion mode xt1/p123 pin xt2/p124 pin 0 input port mode input port 1 xt1 oscillation mode crystal resonator connection amphs1 amphs0 xt1 oscillator oscillation mode selection 0 0 low power consumption oscillation (default) 0 1 normal oscillation 1 0 1 1 ultra-low power consumption oscillation amph control of high-speed system clock oscillation frequency 0 2 mhz f mx 10 mhz 1 10 mhz < f mx 20 mhz cautions 1. cmc can be written only once after reset release, by an 8-bit memory manipulation instruction. 2. after reset release, set cmc before x1 or xt1 oscilla tion is started as set by the clock operation status control register (csc). 3. be sure to set amph to 1 if the x1 clock oscillation fr equency exceeds 10 mhz. 4. when cmc is used at the default value (00h), be sure to set 00h to this register after reset release in order to preven t malfunctioning duri ng a program loop. 5. the xt1 oscillator is a circuit with low amplification in order to achieve low- power consumption. note the followi ng points when designing the circuit. ? pins and circuit boards include par asitic capacitance. therefore, perform oscillation evaluation using a circuit board to be act ually used and confirm that there are no problems. ? when using the ultra-low power cons umption oscillation (amphs1 = 1) as the mode of the xt1 oscillator, use the recommended resonato rs described in chapter 28 electrical spec ifications (target). ? make the wiring between th e xt1 and xt2 pins and the resonators as short as possible, and minimize the parasiti c capacitance and wiring resistance. note this particularly when the ul tra-low power consumption oscillation (amphs1 = 1) is selected. (cautions and remark are given on the next page.) chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 174 ? configure the circuit of the circuit board, using material with little wiring resistance. ? place a ground pattern that has the same potential as v ss as much as possible near the xt1 oscillator. ? be sure that the sign al lines between the xt 1 and xt2 pins, and the resonators do not cross with the other si gnal lines. do not route the wiring near a signal line through which a high fluctuating current flows. ? the impedance between the xt1 and xt 2 pins may drop and oscillation may be disturbed due to moisture absorp tion of the circuit board in a high- humidity environment or dew condensati on on the board. when using the circuit board in such an environment, take measu res to damp-proof the circuit board, such as by coating. ? when coating the circui t board, use material that does not cause capacitance or leakage between th e xt1 and xt2 pins. remark f mx : high-speed system clock frequency (2) clock operation status control register (csc) this register is used to control the op erations of the high-speed system clock, internal high-speed oscillation clock, and subsystem clock (except the 20 mhz internal high-speed oscillation clock and internal low-speed oscillation clock). csc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to c0h. figure 5-3. format of clock operati on status control register (csc) address: fffa1h after reset: c0h r/w symbol <7> <6> 5 4 3 2 1 <0> csc mstop xtstop 0 0 0 0 0 hiostop high-speed system clock operation control mstop x1 oscillation mode external clock input mode input port mode 0 x1 oscillator operating external clock from exclk pin is valid 1 x1 oscillator stopped external clock from exclk pin is invalid input port subsystem clock operation control xtstop xt1 oscillation mode input port mode 0 xt1 oscillator operating 1 xt1 oscillator stopped input port hiostop internal high-speed oscillation clock operation control 0 internal high-speed oscillator operating 1 internal high-speed oscillator stopped ( cautions are listed on the next page.) chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 175 cautions 1. after reset release, set the clo ck operation mode control register (cmc) before setting csc. 2. to start x1 oscillation as set by msto p, check the oscillation stabilization time of the x1 clock by using the oscillation st abilization time counter status register (ostc). 3. do not stop the clock selected fo r the cpu peripheral hardware clock (f clk ) with the osc register. 4. the setting of the flags of the regist er to stop clock oscillation (invalidate the external clock input) and the condition befo re clock oscillation is to be stopped are as follows. table 5-2. condition before stoppin g clock oscillation and flag setting clock condition befo re stopping clock (invalidating external clock input) setting of csc register flags x1 clock external main system clock cpu and peripheral hardware cl ocks operate with a clock other than the high-speed system clock. (cls = 0 and mcs = 0, or cls = 1) mstop = 1 subsystem clock cpu and peripheral har dware clocks operate with a clock other than the subsystem clock. (cls = 0) xtstop = 1 internal high-speed oscillation clock cpu and peripheral hardware cl ocks operate with a clock other than the internal high-speed oscillator clock. (cls = 0 and mcs = 1, or cls = 1) hiostop = 1 (3) oscillation stabilization time c ounter status register (ostc) this is the register that indicates the count status of the x1 clock osci llation stabilization time counter. the x1 clock oscillation stabilization time can be checked in the following case, ? if the x1 clock starts oscillation while the internal hi gh-speed oscillation clock or subsystem clock is being used as the cpu clock. ? if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock with the x1 clock oscillating. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset signal is generated, the stop instruction and mstop (bit 7 of csc register) = 1 clear ostc to 00h. remark the oscillation stabilization time counter starts counting in the following cases. ? when oscillation of the x1 clock starts (exclk, oscsel = 0, 1 mstop = 0) ? when the stop mode is released chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 176 figure 5-4. format of oscillation stabilizati on time counter status register (ostc) address: fffa2h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc most 8 most 9 most 10 most 11 most 13 most 15 most 17 most 18 oscillation stabilization time status most 8 most 9 most 10 most 11 most 13 most 15 most 17 most 18 f x = 10 mhz f x = 20 mhz 0 0 0 0 0 0 0 0 2 8 /f x max. 25.6 s max. 12.8 s max. 1 0 0 0 0 0 0 0 2 8 /f x min. 25.6 s min. 12.8 s min. 1 1 0 0 0 0 0 0 2 9 /f x min. 51.2 s min. 25.6 s min. 1 1 1 0 0 0 0 0 2 10 /f x min. 102.4 s min. 51.2 s min. 1 1 1 1 0 0 0 0 2 11 /f x min. 204.8 s min. 102.4 s min. 1 1 1 1 1 0 0 0 2 13 /f x min. 819.2 s min. 409.6 s min. 1 1 1 1 1 1 0 0 2 15 /f x min. 3.27 ms min. 1.64 ms min. 1 1 1 1 1 1 1 0 2 17 /f x min. 13.11 ms min. 6.55 ms min. 1 1 1 1 1 1 1 1 2 18 /f x min. 26.21 ms min. 13.11 ms min. cautions 1. after the above time has elapsed, the bits are set to 1 in order from most8 and remain 1. 2. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. in the following cases, set the oscillation stabilization time of osts to the value greater than the count value which is to be checked by the ostc register after the oscillation starts. ? if the x1 clock starts oscillation while th e internal high-speed oscillation clock or subsystem clock is bein g used as the cpu clock. ? if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cp u clock with the x1 clock oscillating. (note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r the stop mode is released.) 3. the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 177 (4) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillation stabilization wait time when the stop mode is released. when the x1 clock is selected as t he cpu clock, the operation automatically waits for the time set using osts after the stop mode is released. when the internal high-speed oscillation clock is selected as the cpu clock, confirm with ostc that the desired oscillation stabilization time has elaps ed after the stop mode is released. the oscillation stabilization time can be checked up to the time set using ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets osts to 07h. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 178 figure 5-5. format of oscillation stabiliz ation time select register (osts) address: fffa3h after reset: 07h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 oscillation stabilization time selection osts2 osts1 osts0 f x = 10 mhz f x = 20 mhz 0 0 0 2 8 /f x 25.6 s setting prohibited 0 0 1 2 9 /f x 51.2 s 25.6 s 0 1 0 2 10 /f x 102.4 s 51.2 s 0 1 1 2 11 /f x 204.8 s 102.4 s 1 0 0 2 13 /f x 819.2 s 409.6 s 1 0 1 2 15 /f x 3.27 ms 1.64 ms 1 1 0 2 17 /f x 13.11 ms 6.55 ms 1 1 1 2 18 /f x 26.21 ms 13.11 ms cautions 1. to set the stop mode when the x1 clock is used as th e cpu clock, set the osts register before executi ng the stop instruction. 2. setting the oscillation stabilization time to 20 s or less is prohibited. 3. to change the setting of the osts regist er, be sure to confirm that the counting operation of the ostc register has been completed. 4. do not change the value of the osts register during the x1 clock oscillation stabilization time. 5. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. in the following cases, set the oscillation stabilization time of osts to the value greater than the count value which is to be checked by the ostc register after the oscillation starts. ? if the x1 clock starts oscillation while th e internal high-speed oscillation clock or subsystem clock is bein g used as the cpu clock. ? if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock with the x1 clock oscillating. (note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r the stop mode is released.) 6. the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 179 (5) system clock control register (ckc) this register is used to select a cpu/per ipheral hardware clock and a division ratio. ckc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 09h. figure 5-6. format of system clock control register (ckc) address: fffa4h after reset: 09h r/w note 1 symbol <7> <6> <5> <4> 3 2 1 0 ckc cls css mcs mcm0 1 mdiv2 mdiv1 mdiv0 cls status of cpu/peripheral hardware clock (f clk ) 0 main system clock (f main ) 1 subsystem clock (f sub ) mcs status of main system clock (f main ) 0 internal high-speed oscillation clock (f ih ) 1 high-speed system clock (f mx ) css mcm0 mdiv2 mdiv1 mdiv0 selection of cpu/peripheral hardware clock (f clk ) 0 0 0 f ih 0 0 1 f ih /2 (default) 0 1 0 f ih /2 2 0 1 1 f ih /2 3 1 0 0 f ih /2 4 0 0 1 0 1 f ih /2 5 0 0 0 f mx 0 0 1 f mx /2 0 1 0 f mx /2 2 0 1 1 f mx /2 3 1 0 0 f mx /2 4 0 1 1 0 1 f mx /2 5 note 2 1 note 3 note 3 f sub /2 other than above setting prohibited notes 1. bits 7 and 5 are read-only. 2. setting is prohibited when f mx < 4 mhz. 3. changing the value of the mcm0 bit is prohibited while css is set to 1. remarks 1. f ih : internal high-speed oscillation clock frequency f mx : high-speed system clock frequency f sub : subsystem clock frequency 2. : don?t care ( cautions 1 to 3 are listed on the next page.) chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 180 cautions 1. be sure to set bit 3 to 1. 2. the clock set by css, mcm0, and md iv2 to mdiv0 is supplied to the cpu and peripheral hardware. if the cpu clock is changed, therefore, the clock supplied to peripheral hardware (e xcept the real-time counter, clock output/buzzer output, and watchdog timer) is also changed at the same time. consequently, stop each peripheral function when changing th e cpu/peripheral hardware clock. 3. if the peripheral hardware clock is used as the subsystem cl ock, the operations of the a/d converter and iica are not guaranteed. for the operating characteristics of the peri pheral hardware, refer to the chapters describing the various peripheral hardware as well as chapter 28 electrical specifications (target). the fastest instruction can be execut ed in 1 clock of the cpu clock in the 78k0r/kx3-l. therefore, the relationship between the cpu clock (f clk ) and the minimum instruction execution time is as shown in table 5-3. table 5-3. relationship between cpu clo ck and minimum instruction execution time minimum instruction execution time: 1/f clk main system clock (css = 0) high-speed system clock (mcm0 = 1) internal high-speed oscillation clock (mcm0 = 0) subsystem clock (css = 1) cpu clock (value set by the mdiv2 to mdiv0 bits) at 10 mhz operation at 20 mhz operation at 8 mhz (typ.) operation at 32.768 khz operation f main 0.1 s 0.05 s 0.125 s (typ.) ? f main /2 0.2 s 0.1 s 0.25 s (typ.) (default) ? f main /2 2 0.4 s 0.2 s 0.5 s (typ.) ? f main /2 3 0.8 s 0.4 s 1.0 s (typ.) ? f main /2 4 1.6 s 0.8 s 2.0 s (typ.) ? f main /2 5 3.2 s 1.6 s 4.0 s (typ.) ? f sub /2 ? ? 61 s remark f main : main system clock frequency (f ih or f mx ) f sub : subsystem clock frequency chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 181 (6) 20 mhz internal high-speed osc illation control register (dscctl) this register controls the 20 mhz internal high-speed oscillation clock (dsc) function. it can be used to select whether to use the 20 mhz internal high-speed oscillation clock (f ih20 ) as a peripheral hardware clock that supports 20 mhz. dscctl can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 5-7. format of 20 mhz internal high-sp eed oscillation control register (dscctl) address: f00f6h after reset: 00h r/w note symbol 7 6 5 4 <3> <2> 1 <0> dscctl 0 0 0 0 dscs seldsc 0 dscon dscs 20 mhz internal high-speed oscillation supply status flag 0 not supplied 1 supplied seldsc selection of 20 mhz internal high-speed oscillation for cpu/peripheral hardware clock (f clk ) 0 does not select 20 mhz inter nal high-speed oscillation (clock selected by ckc register is supplied to f clk ) 1 selects 20 mhz internal high-speed oscillati on (20 mhz internal hi gh-speed oscillation is supplied to f clk ) dscon 20 mhz internal hi gh-speed oscillation clock (f ih20 ) operation enable/disable 0 disables operation. 1 enables operation. note bit 3 is read-only. caution set seldsc when 100 s have elapsed after h aving set dscon with v dd 2.7 v. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 182 (7) peripheral enable registers 0, 1, 2 (per0, per1, per2) these registers are used to enable or disable use of each peripheral hardware macro. clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. per0, per1, per2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears theses registers to 00h. figure 5-8. format of peripheral enable registers (1/2) address: f00f0h after reset: 00h r/w symbol <7> 6 <5> <4> 3 <2> 1 0 per0 rtcen 0 adcen iicaen note 1 0 sau0en 0 0 address: f00f1h after reset: 00h r/w symbol 7 6 5 4 <3> 2 1 0 per1 0 0 0 0 oacmpen 0 0 0 address: f00f2h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> per2 0 0 0 0 0 0 0 tau0en rtcen control of real-time c ounter (rtc) input clock supply note 2 0 stops input clock supply. ? sfr used by the real-time counter (rtc) cannot be written (can be read). ? operation of the real-time counter (rtc) continues. 1 supplies input clock. ? sfr used by the real-time counter (rtc) can be read and written. adcen control of a/d co nverter input clock supply 0 stops input clock supply. ? sfr used by the a/d converter cannot be written. ? the a/d converter is in the reset status. 1 supplies input clock. ? sfr used by the a/d converter can be read and written. notes 1. this is not mounted onto 44-pi n products of the 78k0r/kc3-l 2. the input clock that can be c ontrolled by rtcen is used when t he register that is used by the real-time counter (rtc) is accessed from the cpu. rtcen cannot control supply of the operating clock (f sub ) to rtc. caution be sure to clear bits 0, 1, 3, and 6 (44-pin products: bits 0, 1, 3, 4, and 6) of the per0 register, bits 0 to 2 and 4 to 7 of the per1 register, a nd bits 1 to 7 of the per2 register to 0. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 183 figure 5-8. format of peripheral enable registers (2/2) address: f00f0h after reset: 00h r/w symbol <7> 6 <5> <4> 3 <2> 1 0 per0 rtcen 0 adcen iicaen note 0 sau0en 0 0 address: f00f1h after reset: 00h r/w symbol 7 6 5 4 <3> 2 1 0 per1 0 0 0 0 oacmpen 0 0 0 address: f00f2h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> per2 0 0 0 0 0 0 0 tau0en iicaen control of serial interface iica input clock supply 0 stops input clock supply. ? sfr used by the serial interface iica cannot be written. ? the serial interface iica is in the reset status. 1 supplies input clock. ? sfr used by the serial interface iica can be read and written. sau0en control of serial array unit input clock supply 0 stops input clock supply. ? sfr used by the serial ar ray unit cannot be written. ? the serial array unit is in the reset status. 1 supplies input clock. ? sfr used by the serial arra y unit can be read and written. oacmpen control of comparator and prog rammable gain amplifie r input clock supply 0 stops input clock supply. ? sfr used by the comparator and programmable gain amplifier cannot be written. ? the comparator and programmable gain amplifier is in the reset status. 1 supplies input clock. ? sfr used by the comparator and programmable gain amplifier can be read and written. tau0en control of timer arra y unit taus input clock supply 0 stops input clock supply. ? sfr used by timer array unit taus cannot be written. ? timer array unit taus is in the reset status. 1 supplies input clock. ? sfr used by timer array unit taus can be read and written. note this is not mounted onto 44-pi n products of the 78k0r/kc3-l caution be sure to clear bits 0, 1, 3, and 6 (44-pin products: bits 0, 1, 3, 4, and 6) of the per0 register, bits 0 to 2 and 4 to 7 of the per1 register, a nd bits 1 to 7 of the per2 register to 0. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 184 (8) operation speed mode control register (osmc) flpc and fsel can be used to control the step-up circ uit of the flash memory for high-speed operation. if the microcontroller operat es at a low speed with a syst em clock of 10 mhz or less, the power consumption can be lowered by setting this register to the default value, 00h. furthermore, when operating the system clock at 1 mhz, the power consumption can be fu rther reduced by setting flpc to 1. rtclpc can be used to set the operat ion in subsystem clock halt mode. osmc can be set by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 5-9. format of operation speed mode control register (osmc) address: f00f3h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 osmc rtclpc 0 0 0 0 0 flpc fsel flpc fsel f clk frequency selection 0 0 operates at a frequency of 10 mhz or less (default). 0 1 operates at a frequency higher than 10 mhz. 1 0 operates at a frequency of 1 mhz. 1 1 setting prohibited rtclpc setting in subsystem clock halt mode 0 enables supply of subsystem clock to peripheral functions (see table 18-1 for peripheral functi ons whose operations are enabled.) 1 stops supply of subsystem cl ock to peripheral functions other than real-time counter cautions 1. write ?1? to fsel be fore the followin g two operations. ? changing the clock prior to dividing f clk to a clock other than f ih . ? operating the dma controller. 2. the cpu waits when ?1? is written to the fsel flag. the wait time is 15 s to 20 s (target) when f clk = f ih , and 30 s to 40 s (target) when f clk = f ih /2. however, counting the oscillati on stabilization time of f x can continue even while the cpu is waiting. 3. to increase f clk to 10 mhz or higher, set f sel to ?1?, then change f clk after two or more clocks have elapsed. 4. even when set to fsel = 1, the system clock can be operated at a frequency of 10 mhz or less. when setting fsel to ?1 ?, however, do so while v dd 2.25 v. when set to fsel = 1, make sure that v dd 2.25 v at the following timings, even if f clk is divided. ? when releasing f ih or f ex from the stop mode selected for f clk ? when switching f clk from f sub to f main (cautions are given on the next page.) chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 185 5. the halt mode current when the subsyst em clock is used can be reduced by setting rtclpc to 1. however, no clo ck can be supplied to the peripheral functions other than the real-time count er during subsystem clock halt mode. set bit 7 (rtcen) of per0 to 1, and all of bi ts 0 to 6 of per0, bits 0 to 7 of per1, and bits 0 to 7 of per2 to 0 befo re setting subsystem clock halt mode. 6 if flpc is once set from 0 to 1, it is pr ohibited to set it back from 1 to 0, other than by a reset. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 186 5.4 system clock oscillator 5.4.1 x1 oscillator the x1 oscillator oscillates with a cryst al resonator or ceramic resonator (2 to 20 mhz) connected to the x1 and x2 pins. an external clock can also be input. in this case, input the clock signal to the exclk pin. to use the x1 oscillator, set bits 7 and 6 (exclk, oscsel) of the clock operation mode control register (cmc) as follows. ? crystal or ceramic oscillation: exclk, oscsel = 0, 1 ? external clock input: exclk, oscsel = 1, 1 when the x1 oscillator is not used, set the input port mode (exclk, oscsel = 0, 0). when the pins are not used as input port pins, either, see table 2-2 connection of unused pins . figure 5-10 shows an example of the exte rnal circuit of the x1 oscillator. figure 5-10. example of extern al circuit of x1 oscillator (a) crystal or ceramic osc illation (b) external clock v ss x1 x2 crystal resonator or ceramic resonator exclk external clock cautions are listed on the next page. 5.4.2 xt1 oscillator the xt1 oscillator oscillates with a crystal resonator (standard: 32.768 khz) connected to the xt1 and xt2 pins. to use the xt1 oscillator, set bit 4 (oscsels) of t he clock operation mode control register (cmc) to 1. when the xt1 oscillator is not used, set the input port mode (oscsels = 0). when the pins are not used as input port pins, either, see table 2-2 connection of unused pins . figure 5-11 shows an example of the exte rnal circuit of the xt1 oscillator. figure 5-11. example of external circuit of xt1 oscillator (crystal oscillation) xt2 v ss xt1 32.768 khz cautions are listed on the next page. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 187 caution 1. when using the x1 oscillator and xt1 osc illator, wire as follows in the area enclosed by the broken lines in the figures 5-10 and 5-11 to avoid an adverse e ffect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor th e same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. the xt1 oscillator is a circuit with low am plification in order to achieve low-power consumption. note the following points when designing the circuit. ? pins and circuit boards include parasitic capacitance. therefore, perform oscillation evaluation using a circuit board to be actually used and confirm that there are no problems. ? when using the ultra-low power consumption oscillation (amphs1 = 1) as the mode of the xt1 oscillator, use the recommended resona tors described in chapter 28 electrical specifications (target). ? make the wiring between the xt 1 and xt2 pins and the resona tors as short as possible, and minimize the parasitic capacitan ce and wiring resistance. note this particularly when the ultra-low power consumption osc illation (amphs1 = 1) is selected. ? configure the circuit of the circuit board, using material with little wiring resistance. ? place a ground pattern that h as the same potential as v ss as much as possi ble near the xt1 oscillator. ? be sure that the signal lines between the xt1 and xt2 pins, and the r esonators do not cross with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. ? the impedance between the xt1 and xt2 pins may drop and oscillation may be disturbed due to moisture absorption of the circuit boa rd in a high-humidity environment or dew condensation on the board. when using the ci rcuit board in such an environment, take measures to damp-proof the circ uit board, such as by coating. ? when coating the ci rcuit board, use mate rial that does not cau se capacitance or leakage between the xt1 and xt2 pins. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 188 figure 5-12 shows examples of incorrect resonator connection. figure 5-12. examples of incorr ect resonator connection (1/2) (a) too long wiring (b) crossed signal line x2 v ss x1 x1 ng ng ng v ss x2 port (c) the x1 and x2 signal line wires cross. (d) a power supply/gnd pattern exists under the x1 and x2 wires. x2 v ss x1 x1 power supply/gnd pattern v ss x2 note note do not place a power supply/gnd pattern under the wiri ng section (section indicated by a broken line in the figure) of the x1 and x2 pins and the resonator s in a multi-layer board or double-sided board. do not configure a layout that will cause capacitance elements and affect the oscillation characteristics. remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 189 figure 5-12. examples of incorr ect resonator connection (2/2) (e) wiring near high alternating current (f) cu rrent flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 v ss x1 x2 ab c pmn v dd high current high current (g) signals are fetched v ss x1 x2 remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. caution 2. when x2 and xt1 are wired in parallel, the crosstalk noi se of x2 may increase with xt1, resulting in malfunctioning. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 190 5.4.3 internal hi gh-speed oscillator note the internal high-speed oscillator is incorporated in the 78k0r/kx3-l (1, 8 mhz (t yp.)). oscillation can be controlled by bit 0 (hiostop) of the clock operation status cont rol register (csc). 5.4.4 20 mhz internal high-speed oscillator note the 20 mhz internal high-speed oscillator is incorporated in the 78k0r/kx3-l (20 mhz (typ.)). oscillation can be controlled by bit 0 (dscon) of the 20 mhz internal hi gh-speed oscillation control register (dscctl) with v dd 2.7 v. after a reset release, the 20 mhz internal high-speed os cillator starts oscillating by setting bit 0 (dscon) of the dscctl register to 1. note to use the 1, 8, or 20 mhz internal high-speed oscill ation clock, use the option byte to set the frequency in advance (for details, see chapter 23 option byte ). also, the internal high-speed oscillator automatically starts oscillating after reset release. to use the 20 mhz internal high-speed oscillator to operate the microcontroller, o scillation is started by setting bit 0 (d scon) of the 20 mhz internal high-speed oscillation control register (dscctl) to 1 with v dd 2.7 v. 5.4.5 internal low-speed oscillator the internal low-speed oscillator is incorporated in the 78k0r/kx3-l. the internal low-speed oscillation clock is used only as the watchdog timer clock. the internal low-speed oscillation clock cannot be used as the cpu clock. after a reset release, the internal low-speed oscillator au tomatically starts oscillation, and the watchdog timer is driven (30 khz (typ.)) if the watchdog timer operation is enabled by the option byte. the internal low-speed oscillator c ontinues oscillation except when the wa tchdog timer stops. when the watchdog timer operates, the internal low-speed oscillation clo ck does not stop, even in case of a program loop. 5.4.6 prescaler the prescaler generates a cp u/peripheral hardware cl ock by dividing the main system clock and subsystem clock. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 191 5.5 clock generator operation the clock generator generates the following clocks and cont rols the operation modes of the cpu, such as standby mode (see figure 5-1 ). ? main system clock f main ? high-speed system clock f mx x1 clock f x external main system clock f ex ? internal high-speed oscillation clock f ih ? 20 mhz internal high-speed oscillation clock f ih20 ? subsystem clock f sub ? internal low-speed oscillation clock f il ? cpu/peripheral hardware clock f clk the cpu starts operation when the internal high-speed osc illator starts outputting after a reset release in the 78k0r/kx3-l. when the power supply voltage is turned on, the clock gen erator operation is shown in figure 5-13 to figure 5-16. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 192 figure 5-13. clock generator operation wh en power supply voltage is turned on (when lvi default start function stoppe d is set (option byte: lvioff = 1)) internal high-speed oscillation clock (f rh ) cpu clock high-speed system clock (f xh ) (when x1 oscillation selected) internal high-speed oscillation clock high-speed system clock switched by software subsystem clock (f sub ) (when xt1 oscillation selected) subsystem clock x1 clock oscillation stabilization time note 2 starting x1 oscillation is set by software. starting xt1 oscillation is set by software. reset processing (about 2.1 to 5.8 ms) internal reset signal 0 v 1.61 v (typ.) 1.8 v 0.5 v/ms (min.) power supply voltage (v dd ) <1> <2> <4> <5> <5> <4> note 1 <3> <1> when the power is turned on, an internal reset signal is generated by the power-on-clear (poc) circuit. <2> when the power supply voltage exceeds 1.61 v (typ.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> when the power supply voltage rises with a slope of 0.5 v/ms (min.), the cp u starts operation on the internal high-speed oscillation clock after a reset proc essing such as waiting for the voltage of the power supply or regulator to stabilize has been performed after reset release. <4> set the start of oscillation of the x1 or xt1 clock via software (see (1) in 5.6.1 example of controlling high- speed system clock and (1) in 5.6.3 example of cont rolling subsystem clock) . <5> when switching the cpu clock to the x1 or xt1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see (3) in 5.6.1 example of controlli ng high-speed system clock and (2) in 5.6.3 example of controlling subsystem clock ). notes 1. the internal reset processing time includes the o scillation accuracy stabilization time of the internal high-speed oscillation clock. 2. when releasing a reset (above figure) or releas ing stop mode while the cpu is operating on the internal high-speed oscillation clock, confirm the osc illation stabilization time for the x1 clock using the oscillation stabilization time count er status register (ostc). if the cpu operates on the high-speed system clock (x1 oscillation), set the oscillation st abilization time when releasing stop mode using the oscillation stabilization time select register (osts). chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 193 cautions 1. if the voltage rises wit h a slope of less than 0.5 v/ms (min .) from power application until the voltage reaches 1.8 v, input a lo w level to the reset pin from power application until the voltage reaches 1.8 v, or set the lvi default st art function stopped by using the option byte (lvioff = 0) (see figure 5-14). by doing so , the cpu operates with the same timing as <2> and thereafter in figure 5-13 afte r reset release by the reset pin. 2. it is not necessary to wait for the oscillati on stabilization time when an external clock input from the exclk pin is used. remark while the microcontroller is operating, a clock t hat is not used as the cpu clock can be stopped via software settings. the internal high-speed oscill ation clock and high-speed system clock can be stopped by executing the stop instruction (see (4) in 5.6.1 example of controlli ng high-speed system clock , (3) in 5.6.2 example of controlling inte rnal high-speed oscillation clock , and (3) in 5.6.3 example of controlling subsystem clock ). figure 5-14. clock generator operation wh en power supply voltage is turned on (when lvi default start function enable d is set (option byte: lvioff = 0)) internal high-speed oscillation clock (f rh ) cpu clock high-speed system clock (f xh ) (when x1 oscillation selected) internal high-speed oscillation clock high-speed system clock switched by software subsystem clock (f sub ) (when xt1 oscillation selected) subsystem clock x1 clock oscillation stabilization time note 2 starting x1 oscillation is set by software. starting xt1 oscillation is set by software. internal reset signal 0 v 2.07 v (typ.) power supply voltage (v dd ) <1> <3> <2> <4> <5> reset processing (about 195 to 322 s) <4> <5> note 1 <1> when the power is turned on, an internal reset signal is generated by the power-on-clear (poc) circuit. <2> when the power supply voltage exceeds 2.07 v (typ.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> after the reset is released and reset processing is performed, the cpu starts operation on the internal high- speed oscillation clock. <4> set the start of oscillation of the x1 or xt1 clock via software (see (1) in 5.6.1 example of controlling high- speed system clock and (1) in 5.6.3 example of controlling subsystem clock ). <5> when switching the cpu clock to the x1 or xt1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see (3) in 5.6.1 example of controlli ng high-speed system clock and (2) in 5.6.3 example of controlling subsystem clock ). chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 194 notes 1. the internal reset processing time includes the o scillation accuracy stabilization time of the internal high-speed oscillation clock. 2. when releasing a reset (above figure) or releas ing stop mode while the cpu is operating on the internal high-speed oscillation clock, confirm the osc illation stabilization time for the x1 clock using the oscillation stabilization time count er status register (ostc). if the cpu operates on the high-speed system clock (x1 oscillation), set the oscillation st abilization time when releasing stop mode using the oscillation stabilization time select register (osts). cautions 1. a voltage stabilization time (about 2.0 to 5.8 ms) is requi red after the supply voltage reaches 1.61 v (typ.). if the time for the supply voltage to rise from 1.61 v (typ.) to 2.07 v (typ.) is shorter than the voltage stabilization time, reset processing is ente red after the voltage stabilization time elapses. 2. it is not necessary to wait for the oscillation stabilization ti me when an external clock input from the exclk pin is used. remark while the microcontroller is operating, a clock t hat is not used as the cpu clock can be stopped via software settings. the internal high-speed oscill ation clock and high-speed system clock can be stopped by executing the stop instruction (see (4) in 5.6.1 example of controlli ng high-speed system clock, (3) in 5.6.2 example of controlling inte rnal high-speed oscillation clock , and (3) in 5.6.3 example of controlling subsystem clock ). chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 195 figure 5-15. clock generator operation wh en power supply voltage is turned on (when lvi default start function sto pped is set (option byte: lvioff = 1) and changing to 20 mhz internal high-speed oscillation clock) internal high-speed oscillation clock (f ih8 ) cpu clock 20 mhz internal high-speed oscillation clock (f ih20 ) 8 mhz internal high-speed oscillation clock 20 mhz internal high-speed oscillation clock switched by software (seldsc = 1) 20 mhz internal high-speed oscillation clock oscillation stabilization time: 100 s dscon = 1 is set by software. reset processing (about 2.1 to 5.8 ms) internal reset signal 0 v 1.61 v (typ.) 1.8 v 0.5 v/ms (min.) power supply voltage (v dd ) <1> <2> <3> <4> <5> note 2.7 v <1> when the power is turned on, an internal reset signal is generated by the power-on-clear (poc) circuit. <2> when the power supply voltage exceeds 1.61 v (typ.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> when the power supply voltage rises with a slope of 0.5 v/ms (min.), the cp u starts operation on the internal high-speed oscillation clock after a reset proc essing such as waiting for the voltage of the power supply or regulator to stabilize has been performed after reset release. <4> check that the power supply voltage is 2.7 v or more and set dscon = 1 by software. <5> switch the clock by setting seldsc = 1 by software after waiting for 100 s. note the internal reset processing time includes the oscill ation accuracy stabilization time of the internal high- speed oscillation clock. cautions 1. to use the 20 mhz inte rnal high-speed oscillation clock, use bits 2 and 1 (frqsel2 and frqsel1) of the option byte (000c1h) to set the frequency to 20 mhz in advance (for details, see chapter 23 option byte). 2. if the voltage rises with a slope of less than 0.5 v/ms (min.) from power application until the voltage reaches 1.8 v, input a lo w level to the reset pin from power application until the voltage reaches 1.8 v, or set the lvi default st art function stopped by using the option byte (lvioff = 0) (see figure 5-16). by doing so , the cpu operates with the same timing as <2> and thereafter in figure 5-15 afte r reset release by the reset pin. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 196 figure 5-16. clock generator operation wh en power supply voltage is turned on (when lvi default start function enab led is set (option byte: lvioff = 0) and changing to 20 mhz internal high-speed oscillation clock) internal high-speed oscillation clock (f ih8 ) cpu clock 20 mhz internal high-speed oscillation clock (f ih20 ) 8 mhz internal high-speed oscillation clock 20 mhz internal high-speed oscillation clock switched by software (seldsc = 1) dscon = 1 is set by software. reset processing (about 195 to 322 s) internal reset signal 0 v 2.07 v (typ.) 2.7 v power supply voltage (v dd ) <1> <2> <3> <4> note 20 mhz internal high-speed oscillation clock oscillation stabilization time: 100 s <1> when the power is turned on, an internal reset signal is generated by the power-on-clear (poc) circuit. <2> when the power supply voltage exceeds 2.07 v (typ.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> after the reset is released and reset processing is performed, the cpu starts operation on the internal high- speed oscillation clock. <4> check that the power supply voltage is 2.7 v or more and set dscon = 1 by software. <5> switch the clock by setting seldsc = 1 by software after waiting for 100 s. note the internal reset processing time includes the oscill ation accuracy stabilization time of the internal high- speed oscillation clock. cautions 1. to use the 20 mhz inte rnal high-speed oscillation clock, use bits 2 and 1 (frqsel2 and frqsel1) of the option byte (000c1h) to set the frequency to 20 mhz in advance (for details, see chapter 23 option byte). 2. a voltage stabilization time (about 2.0 to 5.8 ms) is required after the supply voltage reaches 1.61 v (typ.). if the time for the supply voltage to rise from 1.61 v (typ.) to 2.07 v (typ.) is shorter than the voltage stabilization time, reset processing is ente red after the voltage stabilization time elapses. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 197 5.6 controlling clock 5.6.1 example of control ling high-speed system clock the following two types of high-s peed system clocks are available. ? x1 clock: crystal/ceramic resonator is connected to the x1 and x2 pins. ? external main system clock: exter nal clock is input to the exclk pin. when the high-speed system clock is not used, the x1/p121 and x2/exclk/p122 pins can be used as input port pins. caution the x1/p121 and x2/exclk/p122 pins are in the input port mode after a reset release. the following describes examples of setti ng procedures for the following cases. (1) when oscillating x1 clock (2) when using external main system clock (3) when using high-speed system clo ck as cpu/peripheral hardware clock (4) when stopping high-speed system clock (1) example of setting procedure when oscillating the x1 clock <1> setting p121/x1 and p122/x2/exclk pins and setting oscillation frequency (cmc register) ? 2 mhz f x 10 mhz exclk oscsel 0 oscsels 0 amphs1 amphs0 amph 0 1 0 0/1 0 0/1 0/1 0 ? 10 mhz < f x 20 mhz exclk oscsel 0 oscsels 0 amphs1 amphs0 amph 0 1 0 0/1 0 0/1 0/1 1 remarks 1. f x : x1 clock oscillation frequency 2. for setting of the p123/xt1 and p124/xt2 pins, see 5.6.3 example of controlling subsystem clock . <2> controlling oscillation of x1 clock (csc register) if mstop is cleared to 0, the x1 oscillator starts oscillating. <3> waiting for the stabilization of the oscillation of x1 clock check the ostc register and wait for the necessary time. during the wait time, other software processing can be executed with the internal high-speed oscillation clock. cautions 1. the cmc register can be written only once after reset release, by an 8-bit memory manipulation instruction. therefore, it is necessary to also set the val ue of the oscsels bit at the same time. for oscsels bit, see 5.6.3 example of controlling subsystem clock. 2. set the x1 clock after th e supply voltage has reached the ope rable voltage of the clock to be used (see chapter 28 electr ical specifications (target)). chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 198 (2) example of setting procedure when using the external main system clock <1> setting p121/x1 and p122/x2/exclk pins (cmc register) exclk oscsel 0 oscsels 0 amphs1 amphs0 amph 1 1 0 0/1 0 0/1 0/1 0/1 remark for setting of the p123/xt 1 and p124/xt2 pins, see 5.6.3 (1) example of setting procedure when oscillating the subsystem clock . <2> controlling external main syst em clock input (csc register) when mstop is cleared to 0, the input of the external main system clock is enabled. cautions 1. the cmc register can be written only once after reset release, by an 8-bit memory manipulation instruction. therefore, it is necessary to al so set the value of the oscsel s bits at the same time. for oscsels bits, see 5.6.3 example of controlling subsystem clock. 2. set the external main system clock after the supply voltage has reached the operable voltage of the clock to be used (see chapter 28 electrical specifications (target)). (3) example of setting procedure wh en using high-speed system clock as cpu/peripheral hardware clock <1> setting high-speed system clock oscillation note (see 5.6.1 (1) example of setting proc edure when oscillating the x1 clock and (2) example of setting procedure when using th e external main system clock. ) note the setting of <1> is not necessary when hi gh-speed system clock is already operating. <2> setting the high-speed system clock as the source clock of the cpu/peripheral hardware clock and setting the division ratio of the set clock (ckc register) mcm0 mdiv2 mdiv1 mdiv0 selection of cpu/peripheral hardware clock (f clk ) 0 0 0 f mx 0 0 1 f mx /2 0 1 0 f mx /2 2 0 1 1 f mx /2 3 1 0 0 f mx /2 4 1 1 0 1 f mx /2 5 note note setting is prohibited when f mx < 4 mhz. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 199 <3> if some peripheral hardware macros are not used, s upply of the input clock to each hardware macro can be stopped. (per0 register) rtcen 0 adcen iicaen note 0 sau0en 0 0 (per1 register) 0 0 0 0 oacmpen 0 0 0 (per2 register) 0 0 0 0 0 0 0 tau0en xxxen input clock control 0 stops input clock supply. 1 supplies input clock. note this is not mounted onto 44-pi n products of the 78k0r/kc3-l caution be sure to clear the following bits to 0. ? bits 0, 1, 3, and 6 of the per0 register (bits 0, 1, 3, 4, and 6 for 44-pin products of 78k0r/kc3-l) ? bits 0 to 2 and 4 to 7 of the per1 register ? bits 1 to 7 of the per2 register remark rtcen: control of the r eal-time counter input clock adcen: control of the a/d converter input clock iicaen: control of the serial interface iica input clock sau0en: control of the serial array unit input clock oacmpen: control of the program mable gain amplifier input clock tau0en: control of the timer array unit taus input clock (4) example of setting procedure when stopping the high-speed system clock the high-speed system clock can be stopped (disabling clock input if the external clock is used) in the following two ways. ? executing the stop instruction ? setting mstop to 1 (a) to execute a stop instruction <1> setting to stop peripheral hardware stop peripheral hardware that cannot be used in the stop mode (for per ipheral hardware that cannot be used in stop mode, see chapter 18 standby function ). <2> setting the x1 clock oscillation stabilization time after stop mode is released if the x1 clock oscillates before t he stop mode is entered, set the va lue of the osts register before executing the stop instruction. <3> executing the stop instruction when the stop instruction is exec uted, the system is placed in t he stop mode and x1 oscillation is stopped (the input of the exte rnal clock is disabled). chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 200 (b) to stop x1 oscillation (disabling exter nal clock input) by setting mstop to 1 <1> confirming the cpu clock status (ckc register) confirm with cls and mcs that the cpu is oper ating on a clock other than the high-speed system clock. when cls = 0 and mcs = 1, the high-speed system cl ock is supplied to the cpu, so change the cpu clock to the subsystem clock or internal high-speed oscillation clock. cls mcs cpu clock status 0 0 internal high-speed oscillation cl ock or 20 mhz internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> setting of x1 clock oscillation stabilizatio n time after restart of x1 clock oscillation note prior to setting "1" to mstop, set the osts regi ster to a value greater than the count value to be confirmed with the osts register afte r x1 clock oscillation is restarted. <3> stopping the high-speed system clock (csc register) when mstop is set to 1, x1 oscillation is stopp ed (the input of the external clock is disabled). note this setting is required to resume the x1 clock oscillation when the high-speed system clock is in the x1 oscillation mode. this setting is not required in the external clock input mode. caution be sure to confirm that mcs = 0 or cls = 1 when setting mstop to 1. in addition, stop peripheral hardware that is operating on the high-speed system clock. 5.6.2 example of controlling inte rnal high-speed oscillation clock the following describes examples of clock setting procedures for the following cases. (1) when restarting oscillation of the internal high-speed oscillation clock (2) when using internal high-speed oscillation clock as cpu/peripheral hardware clock (3) when stopping the internal high-speed oscillation clock (1) example of setting procedure wh en restarting oscillation of the in ternal high-speed oscillation clock note <1> setting restart of oscillation of the intern al high-speed oscillation clock (csc register) when hiostop is cleared to 0, the internal hi gh-speed oscillation clock restarts oscillation. note after a reset release, the internal high-speed oscilla tor automatically starts oscillating and the internal high-speed oscillation clock is selected as the cpu/peripheral hardware clock. (2) example of setting procedure when using intern al high-speed oscillation clock as cpu/peripheral hardware clock <1> restarting oscillation of the internal high-speed oscillation clock note (see 5.6.2 (1) example of setting pr ocedure when restarting internal high-speed oscillation clock ). note the setting of <1> is not necessary when the inte rnal high-speed oscillation clock is operating. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 201 <2> setting the internal high-speed oscillation clock as the source clock of the cpu/peripheral hardware clock and setting the division ratio of the set clock (ckc register) mcm0 mdiv2 mdiv1 mdiv0 selection of cpu/peripheral hardware clock (f clk ) 0 0 0 f ih 0 0 1 f ih /2 0 1 0 f ih /2 2 0 1 1 f ih /2 3 1 0 0 f ih /2 4 0 1 0 1 f ih /2 5 caution if switching the cpu/pe ripheral hardware clock from th e high-speed system clock to the internal high-speed oscillation clock after restarting the inte rnal high-speed oscillation clock, do so after 10 s or more have elapsed. if the switching is made immediately after the internal high-speed oscillation clock is restarted, the accuracy of the internal high-speed oscillati on cannot be guaranteed for 10 s. (3) example of setting procedure when stoppi ng the internal high-speed oscillation clock the internal high-speed oscillation clock can be stopped in the following two ways. ? executing the stop instruction ? setting hiostop to 1 (a) to execute a stop instruction <1> setting of peripheral hardware stop peripheral hardware that cannot be used in the stop mode (for per ipheral hardware that cannot be used in stop mode, see chapter 18 standby function ). <2> setting the x1 clock oscillation stabilization time after stop mode is released if the x1 clock oscillates before t he stop mode is entered, set the va lue of the osts register before executing the stop instruction. <3> executing the stop instruction when the stop instruction is ex ecuted, the system is placed in the stop mode and internal high- speed oscillation clock is stopped. (b) to stop internal high-speed osc illation clock by setting hiostop to 1 <1> confirming the cpu clock status (ckc register) confirm with cls and mcs that the cpu is operat ing on a clock other than the internal high-speed oscillation clock. when cls = 0 and mcs = 0, the internal high-speed oscillation clock is supplied to the cpu, so change the cpu clock to the high-spe ed system clock or subsystem clock. cls mcs cpu clock status 0 0 internal high-speed oscillation clo ck or 20 mhz internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 202 <2> stopping the internal high-speed oscillation clock (csc register) when hiostop is set to 1, internal high-speed oscillation clock is stopped. caution be sure to confirm that mcs = 1 or cls = 1 when setting hiostop to 1. in addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock. 5.6.3 example of cont rolling subsystem clock the subsystem clock can be oscillated by connecti ng a crystal resonator to the xt1 and xt2 pins. when the subsystem clock is not us ed, the xt1/p123 and xt2/p124 pins can be used as input port pins. caution the xt1/p123 and xt2/p124 pins are in the input port mode after a reset release. the following describes examples of setti ng procedures for the following cases. (1) when oscillating subsystem clock (2) when using subsystem clock as cpu clock (3) when stopping subsystem clock caution when the subsystem clock is used as the cpu cl ock, the subsystem clock is also supplied to the peripheral hardware (except th e real-time counter, clock out put/buzzer output, and watchdog timer). at this time, the operations of the a/ d converter and iica are not guaranteed. for the operating characteristics of the peripheral hardware , refer to the chapters describing the various peripheral hardware as well as chapter 28 electrical specifications (target). (1) example of setting procedure wh en oscillating the subsystem clock <1> setting p123/xt1 and p124/xt2 pins (cmc register) exclk oscsel 0 oscsels 0 amphs1 amphs0 amph 0/1 0/1 0 1 0 0/1 0/1 0/1 remark for setting of the p121/x1 and p122/x2 pins, see 5.6.1 example of co ntrolling high-speed system clock . <2> controlling oscillation of subsystem clock (csc register) if xtstop is cleared to 0, the xt1 oscillator starts oscillating. <3> waiting for the stabilization of the subsystem clock oscillation wait for the oscillation stabilization time of the subsystem clock by software, using a timer function. caution the cmc register can be written only once after reset release, by an 8-bit memory manipulation instruction. therefore, it is necessary to also set the val ue of the exclk and oscsel bits at the same time. for exclk and oscsel bits, see 5.6.1 (1) example of setting procedure when oscillating the x1 clock or 5.6. 1 (2) example of setting pro cedure when using the external main system clock. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 203 (2) example of setting procedure when us ing the subsystem cl ock as the cpu clock <1> setting subsystem clock oscillation note (see 5.6.3 (1) example of setting procedur e when oscillating the subsystem clock .) note the setting of <1> is not necessary when while the subsystem clock is operating. <2> setting the subsystem clock as the sour ce clock of the cpu clock (ckc register) css selection of cpu/peripheral hardware clock (f clk ) 1 f sub /2 caution when the subsystem clock is used as the cp u clock, the subsystem cl ock is also supplied to the peripheral hardware (exc ept the real-time counter, clock output/buzzer output, and watchdog timer). at this time, the operat ions of the a/d converter and iica are not guaranteed. for the operating characteristics of the peripheral hardware, refer to the chapters describing the various peripheral hardware as well as chapter 28 electrical specifications (target). (3) example of setting procedure when stopping the subsystem clock <1> confirming the cpu clock status (ckc register) confirm with cls and mcs that the cpu is operat ing on a clock other than the subsystem clock. when cls = 1, the subsystem clock is supplied to t he cpu, so change the cpu clock to the internal high-speed oscillation clock or high-speed system clock. cls mcs cpu clock status 0 0 internal high-speed oscillation cl ock or 20 mhz internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the subsystem clock (csc register) when xtstop is set to 1, subsystem clock is stopped. cautions 1. be sure to confi rm that cls = 0 when setting xtstop to 1. in addition, stop the peripheral hardware if it is op erating on the subsystem clock. 2. the subsystem clock oscillation cannot be stopped using the stop instruction. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 204 5.6.4 example of controlling in ternal low-speed oscillation clock the internal low-speed oscillation clock cannot be used as the cpu clock. used only as the watchdog timer clock. the internal low-speed oscillator automat ically starts oscillation after a reset release, and the watchdog timer is driven (30 khz (typ.)) if the watchdog timer operation is enabled by the option byte. the internal low-speed oscillator c ontinues oscillation except when the wa tchdog timer stops. when the watchdog timer operates, the internal low-speed oscillation clo ck does not stop even in case of a program loop. (1) example of setting procedure when stoppi ng the internal low-speed oscillation clock the internal low-speed oscillation clock can be stopped in the following two ways. ? stop the watchdog timer in the halt/stop mode by th e option byte (bit 0 (wdstbyon) of 000c0h = 0), and execute the halt or stop instruction. ? stop the watchdog timer by the option byte (bit 4 (wdton) of 000c0h = 0). (2) example of setting procedure when restarting osc illation of the internal low-speed oscillation clock the internal low-speed oscillation clock can be restarted as follows. ? release the halt or stop mode (only when the watchdog timer is stopped in the halt/s top mode by the option byte (bit 0 (wdstbyon) of 000c0h) = 0) and when the watchdog timer is stopped as a result of executio n of the halt or stop instruction). chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 205 5.6.5 cpu clock stat us transition diagram figure 5-17 shows the cpu clock status transition diagram of this product. figure 5-17. cpu clock stat us transition diagram internal high-speed oscillation: woken up x1 oscillation/exclk input: stops (input port mode) xt1 oscillation: stops (input port mode) dsc oscillation: stops internal high-speed oscillation: operating x1 oscillation/exclk input: stops (input port mode) xt1 oscillation: stops (input port mode) dsc oscillation: stops v dd 1.61 v 0.09 v note 1 v dd 1.8 v v dd < 1.61 v 0.09 v note 1 cpu: internal high- speed oscillation stop cpu: internal high- speed oscillation halt cpu: x1 oscillation/exclk input stop internal high-speed oscillation: stops x1 oscillation/exclk input: stops xt1 oscillation: oscillatable dsc oscillation: stops internal high-speed oscillation: operating x1 oscillation/exclk input: oscillatable xt1 oscillation: oscillatable dsc oscillation: stops internal high-speed oscillation: stops x1 oscillation/exclk input: stops xt1 oscillation: oscillatable dsc oscillation: stops internal high-speed oscillation: oscillatable x1 oscillation/exclk input: operating xt1 oscillation: oscillatable dsc oscillation: stops cpu: operating with internal high- speed oscillation cpu: operating with x1 oscillation or exclk input cpu: x1 oscillation/exclk input halt power on reset release internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: operating xt1 oscillation: selectable by cpu dsc oscillation: stops internal high-speed oscillation: operating x1 oscillation/exclk input: selectable by cpu xt1 oscillation: selectable by cpu dsc oscillation: selectable by cpu cpu: operating with dsc oscillation cpu: dsc oscillation halt internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: cannot be selected by cpu xt1 oscillation: cannot be selected by cpu dsc oscillation: operating internal high-speed oscillation: oscillatable x1 oscillation/exclk input: oscillatable xt1 oscillation: oscillatable dsc oscillation: operating (g) (k) (d) (j) (c) (f) (i) (e) (h) (b) (a) cpu: operating with xt1 oscillation cpu: xt1 oscillation halt internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: selectable by cpu xt1 oscillation: operating dsc oscillation: stops internal high-speed oscillation: oscillatable x1 oscillation/exclk input: oscillatable xt1 oscillation: operating dsc oscillation: stops note 2 notes 1. preliminary value and subject to change. 2. after reset release, an operation at one of the fo llowing operating frequencies is started, because f clk = f ih /2 has been selected by setting the system clock control register (ckc) to 09h. ? when 1 mhz has been selected by using the option byte: 500 khz (1 mhz/2) ? when 8 mhz or 20 mhz has been selected by using the option byte: 4 mhz (8 mhz/2) remarks 1. if the low-power-supply detector (lvi) is set to on by default by the option bytes, the reset will not be released until the power supply voltage (v dd ) exceeds 2.07 v 0.2 v note . after the reset operation, the status will shift to (b) in the above figure. 2. dsc: 20 mhz internal high-speed oscillation clock chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 206 table 5-4 shows transition of the cpu clock and examples of setting the sfr registers. table 5-4. cpu clock transition a nd sfr register setting examples (1/6) (1) cpu operating with internal high-speed oscillation clock (b) a fter reset release (a) status transition sfr register setting (a) (b) sfr registers do not have to be se t (default status after reset release). (2) cpu operating with high-speed system clock (c) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) cmc register note 1 csc register osmc register ckc register setting flag of sfr register status transition exclk oscsel amph mstop fsel ostc register mcm0 (a) (b) (c) (x1 clock: 2 mhz f x 10 mhz) 0 1 0 0 0 must be checked 1 (a) (b) (c) (x1 clock: 10 mhz < f x 20 mhz) 0 1 1 0 1 note 2 must be checked 1 (a) (b) (c) (external main clock) 1 1 0/1 0 0/1 must not be checked 1 notes 1. the cmc register can be written only once by an 8- bit memory manipulation instruction after reset release. 2. fsel = 1 when f clk > 10 mhz if a divided clock is selected and f clk 10 mhz, use with fsel = 0 is possible even if f x > 10 mhz. caution set the clock after the s upply voltage has reached the operable voltage of the clock to be set (see chapter 28 electrical specifications (target)). (3) cpu operating with subsystem cl ock (d) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) cmc register note csc register ckc register setting flag of sfr register status transition oscsels xtstop waiting for oscillation stabilization css (a) (b) (d) 1 0 necessary 1 note the cmc register can be written only once by an 8-bit memory manipulation instru ction after reset release. remark (a) to (k) in table 5-4 correspond to (a) to (k) in figure 5-17. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 207 table 5-4. cpu clock transition a nd sfr register setting examples (2/6) (4) cpu operating with 20 mhz internal high-speed oscillation clock (j) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) dscctl register note dscctl register setting flag of sfr register status transition dscon waiting for oscillation stabilization seldsc (a) (b) (j) 1 necessary (100 s) 1 note check that v dd 2.7 v and set dscon = 1. (5) cpu clock changing from inte rnal high-speed oscillation clock (b) to high-speed system clock (c) (setting sequence of sfr registers) cmc register note 1 csc register osmc register ckc register setting flag of sfr register status transition exclk oscsel amph osts register mstop fsel ostc register mcm0 (b) (c) (x1 clock: 2 mhz fx 10 mhz) 0 1 0 note 2 0 0 must be checked 1 (b) (c) (x1 clock: 10 mhz < fx 20 mhz) 0 1 1 note 2 0 1 note 3 must be checked 1 (b) (c) (external main clock) 1 1 0/1 note 2 0 0/1 must not be checked 1 unnecessary if these registers are already set unnecessary if the cpu is operating with the high-speed system clock notes 1. the cmc register can be changed only once after reset release. this setting is not necessary if it has already been set. 2. set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts 3. fsel = 1 when f clk > 10 mhz if a divided clock is selected and f clk 10 mhz, use with fsel = 0 is possible even if f x > 10 mhz. caution set the clock after the s upply voltage has reached the operable voltage of the clock to be set (see chapter 28 electrical specifications (target)). remark (a) to (k) in table 5-4 correspond to (a) to (k) in figure 5-17. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 208 table 5-4. cpu clock transition a nd sfr register setting examples (3/6) (6) cpu clock changing from in ternal high-speed oscillation cl ock (b) to subsystem clock (d) (setting sequence of sfr registers) cmc register note csc register ckc register setting flag of sfr register status transition oscsels xtstop waiting for oscillation stabilization css (b) (d) 1 0 necessary 1 unnecessary if the cpu is operating with the subsystem clock note the cmc register can be written only once by an 8-bit memory manipulation instru ction after reset release. (7) cpu clock changing from inte rnal high-speed oscillation clock (b) to 20 mhz internal high-speed oscillation clock (j) (setting sequence of sfr registers) dscctl register note dscctl register setting flag of sfr register status transition dscon waiting for oscillation stabilization seldsc (b) (j) 1 necessary (100 s) 1 unnecessary if the cpu is operating with the 20 mhz internal high-speed oscillation clock note check that v dd 2.7 v and set dscon = 1. (8) cpu clock changing from high- speed system clock (c) to internal high-speed oscillation clock (b) (setting sequence of sfr registers) csc register ckc register setting flag of sfr register status transition hiostop oscillation accuracy stabilization time mcm0 (c) (b) 0 10 s 0 unnecessary if the cpu is operating with the internal high- speed oscillation clock remark (a) to (k) in table 5-4 correspond to (a) to (k) in figure 5-17. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 209 table 5-4. cpu clock transition a nd sfr register setting examples (4/6) (9) cpu clock changing from high-speed system clock (c) to subsystem clock (d) (setting sequence of sfr registers) cmc register note csc register ckc register setting flag of sfr register status transition oscsels xtstop waiting for oscillation stabilization css (c) (d) 1 0 necessary 1 unnecessary if the cpu is operating with the subsystem clock note the cmc register can be written only once by an 8-bit memory manipulation instru ction after reset release. (10) cpu clock changing from subsystem clock (d) to internal high-speed oscillation clock (b) (setting sequence of sfr registers) csc register ckc register setting flag of sfr register status transition hiostop mcm0 css (d) (b) 0 0 0 unnecessary if the cpu is operating with the internal high-speed oscillation clock unnecessary if this register is already set remark (a) to (k) in table 5-4 correspond to (a) to (k) in figure 5-17. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 210 table 5-4. cpu clock transition a nd sfr register setting examples (5/6) (11) cpu clock changing from subsystem clock (d) to high-sp eed system clock (c) (setting sequence of sfr registers) cmc register note 1 csc register osmc register ckc register setting flag of sfr register status transition exclk oscsel amph osts register mstop fsel ostc register mcm0 css (d) (c) (x1 clock: 2 mhz f x 10 mhz) 0 1 0 note 2 0 0 must be checked 1 0 (d) (c) (x1 clock: 10 mhz < f x 20 mhz) 0 1 1 note 2 0 1 note 3 must be checked 1 0 (d) (c) (external main clock) 1 1 0/1 note 2 0 0/1 must not be checked 1 0 unnecessary if this register is already set unnecessary if the cpu is operating with the high-spe ed system clock unnecessary if these registers are already set notes 1. the cmc register can be changed only once after reset release. this setting is not necessary if it has already been set. 2. set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts 3. fsel = 1 when f clk > 10 mhz if a divided clock is selected and f clk 10 mhz, use with fsel = 0 is possible even if f x > 10 mhz. caution set the clock after the s upply voltage has reached the operable voltage of the clock to be set (see chapter 28 electrical specifications (target)). (12) cpu clock changing from 20 mhz internal high- speed oscillation clock (j) to internal high-speed oscillation clock (b) (setting sequence of sfr registers) csc register ckc register dscctl register setting flag of sfr register status transition hiostop mcm0 seldsc dscon (j) (b) 0 0 0 0 unnecessary if the cpu is operating with the internal high-speed oscillation clock unnecessary if this register is already set remark (a) to (k) in table 5-4 correspond to (a) to (k) in figure 5-17. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 211 table 5-4. cpu clock transition a nd sfr register setting examples (6/6) (13) ? halt mode (e) set while cpu is operating with internal high -speed oscillation clock (b) ? halt mode (f) set while cpu is ope rating with high-speed system clock (c) ? halt mode (g) set while cpu is operating with subsystem clock (d) ? halt mode (k) set while cpu is operating with 20 mhz internal high-speed oscillation clock (j) status transition setting (b) (e) (c) (f) (d) (g) (j) (k) executing halt instruction (14) ? stop mode (h) set while cpu is operating wit h internal high-speed oscillation clock (b) ? stop mode (i) set while cpu is operating with hi gh-speed system clock (c) (setting sequence) status transition setting in x1 stop ? (b) (h) in x1 oscillation (c) (i) stopping peripheral functions that cannot operate in stop mode sets the osts register executing stop instruction remark (a) to (k) in table 5-4 correspond to (a) to (k) in figure 5-17. chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 212 5.6.6 condition before changing cpu clo ck and processing after changing cpu clock condition before changing the cpu clock and processing after changing the cpu clock are shown below. table 5-5. changing cpu clock (1/2) cpu clock before change after change condition before change processing after change x1 clock stabilization of x1 oscillation ? oscsel = 1, exclk = 0, mstop = 0 ? after elapse of oscillation stabilization time external main system clock enabling input of ex ternal clock from exclk pin ? oscsel = 1, exclk = 1, mstop = 0 subsystem clock stabilization of xt1 oscillation ? oscsels = 1, xtstop = 0 ? after elapse of oscillation stabilization time internal high- speed oscillation clock 20 mhz internal high-speed oscillation clock stabilization of dsc oscillation with 20 mhz set by using the option byte ? v dd 2.7 v ? after elapse of oscillation stabilization time (100 s) after setting to dscon = 1 ? seldsc = 1 operating current can be reduced by stopping internal high-speed oscillator (hiostop = 1). internal high- speed oscillation clock oscillation of internal high-speed oscillator ? rstop = 0 x1 oscillation can be stopped (mstop = 1). external main system clock transition not possible (to change the clock, set it again after executing reset once.) ? subsystem clock stabilization of xt1 oscillation ? oscsels = 1, xtstop = 0 ? after elapse of oscillation stabilization time x1 oscillation can be stopped (mstop = 1). x1 clock 20 mhz internal high-speed oscillation clock transition cannot be performed unless the clock is changed to the internal high-speed oscillation clock once. ? internal high- speed oscillation clock oscillation of internal high-speed oscillator ? rstop = 0 external main system clock input can be disabled (mstop = 1). x1 clock transition not possible (to change the clock, set it again after executing reset once.) ? subsystem clock stabilization of xt1 oscillation ? oscsels = 1, xtstop = 0 ? after elapse of oscillation stabilization time external main system clock input can be disabled (mstop = 1). external main system clock 20 mhz internal high-speed oscillation clock transition cannot be performed unless the clock is changed to the internal high-speed oscillation clock once. ? chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 213 table 5-5. changing cpu clock (2/2) cpu clock before change after change condition before change processing after change internal high- speed oscillation clock oscillation of internal high-speed oscillator and selection of internal high-speed oscillation clock as main system clock ? hiostop = 0, mcs = 0 x1 clock stabilization of x1 oscillation and selection of high-speed system cl ock as main system clock ? oscsel = 1, exclk = 0, mstop = 0 ? after elapse of oscillation stabilization time ? mcs = 1 external main system clock enabling input of exter nal clock from exclk pin and selection of hi gh-speed system clock as main system clock ? oscsel = 1, exclk = 1, mstop = 0 ? mcs = 1 xt1 oscillation can be stopped (xtstop = 1) subsystem clock 20 mhz internal high-speed oscillation clock transition cannot be performed unless the clock is changed to the internal high-speed oscillation clock once. ? internal high- speed oscillation clock oscillation of internal high-speed oscillator and selection of internal high-speed oscillation clock as main system clock ? hiostop = 0, mcs = 0 ? seldsc = 0 20 mhz internal high-s peed oscillation clock can be stopped (dscon = 0) x1 clock transition cannot be performed unless the clock is changed to the internal high-speed oscillation clock once. ? external main system clock transition cannot be performed unless the clock is changed to the internal high-speed oscillation clock once. ? 20 mhz internal high-speed oscillation clock subsystem clock transition cannot be performed unless the clock is changed to the internal high-speed oscillation clock once. ? chapter 5 clock generator preliminary user?s manual u19291ej1v0ud 214 5.6.7 time required for switchover of cpu clock and main system clock by setting bits 0 to 2, 4, and 6 (mdiv0 to mdiv2, mcm0, c ss) of the system clock contro l register (ckc), the cpu clock can be switched (between the main system clock and the subsystem clock) , main system clock can be switched (between the internal high-speed oscillation clock and the hi gh-speed system clock), and the division ratio of the main system clock can be changed. the actual switchover operation is not performed immediat ely after rewriting to ckc; operation continues on the pre-switchover clock for several cl ocks (see table 5-6 to table 5-9). whether the cpu is oper ating on the main system clock or the sub system clock can be ascertained using bit 7 (cls) of ckc. whether the main syst em clock is operating on the high-spee d system clock or internal high-speed oscillation clock can be ascertained using bit 5 (mcs) of ckc. when the cpu clock is switched, the perip heral hardware clock is also switched. table 5-6. maximum time required for main system clock switchover clock a switching directions clock b remark f main (changing the division ratio) f main see table 5-7 f ih f mx see table 5-8 f main f sub see table 5-9 table 5-7. maximum number of clocks required for f main ? f main (changing the division ratio) set value after switchover set value before switchover clock a clock b clock a 1 + f a /f b clock clock b 1 + f b /f a clock table 5-8. maximum number of clocks required for f ih ? f mx set value before switchover set value after switchover mcm0 mcm0 0 (f main = f ih ) 1 (f main = f mx ) f mx >f ih 1 + f mx /f ih clock 0 (f main = f ih ) f mx preliminary user?s manual u19291ej1v0ud 216 chapter 6 timer array unit taus timer array unit taus has eight 16-bit timers per unit. each 16-bit timer is called a channel and can be used as an independent timer. in addition, two or more ?channels? can be used to create a high-accuracy timer. single-operation function comb ination-operation function ? interval timer ? square wave output ? external event counter ? divider function (channel 0 of 78k0r/kd3-l and 78k0r/ke3-l only) ? input pulse interval measurement ? measurement of high-/low-l evel width of input signal ? pwm output ? one-shot pulse output ? multiple pwm output channel 7 can be used to realize lin-bus reception proces sing in combination with uart0 of the serial array unit. the presence or absence of timer i/o pins in eac h timer array unit channel depends on the product. i/o pins of each product timer array unit channels kc3-l (44-pin) kc3-l (48-pin) kd3-l ke3-l channel 0 ? ? p00/ti00, p01/to00 channel 1 ? ? ? ? channel 2 p10/ti02/to02 channel 3 p11/ti03/to03 channel 4 p12/ti04/to04 channel 5 p13/ti05/to05 channel 6 p50/ti06/to06 p14/ti06/to06 channel 7 p51/ti07/to07 p15/ti07/to07 remark the p52/slti/slto pin can be assi gned to the timer i/os of channels 0 and 1 by setting the input switch control register (isc). see ?? timer i/o pin configuration? in 6.2 configuration of timer array unit taus . chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 217 6.1 functions of timer array unit taus timer array unit taus has the following functions. 6.1.1 functions of each channel when it operates independently single-operation functions are those f unctions that can be used for any channel regardless of the operation mode of the other channel (for details, refer to 6.6.1 overview of single-operation function and combination-operation function ). (1) interval timer each timer of a unit can be used as a reference timer t hat generates an interrupt (in ttm0n) at fixed intervals. (2) square wave output a toggle operation is performed each time inttm0n is ge nerated and a square wave with a duty factor of 50% is output from a timer out put pin (to0n, slto). (3) external event counter each timer of a unit can be used as an event counter t hat generates an interrupt when the number of the valid edges of a signal input to the timer input pi n (ti0n, slti) has reached a specific value. (4) divider function (channel 0 only) note a clock input from a timer input pin (ti00) is divided and output from an output pin (to00). (5) input pulse inte rval measurement counting is started by the valid edge of a pulse signal input to a timer input pin (ti0n, slti). the count value of the timer is captured at the valid edge of the next pulse. in this way, the interval of the input pulse can be measured. (6) measurement of high-/low-l evel width of input signal counting is started by a single edge of the signal input to the timer input pi n (ti0n, slti), and the count value is captured at the other edge. in this way, the high-level or low-level widt h of the input signal can be measured. note 78k0r/kd3-l and 78k0r/ke3-l only remark n: channel number (n = 0 to 7) chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 218 6.1.2 functions of each channel when it operates with another channel combination-operation functions are th ose functions that are attained by us ing the master channel (mostly the reference timer that controls cycles) and the slave channel s (timers that operate follo wing the master channel) in combination (for details, refer to 6.6.1 overview of singl e-operation function and combination-operation function ). (1) pwm (pulse width modulation) output two channels are used as a set to generate a pulse with a specified period and a specified duty factor. (2) one-shot pulse output two channels are used as a set to generate a one-shot pulse with a specified delay time and a specified pulse width. (3) multiple pwm (pulse width modulation) output by extending the pwm function and using one master ch annel and two or more slave channels, up to seven types of pwm signals that have a specific pe riod and a specified duty fa ctor can be generated. 6.1.3 lin-bus supporting function (channel 7 only) (1) detection of wakeup signal the timer starts counting at the falli ng edge of a signal input to the serial data input pin (rxd0) of uart0 and the count value of the timer is captur ed at the rising edge. in this way, a low-level width can be measured. if the low-level width is greater than a specific value, it is recognized as a wakeup signal. (2) detection of sync break field the timer starts counting at the falling edge of a signal in put to the serial data input pin (rxd0) of uart0 after a wakeup signal is detected, and the count value of the timer is captured at t he rising edge. in this way, a low- level width is measured. if the low-level width is greater than a specific value, it is recognized as a sync break field. (3) measurement of pulse width of sync field after a sync break field is detected, the low-level width and high-level width of the signal input to the serial data input pin (rxd0) of uart0 are measured. from the bit interval of the sync field measured in this way, a baud rate is calculated. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 219 6.2 configuration of timer array unit taus timer array unit taus includes the following hardware. table 6-1. configuration of timer array unit taus item configuration timer/counter timer count er register 0n (tcr0n) register timer data register 0n (tdr0n) timer input ti00 to ti07, slti pins, rxd0 pin (for lin-bus) timer output to00 to to07, slto pins, output controller chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 220 ? timer i/o pin configuration the p52/slti/slto pin can be assigned to the timer i/os of channels 0 and 1 by setting the input switch control register (isc). (for deta ils of the input switch c ontrol register (isc), see 6.3 (13) input switch control register (isc) .) the following i/o pins can be sele cted for channels 0 and 1. table 6-2. i/o pins that can be selected for channels 0 and 1 channel for which i/o pin can be selected input pin output pin channel 0 ? p00/ti00 pin note ? p52/slti/slto pin ? p01/to00 pin note ? p52/slti/slto pin channel 1 p52/slti/slto pin p52/slti/slto pin note 78k0r/kd3-l and 78k0r/ke3-l only. only the p52/slti/s lto pin can be assigned to channels 0 and 1 in the 78k0r/kc3-l. caution hereinafter, timer i/o pins ar e described as tin and ton (n = xx), which also includes the selection of the slti and slto pins. remarks 1. when timer input and timer output are shared by the same pin, either only timer input or only timer output can be used. 2. only one of the above-mentioned channels can be assi gned as the timer i/o pin for the p52/slti/slto pin. 3. the slti and slto pins cannot be selected as timer i/os for channels other than those mentioned above (channels 2 to 7). figure 6-1 shows the block diagram. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 221 figure 6-1. block diagram of timer array unit timer clock select register 0 (tps0) 4 4 f clk f clk /2 0 to f clk /2 15 selector f clk /2 0 to f clk /2 15 selector timer output register 0 (to0) to07 to03 to06 to05 to04 to02 to01 to00 timer output enable register 0 (toe0) tau0en peripheral enable register 2 (per2) timer channel enable status register 0 (te0) timer channel stop register 0 (tt0) timer channel start register 0 (ts0) prescaler te07 te03 te06 te05 te04 te02 te01 te00 toe07 toe03 toe06 toe05 toe04 toe02 toe01 toe00 ts07 ts03 ts06 ts05 ts04 ts02 ts01 ts00 tt07 tt03 tt06 tt05 tt04 tt02 tt01 tt00 tol07 tol03 tol06 tol05 tol04 tol02 tol01 tol00 tom07 tom03 tom06 tom05 tom04 tom02 tom01 tom00 timer output level register 0 (tol0) timer output mode register 0 (tom0) channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 (lin-bus supported) rxd0 ti02 ti03 ti04 ti05 ti06 to02 to03 to04 to05 to06 inttm02 inttm03 inttm04 inttm05 inttm06 inttm07 isc1 noise filter enable register 1 (nfen1) ti07 (serial input pin) timer input select register 0 (tis0) tnfen 07 tnfen 06 tnfen 05 tnfen 04 tnfen 03 tnfen 02 0 tnfen 00 note noise filter enable register 2 (nfen2) 0 00 tnfen sl 0 0 0 0 tis07 tis03 tis06 tis05 tis04 tis02 tis01 tis00 to07 prs013 prs003 prs012 prs011 prs010 prs002 prs001 prs000 to00 note inttm00 pm52 cks01 ccs01 mas ter01 sts012 sts011 sts010 md012 cis011 cis010 md013 md011 md010 ovf 01 ck00 ck01 mck tclk f xt /4 tis01 interrupt controller output controller output latch (p52) inttm01 (timer interrupt) timer status register 01 (tsr01) overflow timer data register 01 (tdr01) timer counter register 01 (tcr01) timer mode register 01 (tmr01) channel 0 channel 1 timer controller trigger selection count clock selection mode selection slave/master controller slave/master controller edge detection selector operating clock selection ti00 note trigger signal to slave channel clock signal to slave channel interrupt signal to slave channel selector slto (timer output pin) isc2 of isc register selector slti (timer input pin) isc2 selector input switch control register (isc) note 78k0r/kd3-l and 78k0r/ke3-l only chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 222 (1) timer/counter register 0n (tcr0n) tcr0n is a 16-bit read-only register and is used to count clocks. the value of this counter is incr emented or decremented in synchronization with the rising edge of a count clock. whether the counter is incr emented or decremented depends on the oper ation mode that is selected by the md0n3 to md0n0 bits of tmr0n. figure 6-2. format of timer/counter register 0n (tcr0n) address: f0180h, f0181h (tcr00) to f018eh, f018fh (tcr07) after reset: ffffh r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tcr0n (n = 0 to 7) the count value can be read by reading tcr0n. the count value is set to ffffh in the following cases. ? when the reset signal is generated ? when the tau0en bit of peripheral enable register 2 (per2) is cleared ? when counting of the slave channel has been completed in the pwm output mode ? when counting of the master/slave channel has been completed in the one-shot pulse output mode ? when counting of the slave channel has been completed in the multiple pwm output mode the count value is cleared to 0000h in the following cases. ? when the start trigger is input in the capture mode ? when capturing has been completed in the capture mode caution the count value is not captured to tdr0n even when tcr0n is read. f0181h (tcr00) f0180h (tcr00) chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 223 the tcr0n register read value differs as follows according to operation mode changes and the operating status. table 6-3. tcr0n register read value in various operation modes tcr0n register read value note operation mode count mode operation mode change after reset operation mode change after count operation paused (tt0n = 1) operation restart after count operation paused (tt0n = 1) during start trigger wait status after one count interval timer mode count down ffffh undefined stop value ? capture mode count up 0000h undefined stop value ? event counter mode count down ffffh undefined stop value ? one-count mode count down ffffh undefined stop value ffffh capture & one- count mode count up 0000h undefined stop value capture value of tdr0n register + 1 note the read values of the tcr0n re gister when ts0n has been set to "1" while te0n = 0 are shown. the read value is held in the tcr0n register until the count operation starts. remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 224 (2) timer data register 0n (tdr0n) this is a 16-bit register from which a capture function and a compare function can be selected. the capture or compare function can be switched by selecting an operation mode by using the md0n3 to md0n0 bits of tmr0n. the value of tdr0n can be changed at any time. this register can be read or written in 16-bit units. reset signal generation clears this register to 0000h. figure 6-3. format of timer data register 0n (tdr0n) address: fff18h, fff19h (tdr00), fff1ah, fff1bh (tdr01), after reset: 0000h r/w fff64h, fff65h (tdr02) to fff6eh, fff6fh (tdr07) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tdr0n (n = 0 to 7) (i) when tdr0n is used as compare register counting down is started from the value set to tdr0n. when the count value reaches 0000h, an interrupt signal (inttm0n) is generated. tdr0n ho lds its value until it is rewritten. caution tdr0n does not perform a capture operation even if a capture trigger is input, when it is set to the compare function. (ii) when tdr0n is u sed as capture register the count value of tcr0n is captured to tdr0n when the capture trigger is input. a valid edge of the ti0n pin can be selected as the capt ure trigger. this selection is made by tmr0n. remark n = 0 to 7 fff19h (tdr00) fff18h (tdr00) chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 225 6.3 registers controlling timer array unit timer array unit is controlled by the following registers. ? peripheral enable register 2 (per2) ? timer clock select register 0 (tps0) ? timer mode register 0n (tmr0n) ? timer status register 0n (tsr0n) ? timer channel enable status register 0 (te0) ? timer channel start register 0 (ts0) ? timer channel stop register 0 (tt0) ? timer input select register 0 (tis0) ? timer output enable register 0 (toe0) ? timer output register 0 (to0) ? timer output level register 0 (tol0) ? timer output mode register 0 (tom0) ? input switch control register (isc) ? noise filter enable registers 1, 2 (nfen1, nfen2) ? port mode registers 0, 1, 5 (pm0, pm1, pm5) ? port registers 0, 1, 5 (p0, p1, p5) remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 226 (1) peripheral enable register 2 (per2) per2 is used to enable or disable use of each peripheral hardware macro. clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. when timer array unit taus is used, be sure to set bit 0 (tau0en) of this register to 1. per2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. cautions 1. when setting timer array unit taus, be sure to set tau0en to 1 first. if tau0en = 0, writing to a control register of timer array unit taus is ignored, and all read values are default values. 2. be sure to clear bit 1 to 7 of the per2 register to 0. figure 6-4. format of peripheral enable register 2 (per2) address: f00f2h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> per2 0 0 0 0 0 0 0 tau0en tau0en control of timer a rray unit input clock supply 0 stops supply of input clock. ? sfr used by timer array unit taus cannot be written. ? timer array unit taus is in the reset status. 1 supplies input clock. ? sfr used by timer array unit taus can be read/written. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 227 (2) timer clock select register 0 (tps0) tps0 is a 16-bit register that is used to select two ty pes of operation clocks (ck00, ck01) that are commonly supplied to each channel. ck01 is selected by bits 7 to 4 of tps0, and ck00 is selected by bits 3 to 0. rewriting of tps0 during timer operation is possible only in the following cases. rewriting of prs000 to prs003 bits: possible only when all the channels set to cks0n = 0 are in the operation stopped state (te0n = 0) rewriting of prs010 to prs013 bits: possible only when all the channels set to cks0n = 1 are in the operation stopped state (te0n = 0) tps0 can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 6-5. format of timer cl ock select register 0 (tps0) address: f01b6h, f01b7h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tps0 0 0 0 0 0 0 0 0 prs 013 prs 012 prs 011 prs 010 prs 003 prs 002 prs 001 prs 000 selection of operation clock (ck0m) note prs 0m3 prs 0m2 prs 0m1 prs 0m0 f clk = 2 mhz f clk = 5 mhz f clk = 10 mhz f clk = 20 mhz 0 0 0 0 f clk 2 mhz 5 mhz 10 mhz 20 mhz 0 0 0 1 f clk /2 1 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 0 f clk /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 0 0 1 1 f clk /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 0 1 0 0 f clk /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 0 1 0 1 f clk /2 5 62.5 khz 156.2 khz 312.5 khz 625 khz 0 1 1 0 f clk /2 6 31.25 khz 78.1 khz 156.2 khz 312.5 khz 0 1 1 1 f clk /2 7 15.62 khz 39.1 khz 78.1 khz 156.2 khz 1 0 0 0 f clk /2 8 7.81 khz 19.5 khz 39.1 khz 78.1 khz 1 0 0 1 f clk /2 9 3.91 khz 9.76 khz 19.5 khz 39.1 khz 1 0 1 0 f clk /2 10 1.95 khz 4.88 khz 9.76 khz 19.5 khz 1 0 1 1 f clk /2 11 976 hz 2.44 khz 4.88 khz 9.76 khz 1 1 0 0 f clk /2 12 488 hz 1.22 khz 2.44 khz 4.88 khz 1 1 0 1 f clk /2 13 244 hz 610 hz 1.22 khz 2.44 khz 1 1 1 0 f clk /2 14 122 hz 305 hz 610 hz 1.22 khz 1 1 1 1 f clk /2 15 61 hz 153 hz 305 hz 610 hz note when changing the clock selected for f clk (by changing the system clock control register (ckc) value), stop timer array unit taus (tt0 = 00ffh). caution be sure to clear bits 15 to 8 to ?0?. remarks 1. f clk : cpu/peripheral hardware clock frequency 2. m = 0, 1 n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 228 (3) timer mode register 0n (tmr0n) tmr0n sets an operation mode of channel n. it is us ed to select an operation clock (mck), a count clock, whether the timer operates as the master or a slave, a st art trigger and a capture trigger, the valid edge of the timer input, and an operation mode (interval, captur e, event counter, one-count, or capture & one-count). rewriting tmr0n is prohibited when the register is in operation (when te0 = 1). however, bits 7 and 6 (cis0n1, cis0n0) can be rewritten even while the register is operating with some functions (when te0 = 1) (for details, see 6.7 operation of timer array un it taus as independent channel and 6.8 operation of plural channels of timer array unit taus ). tmr0n can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 6-6. format of timer m ode register 0n (tmr0n) (1/3) address: f0190h, f0191h (tmr00) to f019eh, f019fh (tmr07) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks 0n 0 0 ccs 0n mast er0n sts 0n2 sts 0n1 sts 0n0 cis 0n1 cis 0n0 0 0 md 0n3 md 0n2 md 0n1 md 0n0 cks 0n selection of operation cl ock (mck) of channel n 0 operation clock ck00 se t by tps0 register 1 operation clock ck01 se t by tps0 register operation clock mck is used by the edge detector. a count clock (tclk) and a sampling clock are generated depending on the setting of the ccs0n bit. ccs 0n selection of count clock (tclk) of channel n 0 operation clock mck specified by cks0n bit 1 valid edge of input signal input from ti0n pin count clock tclk is used for the timer/counter, output controller, and interrupt controller. mas ter 0n selection of operation in single-oper ation function or as slave channe l in combination-operation function /operation as master channel in comb ination-operation function of channel n 0 operates in single-operation f unction or as slave channel in combination-operation function. 1 operates as master channel in combination-operation function. only the even channel can be set as a master channel (master0n = 1). be sure to use the odd channel as a slave channel (master0n = 0). clear master0n to 0 for a channel that is used with the single-operation function. caution be sure to clear bits 14, 13, 5, and 4 to ?0?. remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 229 figure 6-6. format of timer m ode register 0n (tmr0n) (2/3) address: f0190h, f0191h (tmr00) to f019eh, f019fh (tmr07) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks 0n 0 0 ccs 0n mast er0n sts 0n2 sts 0n1 sts 0n0 cis 0n1 cis 0n0 0 0 md 0n3 md 0n2 md 0n1 md 0n0 sts 0n2 sts 0n1 sts 0n0 setting of start trigger or capture trigger of channel n 0 0 0 only software trigger start is valid (other trigger sources are unselected). 0 0 1 valid edge of ti0n pin input is used as both the start trigger and capture trigger. 0 1 0 both the edges of ti0n pin input are us ed as a start trigger and a capture trigger. 1 0 0 interrupt signal of the master channel is us ed (when the channel is used as a slave channel with the combination-operation function). other than above setting prohibited cis 0n1 cis 0n0 selection of ti0n pin input valid edge 0 0 falling edge 0 1 rising edge 1 0 both edges (when low-level width is measured) start trigger: falling edge, capture trigger: rising edge 1 1 both edges (when high-level width is measured) start trigger: rising edge, capture trigger: falling edge if both the edges are specified when the value of the sts 0n2 to sts0n0 bits is other than 010b, set the cis0n1 to cis0n0 bits to 10b. remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 230 figure 6-6. format of timer m ode register 0n (tmr0n) (3/3) address: f0190h, f0191h (tmr00) to f019eh, f019fh (tmr07) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks 0n 0 0 ccs 0n mast er0n sts 0n2 sts 0n1 sts 0n0 cis 0n1 cis 0n0 0 0 md 0n3 md 0n2 md 0n1 md 0n0 md 0n3 md 0n2 md 0n1 md 0n0 operation mode of channel n count operation of tcr independent operation 0 0 0 1/0 interval timer mode counting down possible 0 1 0 1/0 capture mode counting up possible 0 1 1 0 event counter mode counting down possible 1 0 0 1/0 one-count mode counting down impossible 1 1 0 0 capture & one-count mode counting up possible other than above setting prohibited the operation of md0n0 bits varies depending on each operation mode (see table below). operation mode (value set by the md0n3 to md0n1 bits (see table above)) md 0n0 setting of starting counting and interrupt 0 timer interrupt is not generated when counting is started (timer output does not change, either). ? interval timer mode (0, 0, 0) ? capture mode (0, 1, 0) 1 timer interrupt is generated when counting is started (timer output also changes). ? event counter mode (0, 1, 1) 0 timer interrupt is not generated when counting is started (timer output does not change, either). 0 start trigger is invalid during counting operation. at that time, interrupt is not generated, either. ? one-count mode note 1 (1, 0, 0) 1 start trigger is valid during counting operation note 2 . at that time, interrupt is also generated. ? capture & one-count mode (1, 1, 0) 0 timer interrupt is not generated when counting is started (timer output does not change, either). start trigger is invalid during counting operation. at that time interrupt is not generated, either. other than above setting prohibited notes 1. in one-count mode, interrupt output (inttm0n) wh en starting a count operation and ton output are not controlled. 2. if the start trigger (ts0n = 1) is issued during op eration, the counter is cleared, an interrupt is generated, and recounting is started. remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 231 (4) timer status register 0n (tsr0n) tsr0n indicates the overflow status of the counter of channel n. tsr0n is valid only in the capture mode (md0n3 to md0n1 = 010b) and capture & one-count mode (md0n3 to md0n1 = 110b). it will not be set in any other mode. see table 6-4 for the operation of the ovf bit in each operation mode and set/clear conditions. tsr0n can be read by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 6-7. format of timer status register 0n (tsr0n) address: f01a0h, f01a1h (tsr00) to f01aeh, f01afh (tsr07) after reset: 0000h r symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tsr0n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ovf ovf counter overflow status of channel n 0 overflow does not occur. 1 overflow occurs. when ovf = 1, this flag is cleared (ovf = 0) when the next value is captured without overflow. table 6-4. ovf bit operation and set/cl ear conditions in each operation mode timer operation mode ovf set/clear conditions clear when no overflow has occurred upon capturing ? capture mode ? capture & one-count mode set when an overflow has occurred upon capturing clear ? interval timer mode ? event counter mode ? one-count mode set ? (use prohibited, not set and not cleared) remark the ovf bit does not change immediately after the counter has overflowed, but changes upon the subsequent capture. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 232 (5) timer channel enable status register 0 (te0) te0 is used to enable or stop the timer operation of each channel. when a bit of timer channel start register 0 (ts0) is set to 1, the corresponding bit of this register is set to 1. when a bit of timer channel stop register 0 (tt0) is set to 1, the corresponding bit of this register is cleared to 0. te0 can be read by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 6-8. format of timer channe l enable status register 0 (te0) address: f01b0h, f01b1h after reset: 0000h r symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 te0 0 0 0 0 0 0 0 0 te07 te06 te05 te04 te03 te02 te01 te00 te0n indication of operation enable/stop status of channel n 0 operation is stopped. 1 operation is enabled. remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 233 (6) timer channel start register 0 (ts0) ts0 is a trigger register that is used to clear a time r counter (tcr0n) and start t he counting operation of each channel. when a bit (ts0n) of this register is set to 1, the co rresponding bit (te0n) of timer channel enable status register 0 (te0) is set to 1. ts0n is a trigger bit and cleared immediately when te0n = 1. ts0 can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 6-9. format of timer channel start register 0 (ts0) address: f01b2h, f01b3h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ts0 0 0 0 0 0 0 0 0 ts07 ts06 ts05 ts04 ts03 ts02 ts01 ts00 ts0n operation enable (start ) trigger of channel n 0 no trigger operation 1 te0n is set to 1 and the count operation becomes enabled. the tcr0n count operation start in the count ope ration enabled state varies depending on each operation mode (see table 6-5). caution be sure to clear bits 15 to 8 to ?0?. remarks 1. when the ts0 register is read, 0 is always read. 2. n = 0 to 7 table 6-5. operations from count operati on enabled state to tcr0n count start (1/2) timer operation mode operat ion when ts0n = 1 is set ? interval timer mode no operation is carried out from start tri gger detection (ts0n=1) until count clock generation. the first count clock loads the value of tdr0n to tcr0n and the subsequent count clock performs count down operation (see 6.3 (6) (a) start timing in interval timer mode ). ? event counter mode writing 1 to ts0n bit loads the value of tdr0n to tcr0n. the subsequent count clock performs count down operation. the external trigger detection selected by sts0n2 to sts0n0 bits in the tmr0n register does not start count operation (see 6.3 (6) (b) start timing in event counter mode ). ? capture mode no operation is carried out from star t trigger detection until count clock generation. the first count clock loads 0000h to tcr0n and the subsequent count clock performs count up operation (see 6.3 (6) (c) start timing in capture mode ). chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 234 table 6-5. operations from count operati on enabled state to tcr0n count start (2/2) timer operation mode operat ion when ts0n = 1 is set ? one-count mode when ts0n = 0, writing 1 to ts0n bit sets the start trigger wait state. no operation is carried out from star t trigger detection until count clock generation. the first count clock loads the value of tdr0n to tcr0n and the subsequent count clock performs count down operation (see 6.3 (6) (d) start timing in one- count mode ). ? capture & one-count mode when ts0n = 0, writing 1 to ts0n bit sets the start trigger wait state. no operation is carried out from star t trigger detection until count clock generation. the first count clock loads 0000h to tcr0n and the subsequent count clock performs count up operation (see 6.3 (6) (e) start timing in capture & one- count mode ). (a) start timing in interval timer mode <1> writing 1 to ts0n sets te0n = 1 <2> the write data to ts0n is held until count clock generation. <3> tcr0n holds the initial val ue until count clock generation. <4> on generation of count clock, the ?tdr0n va lue? is loaded to tcr0n and count starts. figure 6-10. start timing (in interval timer mode) ts0n (write) te0n count clock f clk tcr0n initial value tdr0n value when md0n0 = 1 is set <1> <2> <3> <4> start trigger detection signal ts0n (write) hold signal inttm0n caution in the first cycle operation of count clock after writing ts0n, an error at a maximum of one clock is generated since count start delays until count clock has been generated. when the information on count start timing is necessary, an interrupt can be generated at count start by setting md0n0 = 1. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 235 (b) start timing in event counter mode <1> while te0n is set to 0, tcr0n holds the initial value. <2> writing 1 to ts0n sets 1 to te0n. <3> as soon as 1 has been written to ts0n and 1 has been set to te0n, the "tdr0n value" is loaded to tcr0n to start counting. <4> after that, the tcr0n value is count ed down according to the count clock. figure 6-11. start timing (in event counter mode) te0n f clk tcr0n tdr0n value <1> <1> <2> <3> tdr0n value-1 initial value ts0n (write) count clock start trigger detection signal ts0n (write) hold signal (c) start timing in capture mode <1> writing 1 to ts0n sets te0n = 1 <2> the write data to ts0n is held until count clock generation. <3> tcr0n holds the initial val ue until count clock generation. <4> on generation of count clock, 0000h is loaded to tcr0n and count starts. figure 6-12. start timing (in capture mode) te0n f clk tcr0n inttm0n 0000h <1> <2> <3> <4> initial value when md0n0 = 1 is set ts0n (write) count clock start trigger detection signal ts0n (write) hold signal caution in the first cycle operation of count clock after writing ts0n, an error at a maximum of one clock is generated since count start delays until count clock has been generated. when the information on count start timing is necessary, an interrupt can be generated at count start by setting md0n0 = 1. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 236 (d) start timing in one-count mode <1> writing 1 to ts0n sets te0n = 1 <2> enters the start trigger input wait status, and tcr0n holds the initial value. <3> on start trigger detection , the ?tdr0n value? is loaded to tcr0n and count starts. figure 6-13. start timing (in one-count mode) te0n f clk tcr0n start trigger input wait status tdr0n value initial value <1> <2> <3> ts0n (write) count clock note start trigger detection signal ts0n (write) hold signal tin edge detection signal note when the one-count mode is set, the operation cloc k (mck) is selected as count clock (ccs0n = 0). caution an input signal sampling error is gene rated since operation starts upon start trigger detection (the error is one count clock when ti0n is used). chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 237 (e) start timing in capture & one-count mode <1> writing 1 to ts0n sets te0n = 1 <2> enters the start trigger input wait status, and tcr0n holds the initial value. <3> on start trigger detection , 0000h is loaded to tcr0n and count starts. figure 6-14. start timing (in capture & one-count mode) te0n f clk tcr0n 0000h ts0n (write) count clock note start trigger detection signal ts0n (write) hold signal tin edge detection signal start trigger input wait status initial value <2> <3> <1> note when the capture & one-count mode is set, the operat ion clock (mck) is selected as count clock (ccs0n = 0). caution an input signal sampling error is gene rated since operation starts upon start trigger detection (the error is one count clock when ti0n is used). chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 238 (7) timer channel stop register 0 (tt0) tt0 is a trigger register that is used to clear a ti mer counter (tcr0n) and start the counting operation of each channel. when a bit (tt0n) of this register is set to 1, the corresponding bit (te 0n) of timer channel enable status register 0 (te0) is cleared to 0. tt0n is a tri gger bit and cleared to 0 immediately when te0n = 0. tt0 can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 6-15. format of timer channel stop register 0 (tt0) address: f01b4h, f01b5h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tt0 0 0 0 0 0 0 0 0 tt07 tt06 tt05 tt04 tt03 tt02 tt01 tt00 tt0n operation stop trigger of channel n 0 no trigger operation 1 operation is stopped (s top trigger is generated). caution be sure to clear bits 15 to 8 to ?0?. remarks 1. when the tt0 register is read, 0 is always read. 2. n = 0 to 7 (8) timer input select register 0 (tis0) tis0 is used to select whether a signal input to the time r input pin (ti0n) or the subsystem clock divided by four (f xt /4) is valid for each channel. tis0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 6-16. format of timer input select register 0 (tis0) address: fff3eh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tis0 tis07 tis06 tis05 tis04 tis03 tis02 tis01 tis00 tis0n selection of timer input/sub system clock used with channel n 0 input signal of timer input pin (ti0n) 1 subsystem clock divided by 4 (f xt /4) chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 239 (9) timer output enable register 0 (toe0) toe0 is used to enable or disable timer output of each channel. channel n for which timer output has been enabled become s unable to rewrite the value of the to0n bit of the timer output register (to0) described later by software, and the value reflecting the setting of the timer output function through the count operation is out put from the timer output pin (to0n). toe0 can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 6-17. format of timer out put enable register 0 (toe0) address: f01bah, f01bbh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 toe0 0 0 0 0 0 0 0 0 toe 07 toe 06 toe 05 toe 04 toe 03 toe 02 toe 01 toe 00 toe 0n timer output enable/disable of channel n 0 the to0n operation stopped by count operation (timer channel output bit). writing to the to0n bit is enabled. the to0n pin functions as data output, and it outputs the level set to the to0n bit. the output level of the to0n pin can be manipulated by software. 1 the to0n operation enabled by count oper ation (timer channel output bit). writing to the to0n bit is di sabled (writing is ignored). the to0n pin functions as timer output, and the toe0n is set or reset depending on the timer operation. the to0n pin outputs the square-wave or pwm depending on the timer operation. caution be sure to clear bits 15 to 8 to ?0?. remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 240 (10) timer output register 0 (to0) to0 is a buffer register of timer output of each channel. the value of each bit in this register is output from the timer output pin (to0n) of each channel. this register can be rewritten by software only when ti mer output is disabled (toe0n = 0). when timer output is enabled (toe0n = 1), rewriting this register by softw are is ignored, and the value is changed only by the timer operation. to use the p01/to00, p10/to02, p11/ to03, p12/to04, p1 3/to05, p14/to06 note , p15/to07 note , or p52/slto pin as a port function pin, set the corresponding to0n bit to ?0?. to0 can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. note to06 and to07 are shared with p50 and p51 (p50/to 06, p51/to07), respectively, in products other than the 78k0r/ke3-l. figure 6-18. format of timer output register 0 (to0) address: f01b8h, f01b9h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 to0 0 0 0 0 0 0 0 0 to0 7 to0 6 to0 5 to0 4 to0 3 to0 2 to0 1 to0 0 to0 n timer output of channel n 0 timer output value is ?0?. 1 timer output value is ?1?. caution be sure to clear bits 15 to 8 to ?0?. remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 241 (11) timer output level register 0 (tol0) tol0 is a register that controls t he timer output level of each channel. the setting of the inverted output of channel n by this register is reflec ted at the timing of set or reset of the timer output signal while the timer output is enabled (t oe0n = 1) in the combination-operation mode (tom0n = 1). in the toggle mode (tom0n = 0), this register setting is invalid. tol0 can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 6-19. format of timer ou tput level register 0 (tol0) address: f01bch, f01bdh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tol0 0 0 0 0 0 0 0 0 tol 07 tol 06 tol 05 tol 04 tol 03 tol 02 tol 01 tol 00 tol 0n control of timer output level of channel n 0 positive logic out put (active-high) 1 inverted output (active-low) caution be sure to clear bits 15 to 8 to ?0?. remarks 1. if the value of this register is rewritten duri ng timer operation, the timer output is inverted when the timer output signal changes next, instead of imm ediately after the register value is rewritten. 2. n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 242 (12) timer output mode register 0 (tom0) tom0 is used to control the timer output mode of each channel. when a channel is used for the single- operation function, set the corres ponding bit of the channel to be used to 0. when a channel is used for the combination-operatio n function (pwm output, one-shot pulse output, or multiple pwm output), set the corresponding bit of the master channel to 0 and the corresponding bit of the slave channel to 1. the setting of each channel n by this register is reflec ted at the timing when the timer output signal is set or reset while the timer output is enabled (toe0n = 1). tom0 can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 6-20. format of timer ou tput mode register 0 (tom0) address: f01beh, f01bfh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tom0 0 0 0 0 0 0 0 0 tom 07 tom 06 tom 05 tom 04 tom 03 tom 02 tom 01 tom 00 tom 0n control of timer output mode of channel n 0 toggle operation mode (to produce toggle output by timer interrupt request signal (inttm0n)) 1 combination-operation mode (output is set by the time r interrupt request signal (inttm0n) of the master channel, and reset by the timer interrupt reque st signal (inttm0m) of the slave channel) caution be sure to clear bits 15 to 8 to ?0?. remark n: channel number, m: slave channel number n = 0 to 7 (n = 0, 2, 4, 6 for master channel) n < m 7 (where m is a consecutive integer greater than n) chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 243 (13) input switch control register (isc) the isc1 and isc0 bits of the isc register are used to im plement lin-bus communication operation by using channel 7 in association with the serial array unit. when t he isc1 bit is set to 1, the input signal of the serial data input pin (rxd0) is selected as a timer input signal. the isc2 bit is set when selecting the p52/slti/slto pin as the timer i/o pin of timer channels 0 and 1. isc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 6-21. format of input switch control register (isc) address: fff3ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 0 0 0 isc2 isc1 isc0 selecting p52/slti/slto pin as timer i/o pin channel 0 channel 1 isc2 input pin output pin input pin output pin 0 p00/ti00 note p01/to00 note p52/slti p52/slto 1 p52/slti p52/slto ? ? other than above setting prohibited isc1 switching channel 7 input of timer array unit taus 0 uses the input signal of the ti07 pin as a timer input (normal operation). 1 input signal of r x d0 pin is used as timer input (wakeup signal detection). isc0 switching external interrupt (intp0) input 0 uses the input signal of the intp0 pin as an external interrupt (normal operation). 1 uses the input signal of the r x d0 pin as an external interrupt (to measure the pulse widths of t he sync break field and sync field). note 78k0r/kd3-l and 78kr/ke3-l only. only the p52/sl ti/slto pin can be assigned to channels 0 and 1 in the 78k0r/kc3-l. caution be sure to clear bits 7 to 3 to ?0?. remark when the lin-bus communication func tion is used, select the input signal of the rxd0 pin by setting isc1 to 1. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 244 (14) noise filter enable re gisters 1, 2 (nfen1, nfen2) nfen1 and nfen2 are used to set whether the noise filt er can be used for the timer input signal to each channel. enable the noise filter by setting the corresponding bi ts to 1 on the pins in need of noise removal. when the noise filter is on, matc h detection and synchronization of the 2 clocks is performed with the cpu/peripheral hardware clock (f clk ). when the noise filter is off, only synchronization is performed with the cpu/peripheral hardware clock (f clk ). nfen1 and nfen2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 245 figure 6-22. format of noise filter en able registers 1, 2 (nfen1, nfen2) address: f0061h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 nfen1 tnfen07 tnfen06 tnfen05 tnfen04 tnfen03 tnfen02 0 tnfen00 note 1 address: f0062h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 nfen2 0 0 0 tnfensl 0 0 0 0 tnfen07 enable/disable using noise filt er of ti07/to07/p15 (p51) pin note 2 or rxd0/p74 pin input signal note 3 0 noise filter off 1 noise filter on tnfen06 enable/disable using noise filt er of ti06/to06/p14 (p50) pin note 2 input signal 0 noise filter off 1 noise filter on tnfen05 enable/disable using noise filt er of ti05/to05/p13 pin input signal 0 noise filter off 1 noise filter on tnfen04 enable/disable using noise filter of ti04/to04/rtcdiv/rtccl/p12 pin input signal 0 noise filter off 1 noise filter on tnfen03 enable/disable using noise filt er of ti03/to03/p11 pin input signal 0 noise filter off 1 noise filter on tnfen02 enable/disable using noise filt er of ti02/to02/p10 pin input signal 0 noise filter off 1 noise filter on tnfen00 note 1 enable/disable using noise filter of ti00/p00 pin input signal 0 noise filter off 1 noise filter on tnfensl enable/disable using noise filt er of slti/slto/p52 pin input signal 0 noise filter off 1 noise filter on notes 1. 78k0r/kd3-l and 78k0r/ke3-l only 2. ti06/to06 and ti07/to07 are shared with p50 and p51, respective ly, in products other than the 78k0r/ke3-l. 3. the applicable pin can be switched by setting isc1 of the isc register. isc1 = 0: whether or not to use the noise filter of ti07 pin can be selected. isc1 = 1: whether or not to use the noi se filter of rxd0 pin can be selected. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 246 (15) port mode registers 0 note , 1, 5 (pm0 note , pm1, pm5) these registers set input/output of ports 0 note , 1, and 5 in 1-bit units. when using the ports (such as p01/to00 and p10/to02/ti 02) to be shared with the timer output pin for timer output, set the port mode register (pmxx) bit and port register (pxx) bit corresponding to each port to 0. example: when using p10/to02/ti02 for timer output set the pm10 bit of port mode register 1 to 0. set the p10 bit of port register 1 to 0. when using the ports (such as p00/ ti00 and p10/to02/ti02) to be shared with the timer output pin for timer input, set the port mode register (pmxx) bit corresponding to each port to 1. at this time, the port register (pxx) bit may be 0 or 1. example: when using p10/to02/ti02 for timer input set the pm10 bit of port mode register 1 to 1. set the p10 bit of port register 1 to 0 or 1. pm0 note , pm1, and pm5 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation se ts these registers to ffh. note 78k0r/kd3-l and 78k0r/ke3-l only figure 6-23. format of port mode registers 0, 1, 5 (pm0, pm1, pm5) address: fff20h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm0 1 1 1 1 1 1 pm01 pm00 address: fff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 address: fff25h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm5 1 1 1 1 pm53 pm52 pm51 pm50 pmmn pmn pin i/o mode selection (m = 0, 1, 5; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) remark the figure shown above presents the fo rmat of port mode register 0, 1, and 5 of 78k0r/ke3-l products. for the format of port mode register of other products, see (1) port mode r egisters (pmxx) in 4.3 registers controlling port function. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 247 6.4 channel output (to0n pin) control 6.4.1 to0n pin output circuit configuration figure 6-24. output circuit configuration interrupt signal of the master channel (inttm0n) tol0n tom0n toe0n <1> <2> <3> <4> <5> to0n write signal to0n pin to0n register set reset/toggle internal bus interrupt signal of the slave channel (inttm0p) controller the following describes the to0n pin output circuit. <1> when tom0n = 0 (toggle mode), the set value of t he tol0n register is ignored and only inttm0p (slave channel timer interrupt) is transmitted to the to0n register. <2> when tom0n = 1 (combination-operation mode), both inttm0n (master channel timer interrupt) and inttm0p (slave channel timer interrupt) are transmitted to the to0n register. at this time, the tol0n register becomes valid and the signals are controlled as follows: when tol0n = 0: forward operation (inttm0 set, inttm0p reset) when tol0n = 1: reverse operation (inttm0 reset, inttm0p set) when inttm0n and inttm0p are simultaneously generated, (0% output of pwm), inttm0p (reset signal) takes priority, and inttm0n (set signal) is masked. <3> when toe0n = 1, inttm0n (master channel timer interrupt) and inttm0p (slave channel timer interrupt) are transmitted to the to0n register. writing to t he to0n register (to0n write signal) becomes invalid. when toe0n = 1, the to0n pin output never chang es with signals other than interrupt signals. to initialize the to0n pin output level, it is nece ssary to set toe0n = 0 and to write a value to to0n. <4> when toe0n = 0, writing to to0n bit to the tar get channel (to0n write signal) becomes valid. when toe0n = 0, neither inttm0n (master channel time r interrupt) nor inttm0p (slave channel timer interrupt) is transmitted to to0n register. <5> the to0n register can always be read, and the to0n pin output level can be checked. remarks 1. n = 0 to 7 (n = 0, 2, 4, or 6 for master channel) 2. p = n + 1, n + 2, n + 3 ... (where p 7) chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 248 6.4.2 to0n pin output setting the following figure shows the procedure and status transition of to0n out put pin from initial setting to timer operation start. figure 6-25. status transition from ti mer output setting to operation start tcr0n timer alternate-function pin timer output signal toe0n to0n (counter) undefined value (ffffh after reset) write operation enabled period to to0n <1> set tom0n set tol0n <4> set the port to output mode <2> set to0n <3> set toe0n <5> timer operation start write operation disabled period to to0n hi-z <1> the operation mode of timer output is set. ? tom0n bit (0: toggle mode, 1: combination-operation mode) ? tol0n bit (0: forward output, 1: reverse output) <2> the timer output signal is set to the initial status by setting to0n. <3> the timer output operation is enabled by wr iting 1 to toe0n (writing to to0n is disabled). <4> the port i/o setting is set to output (see 6.3 (15) port mode registers 0, 1, 5 ). <5> the timer operation is enabled (ts0n = 1). remark n = 0 to 7 6.4.3 cautions on channel output operation (1) changing values set in registers to 0, toe0, and tol0 during timer operation since the timer operations (operati ons of tcr0n and tdr0n) are indepen dent of the to0n output circuit and changing the values set in to0, toe0, and tol0 does not affect the timer operation, the values can be changed during timer operation. when the values set in toe0, tol0, and tom0 (except for to0) are changed close to the timer interrupt (inttm0n), the waveform output to the to0n pin ma y be different depending on whether the values are changed immediately before or immediately after the ti mer interrupt (inttm0n) signal generation timing. remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 249 (2) default level of to0n pin and output level after timer operation start the following figure shows the to0n pin output level transition when writing has been done in the state of toe0n = 0 before port output is enabled and toe0n = 1 is set after changing the default level. (a) when operation starts with tom0n = 0 setting (toggle output) the setting of tol0n is invalid when tom0n = 0. when the timer operation starts after setting the default level, the toggle signal is generated an d the output level of to0n pin is reversed. figure 6-26. to0n pin output status at toggle output (tom0n = 0) toe0n to0n = 0, tol0n = 0 to0n = 1, tol0n = 0 to0n = 0, tol0n = 1 (same output waveform as tol0n = 0) to0n = 1, tol0n = 1 (same output waveform as tol0n = 0) default level, tol0n setting independent of tol0n setting port output is enabled to0n pin transition toggle toggle toggle toggle toggle hi-z hi-z hi-z hi-z dependent on to0n setting remarks 1. toggle: reverse to0n pin output status 2. n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 250 (b) when operation starts with tom0n = 1 setti ng (combination-operation mode (pwm output)) when tom0n = 1, the active level is determined by tol0n setting. figure 6-27. to0n pin output stat us at pwm output (tom0n = 1) toe0n to0n = 0, tol0n = 0 (active high) to0n = 1, tol0n = 0 (active high) to0n = 0, tol0n = 1 (active low) to0n = 1, tol0n = 1 (active low) default level, tol0n setting dependent on tol0n setting dependent on to0n setting no change set reset set reset set hi-z hi-z hi-z hi-z to0n pin transition port output is enabled remarks 1. set: the output signal of to0n pin changes from inactive level to active level. reset: the output signal of to0n pin changes from active level to inactive level. 2. n = 0 to 7 (3) operation of to0n pin in combination-operation mode (tom0n = 1) (a) when tol0n setting has been changed during timer operation when the tol0n setting has been changed during timer operation, the setting becomes valid at the generation timing of to0n change condition. rewriti ng tol0n does not change the output level of to0n. the following figure shows the operation when the value of tol0n has been changed during timer operation (tom0n = 1). figure 6-28. operation when tol0n ha s been changed during timer operation internal set signal internal reset signal tol0n to0n pin set/reset signals are inverted to0n does not change remarks 1. set: the output signal of to0n pin changes from inactive level to active level. reset: the output signal of to0n pin changes from active level to inactive level. 2. n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 251 (b) set/reset timing to realize 0%/100% output at pwm output, the to0n pi n/to0n set timing at master channel timer interrupt (inttm0n) generation is delayed by 1 count clock by the slave channel. if the set condition and reset condition are generated at the same time, a higher priority is given to the latter. figure 6-29 shows the set/reset operat ing statuses where the master/sla ve channels are set as follows. master channel: toe0n = 1, tom0n = 0, tol0n = 0 slave channel: toe0p = 1, tom0p = 1, tol0p = 0 figure 6-29. set/reset ti ming operating statuses to_reset (internal signal) to_reset (internal signal) (internal signal) inttm0n to0n pin/ to0n to0p pin/ to0p count clock f clk inttm0p to_set delays to_reset by 1 count clock with slave channel toggle set reset master channel slave channel remarks 1. to_reset: to0n pin reset/toggle signal to_set: to0n pin set signal 2. n = 0 to 7 (where n = 0, 2, 4, or 6 for master channel) 3. p = n+1, n+2, n+3 ... (where p 7) chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 252 6.4.4 collective mani pulation of to0n bit in the to0 register, the setting bits for all the channels ar e located in one register in the same way as the ts0 register (channel start trigger). theref ore, to0n of all the channels can be manipu lated collectively. only specific bits can also be manipulated by setting the correspondi ng toe0n = 0 to a target to0n (channel output). figure 6-30. example of to0n bit collective manipulation before writing to0 0 0 0 0 0 0 0 0 to07 0 to06 0 to05 1 to04 0 to03 0 to02 0 to01 1 to00 0 toe0 0 0 0 0 0 0 0 0 toe07 0 toe06 0 toe05 1 toe04 0 toe03 1 toe02 1 toe01 1 toe00 1 data to be written 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 after writing to0 0 0 0 0 0 0 0 0 to07 1 to06 1 to05 1 to04 0 to03 0 to02 0 to01 1 to00 0 writing is done only to to0n bit with toe0n = 0, and writing to to0n bit with toe0n = 1 is ignored. to0n (channel output) to which toe0n = 1 is set is not affe cted by the write op eration. even if the write operation is done to to0n, it is ignored and the output change by timer operation is normally done. figure 6-31. to0n pin statuses by collective manipulation of to0n bit to07 to06 to05 to04 to03 to02 to01 to00 two or more to0n output can be changed simultaneously output does not change when value does not change before writing writing to to0n register is ignored when toe0n = 1 writing to to0n register (caution and remark are given on the next page.) o o o chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 253 caution when toe0n = 1, even if the output by ti mer interrupt of each timer (inttm0n) contends with writing to to0n, output is normally done to to0n pin. remark n = 0 to 7 6.4.5 timer interrupt and to0n pin output at operation start in the interval timer mode or capture mode, the md0n0 bit in the tmr0n register sets whether or not to generate a timer interrupt at count start. when md0n0 is set to 1, the count operation start timing can be known by the timer interrupt (inttm0n) generation. in the other modes, neither timer interrupt at c ount operation start nor to 0n output is controlled. figures 6-32 and 6-33 show operation examples when the interval timer mode (toe0n = 1, tom0n = 0) is set. figure 6-32. when md0n0 is set to 1 tcr0n te0n to0n inttm0n count operation start when md0n0 is set to 1, a timer interrupt (inttm0n) is output at count operation start, and to0n performs a toggle operation. figure 6-33. when md0n0 is set to 0 tcr0n te0n to0n inttm0n count operation start when md0n0 is set to 0, a timer interrupt (inttm0n) is not output at count operation start, and to0n does not change either. after counting one cycle, inttm0n is output and to0n performs a toggle operation. remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 254 6.5 channel input (ti0n pin) control 6.5.1 ti0n edge detection circuit (1) edge detection basic operation timing edge detection circuit sampling is done in accordance with the operation clock (mck). figure 6-34. edge detect ion basic operation timing f clk rising edge detection internal trigger falling edge detection internal trigger operation clock (mck) synchronized (noise filter) internal ti0n signal remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 255 6.6 basic function of timer array unit taus 6.6.1 overview of single-operation func tion and combination-operation function timer array unit taus consists of several channels and has a single-operation function that allows each channel to operate independently, and a combination-operation functi on that uses two or more channels in combination. the single-operation function can be used for any channel, regardless of the operation mode of the other channels. the combination-operation function is r ealized by combining a master channel (reference timer that mainly counts periods) and a slave channel (timer that operates in acco rdance with the master channel), and several rules must be observed when using this function. 6.6.2 basic rules of comb ination-operation function the basic rules of using the combinat ion-operation function are as follows. (1) only an even channel (channel 0, 2, 4, etc.) can be set as a master channel. (2) any channel, except channel 0, can be set as a slave channel. (3) the slave channel must be lower than the master channel. example: if channel 2 is set as a master channel, channel 3 or those that follow (ch annels 3, 4, 5, etc.) can be set as a slave channel. (4) two or more slave channels can be set for one master channel. (5) when two or more master channels are to be used, slave channels with a master channel between them may not be set. example: if channels 0 and 4 are set as master channel s, channels 1 to 3 can be set as the slave channels of master channel 0. channels 5 to 7 cannot be set as the slave channels of master channel 0. (6) the operating clock for a slave channel in combination with a master channel must be the same as that of the master channel. the cks bit (bit 15 of the tmr0n register) of the slave c hannel that operates in combination with the master channel must be the same value as that of the master channel. (7) a master channel can transmit inttm0n (interrupt), start software trigger, and count clock to the lower channels. (8) a slave channel can use the inttm0n (interrupt), star t software trigger, and count clock of the master channel, but it cannot transmit its own inttm0n (i nterrupt), start software trigger, and count clock to the lower channel. (9) a master channel cannot use the inttm0n (interrupt ), start software trigger, and count clock from the other higher master channel. (10) to simultaneously start channels that operate in combination, the ts0n bit of the channels in combination must be set at the same time. (11) to stop the channels in combination simultaneously, the tt0n bit of the channels in combination must be set at the same time. remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 256 channel 1: slave channel 0: master channel group 1 (combination-operation function) * the operating clock of channel group 1 may be different from that of channel group 2. channel 2: slave channel 3: single-operation function channel 4: master channel 7: single-operation function ck00 ck01 taus * a channel that singly operates may be between channel group 1 and channel group 2. channel group 2 (combination-operation function) channel 6: slave channel 5: single-operation function ck00 * a channel that singly operates may be between a master and a slave of channel group 2. furthermore, the operating clock may be set separately. 6.6.3 applicable range of basic ru les of combination-operation function the rules of the combination-operat ion function are applied in a channel group (a master channel and slave channels forming one combination-operation function). if two or more channel groups that do not operate in comb ination are specified, the bas ic rules of the combination- operation function in 6.6.2 basic rules of comb ination-operation function do not apply to the channel groups. example chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 257 6.7 operation of timer array unit taus as independent channel 6.7.1 operation as interval timer/square wave output (1) interval timer the timer array unit can be used as a reference timer that generates inttm0n (timer interrupt) at fixed intervals. the interrupt generation period can be calculated by the following expression. generation period of inttm0n (timer in terrupt) = period of count clock (set value of tdr0n + 1) (2) operation as square wave output to0n performs a toggle operation as soon as inttm0n has been generated, and outputs a square wave with a duty factor of 50%. the period and frequency for outputting a square wave from to0n can be calculated by the following expressions. ? period of square wave output from to0n = period of count clock (set value of tdr0n + 1) 2 ? frequency of square wave output from to0n = fr equency of count clock/{(set value of tdr0n + 1) 2} tcr0n operates as a down counter in the interval timer mode. tcr0n loads the value of tdr0n at the fi rst count clock after the channel start trigger bit (ts0n) is set to 1. if md0n0 of tmr0n = 0 at this time, inttm0n is not out put and to0n is not toggled. if md0n0 of tmr0n = 1, inttm0n is output and to0n is toggled. after that, tcr0n count down in synchronization with the count clock. when tcr0n = 0000h, inttm0n is output and to0n is toggled at the next count clock. at the same time, tcr0n loads the value of tdr0n again. after that, the same operation is repeated. tdr0n can be rewritten at any time. the new val ue of tdr0n becomes valid from the next period. figure 6-35. block diagram of operation as interval timer/square wave output timer counter (tcr0n) to0n pin interrupt signal (inttm0n) data register (tdr0n) interrupt controller output controller clock selection trigger selection operation clock ck00 ck01 ts0n remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 258 figure 6-36. example of basic timing of operati on as interval timer/square wave output (md0n0 = 1) ts0n te0n tdr0n tcr0n to0n inttm0n a a+1 b 0000h a+1 a+1 b+1 b+1 b+1 remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 259 figure 6-37. example of set contents of regi sters in interval timer/square wave output (a) timer mode register 0n (tmr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks0n 1/0 0 0 ccs0n 0 mas ter0n 0 sts0n2 0 sts0n1 0 sts0n0 0 cis0n1 0 cis0n0 0 0 0 md0n3 0 md0n2 0 md0n1 0 md0n0 1/0 operation mode of channel n 000b: interval timer setting of operation when counting is started 0: neither generates inttm0n nor inverts timer output when counting is started. 1: generates inttm0n and inverts timer output when counting is started. selection of ti0n pin input edge 00b: sets 00b because these are not used. start trigger selection 000b: selects only software start. slave/master selection 0: cleared to 0 when single-operation function is selected. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel n. 1: selects ck01 as operation clock of channel n. (b) timer output register 0 (to0) bit n to0 to0n 1/0 0: outputs 0 from to0n. 1: outputs 1 from to0n. (c) timer output enable register 0 (toe0) bit n toe0 toe0n 1/0 0: stops the to0n output operation by counting operation. 1: enables the to0n output operation by counting operation. (d) timer output level register 0 (tol0) bit n tol0 tol0n 0 0: cleared to 0 when tom0n = 0 (toggle mode) (e) timer output mode register 0 (tom0) bit n tom0 tom0n 0 0: sets toggle mode. remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 260 figure 6-38. operation procedure of inte rval timer/square wave output function software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per2 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) taus default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. sets the tmr0n register (determines operation mode of channel). sets interval (period) value to the tdr0n register. channel stops operating. (clock is supplied and some power is consumed.) channel default setting to use the to0n output clears the tom0n bit of the tom0 register to 0 (toggle mode). clears the tol0n bit to 0. sets the to0n bit and determines default level of the to0n output. sets toe0n to 1 and enables operation of to0n. clears the port register and port mode register to 0. the to0n pin goes into hi-z output state. the to0n default setting level is output when the port mode register is in the output mode and the port register is 0. to0n does not change because channel stops operating. the to0n pin outputs the to0n set level. operation start sets toe0n to 1 (only when operation is resumed). sets the ts0n bit to 1. the ts0n bit automatically returns to 0 because it is a trigger bit. te0n = 1, and count operation starts. value of tdr0n is loaded to tcr0n at the count clock input. inttm0n is generated and to0n performs toggle operation if the md0n0 bit of the tmr0n register is 1. during operation set values of tmr0n, tom0, and tol0 registers cannot be changed. set value of the tdr0n register can be changed. the tcr0n register can always be read. the tsr0n register is not used. set values of the to0 and toe0 registers can be changed. counter (tcr0n) counts down. when count value reaches 0000h, the value of tdr0n is loaded to tcr0n again and the count operation is continued. by detecting tcr0n = 0000h, inttm0n is generated and to0n performs toggle operation. after that, the above operation is repeated. the tt0n bit is set to 1. the tt0n bit automatically returns to 0 because it is a trigger bit. te0n = 0, and count operation stops. tcr0n holds count value and stops. the to0n output is not initialized but holds current status. operation stop toe0n is cleared to 0 and value is set to the to0n bit. the to0n pin outputs the to0n set level. taus stop to hold the to0n pin output level clears to0n bit to 0 after the value to be held is set to the port register. when holding the to0n pin output level is not necessary switches the port mode register to input mode. the to0n pin output level is held by port function. the to0n pin output level goes into hi-z output state. the tau0en bit of the per2 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. (the to0n bit is cleared to 0 and the to0n pin is set to port mode.) remark n = 0 to 7 operation is resumed. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 261 6.7.2 operation as external event counter the timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the ti0n pin. when a specified count valu e is reached, the event counter generates an interrupt. the specified number of counts ca n be calculated by the following expression. specified number of counts = set value of tdr0n + 1 tcr0n operates as a down counter in the event counter mode. when the channel start trigger bit (ts0n) is set to 1, tcr0n loads the value of tdr0n. tcr0n counts down each time the valid input edge of the ti0n pin has been detected. when tcr0n = 0000h, tcr0n loads the value of tdr 0n again, and outputs inttm0n. after that, the above operation is repeated. to0n must not be used because its waveform depends on the external event and irregular. tdr0n can be rewritten at any time. the new value of tdr0n becomes valid during the next count period. figure 6-39. block diagram of oper ation as external event counter timer counter (tcr0n) edge detection interrupt signal (inttm0n) ti0n pin data register (tdr0n) interrupt controller clock selection trigger selection ts0n remark n = 0 to 7 figure 6-40. example of basic timing of operation as external event counter ts0n te0n ti0n tdr0n tcr0n 0003h 0002h 0 0000h 1 3 0 1 2 0 1 2 1 2 3 2 inttm0n 4 events 4 events 3 events remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 262 figure 6-41. example of set contents of registers in external event counter mode (a) timer mode register 0n (tmr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks0n 1/0 0 0 ccs0n 1 mas ter0n 0 sts0n2 0 sts0n1 0 sts0n0 0 cis0n1 1/0 cis0n0 1/0 0 0 md0n3 0 md0n2 1 md0n1 1 md0n0 0 operation mode of channel n 011b: event count mode setting of operation when counting is started 0: neither generates inttm0n nor inverts timer output when counting is started. selection of ti0n pin input edge 00b: detects falling edge. 01b: detects rising edge. 10b: detects both edges. 11b: setting prohibited start trigger selection 000b: selects only software start. slave/master selection 0: cleared to 0 when single-operation function is selected. count clock selection 1: selects the ti0n pin input valid edge. operation clock selection 0: selects ck00 as operation clock of channel n. 1: selects ck01 as operation clock of channel n. (b) timer output register 0 (to0) bit n to0 to0n 0 0: outputs 0 from to0n. (c) timer output enable register 0 (toe0) bit n toe0 toe0n 0 0: stops the to0n output operation by counting operation. (d) timer output level register 0 (tol0) bit n tol0 tol0n 0 0: cleared to 0 when tom0n = 0 (toggle mode). (e) timer output mode register 0 (tom0) bit n tom0 tom0n 0 0: sets toggle mode. remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 263 figure 6-42. operation procedure when ex ternal event counter function is used software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per2 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) taus default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. channel default setting sets the tmr0n register (determines operation mode of channel). sets number of counts to the tdr0n register. clears the toe0n bit of the toe0 register to 0. channel stops operating. (clock is supplied and some power is consumed.) operation start sets the ts0n bit to 1. the ts0n bit automatically returns to 0 because it is a trigger bit. te0n = 1, and count operation starts. value of tdr0n is loaded to tcr0n and detection of the ti0n pin input edge is awaited. during operation set value of the tdr0n register can be changed. the tcr0n register can always be read. the tsr0n register is not used. set values of tmr0n, tom0, tol0, to0, and toe0 registers cannot be changed. counter (tcr0n) counts down each time input edge of the ti0n pin has been detected. when count value reaches 0000h, the value of tdr0n is loaded to tcr0n again, and the count operation is continued. by detecting tcr0n = 0000h, the inttm0n output is generated. after that, the above operation is repeated. operation stop the tt0n bit is set to 1. the tt0n bit automatically returns to 0 because it is a trigger bit. te0n = 0, and count operation stops. tcr0n holds count value and stops. taus stop the tau0en bit of the per2 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. remark n = 0 to 7 operation is resumed. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 264 6.7.3 operation as frequency divider (channe l 0 of 78k0r/kd3-l and 78k0r/ke3-l only) the timer array unit can be used as a frequency divider that divides a clock input to the ti00 pin and outputs the result from to00. the divided clock frequency output from to00 c an be calculated by the following expression. ? when rising edge/falling edge is selected: divided clock frequency = input clock frequency/{(set value of tdr00 + 1) 2} ? when both edges are selected: divided clock frequency ? input clock frequency/(set value of tdr00 + 1) tcr00 operates as a down counter in the interval timer mode. after the channel start trigger bit (ts00) is set to 1, tcr00 loads the value of tdr 00 when the ti00 valid edge is detected. if md000 of tmr00 = 0 at this time, inttm00 is not output and to00 is not toggled. if md000 of tmr00 = 1, inttm00 is output an d to00 is toggled. after that, tcr00 counts down at the valid edge of ti00. when tcr00 = 0000h, it toggl es to00. at the same time, tcr00 loads the value of t dr00 again, and continues counting. if detection of both the edges of ti00 is selected, the duty factor error of the input clock affects the divided clock period of the to00 output. the period of the to00 output clock includes a samp ling error of one period of the operation clock. clock period of to00 output = ideal to00 output clock period operation clock period (error) tdr00 can be rewritten at any time. the new value of tdr00 becomes valid during the next count period. figure 6-43. block diagram of operation as frequency divider timer counter (tcr00) edge detection ti00 pin data register (tdr00) clock selection trigger selection ts00 to00 pin output controller chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 265 figure 6-44. example of basic timing of operation as frequency divider (md000 = 1) ts00 te00 ti00 tdr00 tcr00 to00 inttm00 0002h divided by 6 0001h 0 0000h 1 2 0 1 2 0 1 0 1 0 1 0 1 0 1 2 divided by 4 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 266 figure 6-45. example of set contents of re gisters during operation as frequency divider (a) timer mode register 00 (tmr00) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr00 cks00 1/0 0 0 ccs00 1 mas ter00 0 sts002 0 sts001 0 sts000 0 cis001 1/0 cis000 1/0 0 0 md003 0 md002 0 md001 0 md000 1/0 operation mode of channel 0 000b: interval timer setting of operation when counting is started 0: neither generates inttm00 nor inverts timer output when counting is started. 1: generates inttm00 and inverts timer output when counting is started. selection of ti00 pin input edge 00b: detects falling edge. 01b: detects rising edge. 10b: detects both edges. 11b: setting prohibited start trigger selection 000b: selects only software start. slave/master selection 0: cleared to 0 when single-operation function is selected. count clock selection 1: selects the ti00 pin input valid edge. operation clock selection 0: selects ck00 as operation clock of channel 0. 1: selects ck01 as operation clock of channel 0. (b) timer output register 0 (to0) bit 0 to0 to00 1/0 0: outputs 0 from to00. 1: outputs 1 from to00. (c) timer output enable register 0 (toe0) bit 0 toe0 toe00 1/0 0: stops the to00 output operation by counting operation. 1: enables the to00 output operation by counting operation. (d) timer output level register 0 (tol0) bit 0 tol0 tol00 0 0: cleared to 0 when tom00 = 0 (toggle mode) (e) timer output mode register 0 (tom0) bit 0 tom0 tom00 0 0: sets toggle mode. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 267 figure 6-46. operation procedure when frequency divider function is used software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per2 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) taus default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. sets the tmr00 register (determines operation mode of channel). sets interval (period) value to the tdr00 register. channel stops operating. (clock is supplied and some power is consumed.) channel default setting clears the tom00 bit of the tom0 register to 0 (toggle mode). clears the tol00 bit to 0. sets the to00 bit and determines default level of the to00 output. sets toe00 to 1 and enables operation of to00. clears the port register and port mode register to 0. the to00 pin goes into hi-z output state. the to00 default setting level is output when the port mode register is in output mode and the port register is 0. to00 does not change because channel stops operating. the to00 pin outputs the to00 set level. operation start sets the toe00 to 1 (only when operation is resumed). sets the ts00 bit to 1. the ts00 bit automatically returns to 0 because it is a trigger bit. te00 = 1, and count operation starts. value of tdr00 is loaded to tcr00 at the count clock input. inttm00 is generated and to00 performs toggle operation if the md000 bit of the tmr00 register is 1. during operation set value of the tdr00 register can be changed. the tcr00 register can always be read. the tsr00 register is not used. set values of to0 and toe0 registers can be changed. set values of tmr00, tom0, and tol0 registers cannot be changed. counter (tcr00) counts down. when count value reaches 0000h, the value of tdr00 is loaded to tcr00 again, and the count operation is continued. by detecting tcr00 = 0000h, inttm00 is generated and to00 performs toggle operation. after that, the above operation is repeated. the tt00 bit is set to 1. the tt00 bit automatically returns to 0 because it is a trigger bit. te00 = 0, and count operation stops. tcr00 holds count value and stops. the to00 output is not initialized but holds current status. operation stop toe00 is cleared to 0 and value is set to the to00 bit. the to00 pin outputs the to00 set level. to hold the to00 pin output level clears to00 bit to 0 after the value to be held is set to the port register. when holding the to00 pin output level is not necessary switches the port mode register to input mode. the to00 pin output level is held by port function. the to00 pin output level goes into hi-z output state. taus stop the tau0en bit of the per2 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. (the to00 bit is cleared to 0 and the to00 pin is set to port mode). operation is resumed. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 268 6.7.4 operation as input pu lse interval measurement the count value can be captured at the ti0n valid edge and t he interval of the pulse input to ti0n can be measured. the pulse interval can be calculated by the following expression. ti0n input pulse interval = period of count clock ((10000h tsr0n: ovf) + (capture value of tdr0n + 1)) caution the ti0n pin input is sampled using the operating clock selected with the cks0n bit of the tmr0n register, so an error equivalent to one operation clock occurs. tcr0n operates as an up counter in the capture mode. when the channel start trigger (ts0n) is set to 1, tcr 0n counts up from 0000h in synchronization with the count clock. when the ti0n pin input valid edge is det ected, the count value is transferr ed (captured) to tdr0n and, at the same time, the counter (tcr0n) is cleared to 0000h, and the in ttm0n is output. if the counter overflows at this time, the ovf bit of the tsr0n register is set to 1. if the count er does not overflow, the ovf bit is cleared. after that, the above operation is repeated. as soon as the count value has been capt ured to the tdr0n register, the ovf bit of the tsr0n register is updated depending on whether the counter overflow s during the measurement pe riod. therefore, the ov erflow status of the captured value can be checked. if the counter reaches a full count for two or more periods , it is judged to be an overflow occurrence, and the ovf bit of the tsr0n register is set to 1. however, a normal interval value cannot be measured for the ovf bit, if two or more overflows occur. set sts0n2 to sts0n0 of the tmr0n register to 001b to use the valid edges of ti0n as a start trigger and a capture trigger. when te0n = 1, instead of the ti0n pin input, a software operation (ts0n = 1) can be used as a capture trigger. figure 6-47. block diagram of operatio n as input pulse interval measurement timer counter (tcr0n) interrupt signal (inttm0n) data register (tdr0n) interrupt controller clock selection trigger selection operation clock ck00 ck01 edge detection ti0n pin ts0n remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 269 figure 6-48. example of basic timing of operati on as input pulse interval measurement (md0n0 = 0) ts0n te0n ti0n tdr0n tcr0n 0000h c b 0000h a c d inttm0n ffffh b a d ovf0n remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 270 figure 6-49. example of set contents of registers to measure input pulse interval (a) timer mode register 0n (tmr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks0n 1/0 0 0 ccs0n 0 mas ter0n 0 sts0n2 0 sts0n1 0 sts0n0 1 cis0n1 1/0 cis0n0 1/0 0 0 md0n3 0 md0n2 1 md0n1 0 md0n0 1/0 operation mode of channel n 010b: ca p ture mode setting of operation when counting is started 0: does not generate inttm0n when counting is started. 1: generates inttm0n when counting is started. selection of ti0n pin input edge 00b: detects falling edge. 01b: detects rising edge. 10b: detects both edges. 11b: setting prohibited capture trigger selection 001b: selects the ti0n pin input valid edge. slave/master selection 0: cleared to 0 when single-operation function is selected. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel n. 1: selects ck01 as operation clock of channel n. (b) timer output register 0 (to0) bit n to0 to0n 0 0: outputs 0 from to0n. (c) timer output enable register 0 (toe0) bit n toe0 toe0n 0 0: stops to0n output operation by counting operation. (d) timer output level register 0 (tol0) bit n tol0 tol0n 0 0: cleared to 0 when tom0n = 0 (toggle mode). (e) timer output mode register 0 (tom0) bit n tom0 tom0n 0 0: sets toggle mode. remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 271 figure 6-50. operation procedure when input pulse interval measurement function is used software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per2 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) taus default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. channel default setting sets the tmr0n register (determines operation mode of channel). channel stops operating. (clock is supplied and some power is consumed.) operation start sets ts0n bit to 1. the ts0n bit automatically returns to 0 because it is a trigger bit. te0n = 1, and count operation starts. tcr0n is cleared to 0000h at the count clock input. when the md0n0 bit of the tmr0n register is 1, inttm0n is generated. during operation set values of only the cis0n1 and cis0n0 bits of the tmr0n register can be changed. the tdr0n register can always be read. the tcr0n register can always be read. the tsr0n register can always be read. set values of tom0, tol0, to0, and toe0 registers cannot be changed. counter (tcr0n) counts up from 0000h. when the ti0n pin input valid edge is detected, the count value is transferred (captured) to tdr0n. at the same time, tcr0n is cleared to 0000h, and the inttm0n signal is generated. if an overflow occurs at this time, the ovf bit of the tsr0n register is set; if an overflow does not occur, the ovf bit is cleared. after that, the above operation is repeated. operation stop the tt0n bit is set to 1. the tt0n bit automatically returns to 0 because it is a trigger bit. te0n = 0, and count operation stops. tcr0n holds count value and stops. the ovf bit of the tsr0n register is also held. taus stop the tau0en bit of the per2 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. remark n = 0 to 7 operation is resumed. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 272 6.7.5 operation as input signal hi gh-/low-level width measurement by starting counting at one edge of ti0n and capturing the number of counts at another edge, the signal width (high-level width/low-level width) of ti0n can be measured. the signal width of ti0n can be calculated by the following expression. signal width of ti0n input = period of count clock ((10000h tsr0n: ovf) + (capture value of tdr0n + 1)) caution the ti0n pin input is sampled using the operating clock selected with the cks0n bit of the tmr0n register, so an error equivalent to one operation clock occurs. tcr0n operates as an up counter in the capture & one-count mode. when the channel start trigger (ts0n) is set to 1, te0n is set to 1 and the ti 0n pin start edge detection wait status is set. when the ti0n start valid edge (rising edge of ti0n when the high-level width is to be measured) is detected, the counter counts up in synchronization with the count clock. when the valid capture edge (falling edge of ti0n when the high-level width is to be measured) is det ected later, the count value is transfe rred to tdr0n and, at the same time, inttm0n is output. if the counter overflows at this time, the ovf bit of the tsr0n register is set to 1. if the counter does not overflow, the ovf bit is clear ed. tcr0n stops at the value ?value transferred to tdr0n + 1?, and the ti0n pin start edge detection wait status is set. after that, the above operation is repeated. as soon as the count value has been capt ured to the tdr0n register, the ovf bit of the tsr0n register is updated depending on whether the counter overflow s during the measurement pe riod. therefore, the ov erflow status of the captured value can be checked. if the counter reaches a full count for two or more periods , it is judged to be an overflow occurrence, and the ovf bit of the tsr0n register is set to 1. however, a normal interval value cannot be measured for the ovf bit, if two or more overflows occur. whether the high-level width or low-le vel width of the ti0n pin is to be measured can be selected by using the cis0n1 and cis0n0 bits of the tmr0n register. because this function is used to measure the signal wi dth of the ti0n pin input, ts0n cannot be set to 1 while te0n is 1. cis0n1, cis0n0 of tmr0n = 10b: low-level width is measured. cis0n1, cis0n0 of tmr0n = 11b: high-level width is measured. figure 6-51. block diagram of operation as in put signal high-/low-le vel width measurement timer counter (tcr0n) interrupt signal (inttm0n) data register (tdr0n) interrupt controller clock selection trigger selection operation clock ck00 ck01 edge detection ti0n pin remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 273 figure 6-52. example of basic timing of operati on as input signal high-/low- level width measurement ts0n te0n ti0n tdr0n tcr0n b 0000h a c inttm0n ffffh b a c ovf0n 0000h remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 274 figure 6-53. example of set contents of regist ers to measure input signal high-/low-level width (a) timer mode register 0n (tmr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks0n 1/0 0 0 ccs0n 0 mas ter0n 0 sts0n2 0 sts0n1 1 sts0n0 0 cis0n1 1 cis0n0 1/0 0 0 md0n3 1 md0n2 1 md0n1 0 md0n0 0 operation mode of channel n 110b: capture & one-count setting of operation when counting is started 0: does not generate inttm0n when counting is started. selection of ti0n pin input edge 10b: both edges (to measure low-level width) 11b: both edges (to measure high-level width) start trigger selection 010b: selects the ti0n pin input valid edge. slave/master selection 0: cleared to 0 when single-operation function is selected. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel n. 1: selects ck01 as operation clock of channel n. (b) timer output register 0 (to0) bit n to0 to0n 0 0: outputs 0 from to0n. (c) timer output enable register 0 (toe0) bit n toe0 toe0n 0 0: stops the to0n output operation by counting operation. (d) timer output level register 0 (tol0) bit n tol0 tol0n 0 0: cleared to 0 when tom0n = 0 (toggle mode). (e) timer output mode register 0 (tom0) bit n tom0 tom0n 0 0: sets toggle mode. remark n = 0 to 7 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 275 figure 6-54. operation procedure when input signal high-/low-level width measu rement function is used software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per2 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) taus default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. channel default setting sets the tmr0n register (determines operation mode of channel). clears toe0n to 0 and stops operation of to0n. channel stops operating. (clock is supplied and some power is consumed.) sets the ts0n bit to 1. the ts0n bit automatically returns to 0 because it is a trigger bit. te0n = 1, and the ti0n pin start edge detection wait status is set. operation start detects ti0n pin input count start valid edge. clears tcr0n to 0000h and starts counting up. during operation set value of the tdr0n register can be changed. the tcr0n register can always be read. the tsr0n register is not used. set values of tmr0n, tom0, tol0, to0, and toe0 registers cannot be changed. when the ti0n pin start edge is detected, the counter (tcr0n) counts up from 0000h. if a capture edge of the ti0n pin is detected, the count value is transferred to tdr0n and inttm0n is generated. if an overflow occurs at this time, the ovf bit of the tsr0n register is set; if an overflow does not occur, the ovf bit is cleared. tcr0n stops the count operation until the next ti0n pin start edge is detected. operation stop the tt0n bit is set to 1. tt0n bit automatically returns to 0 because it is a trigger bit. te0n = 0, and count operation stops. tcr0n holds count value and stops. the ovf bit of the tsr0n register is also held. taus stop the tau0en bit of per2 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. remark n = 0 to 7 operation is resumed. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 276 6.8 operation of plural channels of timer array unit taus 6.8.1 operation as pwm function two channels can be used as a set to generate a pulse of any period and duty factor. the period and duty factor of the output pulse can be calculated by the following expressions. pulse period = {set value of tdr0n (master) + 1} count clock period duty factor [%] = {set value of tdr0m (s lave)}/{set value of tdr0n (master) + 1} 100 0% output: set value of tdr0m (slave) = 0000h 100% output: set value of tdr0m (slave) {set value of tdr0n (master) + 1} remark the duty factor exceeds 100% if the set value of tdr0m (slave) > (set value of tdr0n (master) + 1), it summarizes to 100% output. the master channel operates in the interval timer m ode and counts the periods. when the channel start trigger (ts0n) is set to 1, inttm0n is output. tcr0n coun ts down starting from the l oaded value of tdr0n, in synchronization with the count clock. when tcr0n = 0000h , inttm0n is output. tcr0n loads the value of tdr0n again. after that, it conti nues the similar operation. tcr0m of a slave channel operates in one-count mode, counts the duty fact or, and outputs a pwm waveform from the to0m pin. tcr0m of the slave c hannel loads the value of tdr0m, usi ng inttm0n of the master channel as a start trigger, and stops counting until the next start trigger (inttm0n of the master channel) is input. the output level of to0m bec omes active one count clock after generat ion of inttm0n from the master channel, and inactive when tcr0m = 0000h. caution to rewrite both tdr0n of the master channe l and tdr0m of the slave channel, a write access is necessary two times. the timing at which the values of t dr0n and tdr0m are loaded to tcr0n and trc0m is upon occurrence of inttm0n of the master channel. thus, when rewriting is performed split before and after occurrence of inttm0n of the master channel, the to0m pin cannot output the expected waveform. to rewrit e both tdr0n of the master and tdr0m of the slave, therefore, be sure to rewrite both the registers immediately after inttm0n is generated from the master channel. remark n = 0, 2, 4, 6 m = n + 1 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 277 figure 6-55. block diagram of operation as pwm function timer counter (tcr0n) interrupt signal (inttm0n) data register (tdr0n) interrupt controller clock selection trigger selection operation clock ck00 ck01 ts0n timer counter (tcr0m) interrupt signal (inttm0m) data register (tdr0m) interrupt controller clock selection trigger selection operation clock ck00 ck01 to0m pin output controller master channel (interval timer mode) slave channel (one-count mode) remark n = 0, 2, 4, 6 m = n + 1 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 278 figure 6-56. example of basic ti ming of operation as pwm function ts0n te0n tdr0n tcr0n to0n inttm0n a b 0000h ts0m te0m tdr0m tcr0m to0m inttm0m c c d 0000h c d master channel slave channel a+1 a+1 b+1 ffffh ffffh remark n = 0, 2, 4, 6 m = n + 1 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 279 figure 6-57. example of set contents of register s when pwm function (master channel) is used (a) timer mode register 0n (tmr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks0n 1/0 0 0 ccs0n 0 mas ter0n 1 sts0n2 0 sts0n1 0 sts0n0 0 cis0n1 0 cis0n0 0 0 0 md0n3 0 md0n2 0 md0n1 0 md0n0 1 operation mode of channel n 000b: interval timer setting of operation when counting is started 1: generates inttm0n when counting is started. selection of ti0n pin input edge 00b: sets 00b because these are not used. start trigger selection 000b: selects only software start. slave/master selection 1: channel 1 is set as master channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel n. 1: selects ck01 as operation clock of channel n. (b) timer output register 0 (to0) bit n to0 to0n 0 0: outputs 0 from to0n. (c) timer output enable register 0 (toe0) bit n toe0 toe0n 0 0: stops the to0n output operation by counting operation. (d) timer output level register 0 (tol0) bit n tol0 tol0n 0 0: cleared to 0 when tom0n = 0 (toggle mode). (e) timer output mode register 0 (tom0) bit n tom0 tom0n 0 0: sets toggle mode. remark n = 0, 2, 4, 6 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 280 figure 6-58. example of set contents of regist ers when pwm function (slave channel) is used (a) timer mode register 0m (tmr0m) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0m cks0m 1/0 0 0 ccs0m 0 mas ter0 m 0 sts0m2 1 sts0m1 0 sts0m0 0 cis0m1 0 cis0m0 0 0 0 md0m3 1 md0m2 0 md0m1 0 md0m0 1 operation mode of channel m 100b: one-count mode start trigger during operation 1: trigger input is valid. selection of ti0m pin input edge 00b: sets 00b because these are not used. start trigger selection 100b: selects inttm0n of master channel. slave/master selection 0: channel 0 is set as slave channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel m. 1: selects ck01 as operation clock of channel m. * make the same setting as master channel. (b) timer output register 0 (to0) bit m to0 to0m 1/0 0: outputs 0 from to0m. 1: outputs 1 from to0m. (c) timer output enable register 0 (toe0) bit m toe0 toe0m 1/0 0: stops the to0m output operation by counting operation. 1: enables the to0m output operation by counting operation. (d) timer output level register 0 (tol0) bit m tol0 tol0m 1/0 0: positive logic output (active-high) 1: inverted output (active-low) (e) timer output mode register 0 (tom0) bit m tom0 tom0m 1 1: sets the combination-operation mode. remark n = 0, 2, 4, 6 m = n + 1 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 281 figure 6-59. operation procedure wh en pwm function is used (1/2) software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per2 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) taus default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. sets the tmr0n and tmr0m registers of two channels to be used (determines oper ation mode of channels). an interval (period) value is set to the tdr0n register of the master channel, and a duty factor is set to the tdr0m register of the slave channel. channel stops operating. (clock is supplied and some power is consumed.) channel default setting sets slave channel. the tom0m bit of the tom0 register is set to 1 (combination-operation mode). sets the tol0m bit. sets the to0m bit and determines default level of the to0m output. sets toe0m to 1 and enables operation of to0m. clears the port register and port mode register to 0. the to0m pin goes into hi-z output state. the to0m default setting level is output when the port mode register is in output mode and the port register is 0. to0m does not change because channel stops operating. the to0m pin outputs the to0m set level. remark n = 0, 2, 4, 6 m = n + 1 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 282 figure 6-59. operation procedure wh en pwm function is used (2/2) software operation hardware status operation start sets toe0m (slave) to 1 (only when operation is resumed). the ts0n (master) and ts0m (slave) bits of the ts0 register are set to 1 at the same time. the ts0n and ts0m bits automatically return to 0 because they are trigger bits. te0n = 1, te0m = 1 when the master channel starts counting, inttm0n is generated. triggered by this interrupt, the slave channel also starts counting. during operation set values of the tmr0n and tmr0m registers cannot be changed. set values of the tdr0n and tdr0m registers can be changed after inttm0n of the master channel is generated. the tcr0n and tcr0m registers can always be read. the tsr0n and tsr0m registers are not used. set values of the tol0, to0, and toe0 registers cannot be changed. the counter of the master channel loads the tdr0n value to tcr0n, and counts down. when the count value reaches tcr0n = 0000h, inttm0n output is generated. at the same time, the value of the tdr0n register is loaded to tcr0n, and the counter starts counting down again. at the slave channel, the value of tdr0m is loaded to tcr0m, triggered by inttm0n of the master channel, and the counter starts counting down. the output level of to0m becomes active one c ount clock after generation of the inttm0n output from the master channel. it becomes inactive when tcr0m = 0000h, and the counting operation is stopped. after that, the above operation is repeated. the tt0n (master) and tt0m (slave) bits are set to 1 at the same time. the tt0n and tt0m bits automatically return to 0 because they are trigger bits. te0n, te0m = 0, and count operation stops. tcr0n and tcr0m hold count value and stops. the to0m output is not initialized but holds current status. operation stop toe0m of slave channel is cleared to 0 and value is set to the to0m bit. the to0m pin outputs the to0m set level. to hold the to0m pin output levels clears to0m bit to 0 after the value to be held is set to the port register. when holding the to0m pin output levels is not necessary switches the port mode register to input mode. the to0m pin output levels is held by port function. the to0m pin output levels go are into hi-z output state. taus stop the tau0en bit of the per2 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. (the to0m bit is cleared to 0 and the to0m pin is set to port mode.) remark n = 0, 2, 4, 6 m = n + 1 operation is resumed. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 283 6.8.2 operation as one-shot pulse output function by using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input to the ti0n pin. the delay time and pulse width can be ca lculated by the following expressions. delay time = {set value of tdr0n (master) + 2} count clock period pulse width = {set value of tdr0m (slave)} count clock period the master channel operates in the one-count mode and counts the delays. tcr0n of the master channel starts operating upon start trigger detection and tcr0n loads the value of tdr0n. tcr0n counts down from the value of tdr0n it has loaded, in synchronization with the count clock. when tcr0n = 0000h, it outputs inttm0n and stops counting until the next start trigger is detected. the slave channel operates in the one-co unt mode and counts the pulse width. tcr0m of the slave channel starts operation using inttm0n of the master channel as a start trigger, and loads t he tdr0m value. tcr0m counts down from the value of tdr0m it has load ed, in synchronization with the count value. when tcr0m = 0000h, it outputs inttm0m and stops counting until the next start trigger (inttm0n of the master channel) is detected. the output level of to0m becomes active one count clock after genera tion of inttm0n from the master channel, and inactive when tcr0m = 0000h. instead of using the ti0n pin input, a one- shot pulse can also be output using the software operation (ts0n = 1) as a start trigger. caution the timing of loading of tdr0n of the master channel is different from that of tdr0m of the slave channel. if tdr0n and tdr0m are rewritten during opera tion, therefore, an illegal waveform is output. be sure to rewrite tdr0n and tdr0m af ter inttm0n of the channe l to be rewritten is generated. remark n = 0, 2, 4, 6 m = n + 1 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 284 figure 6-60. block diagram of operat ion as one-shot pulse output function timer counter (tcr0n) interrupt signal (inttm0n) data register (tdr0n) interrupt controller clock selection trigger selection operation clock ck00 ck01 ts0n timer counter (tcr0m) interrupt signal (inttm0m) data register (tdr0m) interrupt controller clock selection trigger selection operation clock ck00 ck01 to0m pin output controller master channel (one-count mode) slave channel (one-count mode) edge detection ti0n pin remark n = 0, 2, 4, 6 m = n + 1 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 285 figure 6-61. example of basic timing of operation as one-shot pulse output function te0n tdr0n tcr0n to0n inttm0n a b 0000h ts0m te0m tdr0m tcr0m to0m inttm0m 0000h b master channel slave channel a+2 b a+2 ffffh ffffh ti0n ts0n remark n = 0, 2, 4, 6 m = n + 1 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 286 figure 6-62. example of set contents of registers when one-shot pulse output func tion is used (master channel) (a) timer mode register 0n (tmr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks0n 1/0 0 0 ccs0n 0 mas ter0n 1 sts0n2 0 sts0n1 0 sts0n0 1 cis0n1 1/0 cis0n0 1/0 0 0 md0n3 1 md0n2 0 md0n1 0 md0n0 0 operation mode of channel n 100b: one-count mode start trigger during operation 0: trigger input is invalid. selection of ti0n pin input edge 00b: detects falling edge. 01b: detects rising edge. 10b: detects both edges. 11b: setting prohibited start trigger selection 001b: selects the ti0n pin input valid edge. slave/master selection 1: channel 1 is set as master channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channels n. 1: selects ck01 as operation clock of channels n. (b) timer output register 0 (to0) bit n to0 to0n 0 0: outputs 0 from to0n. (c) timer output enable register 0 (toe0) bit n toe0 toe0n 0 0: stops the to0n output operation by counting operation. (d) timer output level register 0 (tol0) bit n tol0 tol0n 0 0: cleared to 0 when tom0n = 0 (toggle mode). (e) timer output mode register 0 (tom0) bit n tom0 tom0n 0 0: sets toggle mode. remark n = 0, 2, 4, 6 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 287 figure 6-63. example of set contents of registers when one-shot pulse output func tion is used (slave channel) (a) timer mode register 0m (tmr0m) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0m cks0m 1/0 0 0 ccs0m 0 mas ter0 m 0 sts0m2 1 sts0m1 0 sts0m0 0 cis0m1 0 cis0m0 0 0 0 md0m3 1 md0m2 0 md0m1 0 md0m0 0 operation mode of channel m 100b: one-count mode start trigger during operation 0: trigger input is invalid. selection of ti0m pin input edge 00b: sets 00b because these are not used. start trigger selection 100b: selects inttm0n of master channel. slave/master selection 0: channel 0 is set as slave channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel m. 1: selects ck01 as operation clock of channel m. * make the same setting as master channel. (b) timer output register 0 (to0) bit m to0 to0m 1/0 0: outputs 0 from to0m. 1: outputs 1 from to0m. (c) timer output enable register 0 (toe0) bit m toe0 toe0m 1/0 0: stops the to0m output operation by counting operation. 1: enables the to0m output operation by counting operation. (d) timer output level register 0 (tol0) bit m tol0 tol0m 1/0 0: positive logic output (active-high) 1: inverted output (active-low) (e) timer output mode register 0 (tom0) bit m tom0 tom0m 1 1: sets the combination-operation mode. remark n = 0, 2, 4, 6 m = n + 1 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 288 figure 6-64. operation procedure of one-shot pulse output function (1/2) software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per2 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) taus default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. sets the tmr0n and tmr0m registers of two channels to be used (determines oper ation mode of channels). an output delay is set to the tdr0n register of the master channel, and a pulse width is set to the tdr0m register of the slave channel. channel stops operating. (clock is supplied and some power is consumed.) channel default setting sets slave channel. the tom0m bit of the tom0 register is set to 1 (combination-operation mode). sets the tol0m bit. sets the to0m bit and determines default level of the to0m output. sets toe0m to 1 and enables operation of to0m. clears the port register and port mode register to 0. the to0m pin goes into hi-z output state. the to0m default setting level is output when the port mode register is in output mode and the port register is 0. to0m does not change because channel stops operating. the to0m pin outputs the to0m set level. remark n = 0, 2, 4, 6 m = n + 1 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 289 figure 6-64. operation procedure of one-shot pulse output function (2/2) software operation hardware status sets toe0m (slave) to 1 (only when operation is resumed). the ts0n (master) and ts0m (slave) bits of the ts0 register are set to 1 at the same time. the ts0n and ts0m bits automatically return to 0 because they are trigger bits. te0n and te0m are set to 1 and the master channel enters the ti0n input edge detection wait status. counter stops operating. operation start detects the ti0n pin input valid edge of master channel. master channel starts counting. during operation set values of only the cis0n1 and cis0n0 bits of the tmr0n register can be changed. set values of the tmr0m, tdr0n, tdr0m, and tom0 registers cannot be changed. the tcr0n and tcr0m registers can always be read. the tsr0n and tsr0m registers are not used. set values of the tol0, to0, and toe0 registers can be changed. master channel loads the value of tdr0n to tcr0n when the ti0n pin valid input edge is detected, and the counter starts counting down. when the count value reaches tcr0n = 0000h, the inttm0n output is generated, and the counter stops until the next valid edge is input to the ti0n pin. the slave channel, triggered by inttm0n of the master channel, loads the value of tdr0m to tcr0m, and the counter starts counting down. the output level of to0m becomes active one count clock after generation of inttm0n from the master channel. it becomes inactive when tcr0m = 0000h, and the counting operation is stopped. after that, the above operation is repeated. the tt0n (master) and tt0m (slave) bits are set to 1 at the same time. the tt0n and tt0m bits automatically return to 0 because they are trigger bits. te0n, te0m = 0, and count operation stops. tcr0n and tcr0m hold count value and stops. the to0m output is not initialized but holds current status. operation stop toe0m of slave channel is cleared to 0 and value is set to the to0m bit. the to0m pin outputs the to0m set level. to hold the to0m pin output levels clears to0m bit to 0 after the value to be held is set to the port register. when holding the to0m pin output levels is not necessary switches the port mode register to input mode. the to0m pin output levels is held by port function. the to0m pin output levels go are into hi-z output state. taus stop the tau0en bit of the per2 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. (the to0m bit is cleared to 0 and the to0m pin is set to port mode.) remark n = 0, 2, 4, 6 m = n + 1 operation is resumed. chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 290 6.8.3 operation as multiple pwm output function by extending the pwm function and using two or more sl ave channels, many pwm output signals can be produced. for example, when using two slave channels, the period and duty factor of an output pu lse can be calculated by the following expressions. pulse period = {set value of tdr0n (master) + 1} count clock period duty factor 1 [%] = {set value of tdr0p (s lave 1)}/{set value of tdr0n (master) + 1} 100 duty factor 2 [%] = {set value of tdr0q (s lave 2)}/{set value of tdr0n (master) + 1} 100 remark although the duty factor exceeds 100% if the set value of tdr0p (slave 1) > {set value of tdr0n (master) + 1} or if the {set value of tdr0q (slave 2)} > {set value of tdr0n (master) + 1}, it is summarized into 100% output. tcr0n of the master channel operates in the interval timer mode and counts the periods. tcr0p of the slave channel 1 operates in one-count mode, counts the du ty factor, and outputs a pwm waveform from the to0p pin. tcr0p l oads the value of tdr0p to tcr0p, using inttm0n of the master channel as a start trigger, and start counting down. when tcr0p = 0000h, tcr0p outputs inttm0p and st ops counting until the next start trigger (inttm0n of the master channel) has been i nput. the output level of to0p becomes active one count clock after generation of inttm0n from the ma ster channel, and inactive when tcr0p = 0000h. in the same way as tcr0p of the slave channel 1, t cr0q of the slave channel 2 operates in one-count mode, counts the duty factor, and outputs a pwm waveform from the to0q pin. tcr0q loads the value of tdr0q to tcr0q, using inttm0n of the master channel as a start tri gger, and starts counting down. when tcr0q = 0000h, tcr0q outputs inttm0q and stops counting until th e next start trigger (inttm0n of the master channel) has been input. the output level of to0q becomes active one count clock after generation of in ttm0n from the master channel, and inactive when tcr0q = 0000h. when channel 0 is used as the master channel as above, up to seven types of pwm signals can be output at the same time. caution to rewrite both tdr0n of the master channe l and tdr0p of the slave channel 1, write access is necessary at least twice. sin ce the values of tdr0n and tdr0p are loaded to tcr0n and tcr0p after inttm0n is generated from th e master channel, if rewriting is performed separately before and after generation of inttm0n from the mast er channel, the to0p pin cannot output the expected waveform. to rewrite both tdr0n of th e master and tdr0p of the slave, be sure to rewrite both the registers immediately after inttm0n is generated from th e master channel (this applies also to tdr0q of the slave channel 2) . remark n = 0, 2, 4 n < p < q 7 where p and q are consecutive integers following n (p = n + 1, q = n + 2) chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 291 figure 6-65. block diagram of operation as multiple pwm output function (output two types of pwms) timer counter (tcr0n) interrupt signal (inttm0n) data register (tdr0n) interrupt controller clock selection trigger selection operation clock ck00 ck01 ts0n timer counter (tcr0p) interrupt signal (inttm0p) data register (tdr0p) interrupt controller clock selection trigger selection operation clock ck00 ck01 to0p pin output controller master channel (interval timer mode) slave channel 1 (one-count mode) timer counter (tcr0q) interrupt signal (inttm0q) data register (tdr0q) interrupt controller clock selection trigger selection operation clock ck00 ck01 to0q pin output controller slave channel 2 (one-count mode) remarks 1. n = 0, 2, 4 2. p = n + 1 q = n + 2 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 292 figure 6-66. example of basic timing of operation as mu ltiple pwm output function (output two types of pwms) ts0n te0n tdr0n tcr0n to0n inttm0n a b 0000h ts0p te0p tdr0p tcr0p to0p inttm0p c c d 0000h c d master channel slave channel 1 a+1 a+1 b+1 ffffh ffffh ts0q te0q tdr0q tcr0q to0q inttm0q e f 0000h e f slave channel 2 a+1 a+1 b+1 ffffh e f d remarks 1. n = 0, 2, 4 2. p = n + 1 q = n + 2 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 293 figure 6-67. example of set contents of registers when multiple pwm output function (master channel) is used (a) timer mode register 0n (tmr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0n cks0n 1/0 0 0 ccs0n 0 mas ter0n 1 sts0n2 0 sts0n1 0 sts0n0 0 cis0n1 0 cis0n0 0 0 0 md0n3 0 md0n2 0 md0n1 0 md0n0 1 operation mode of channel n 000b: interval timer setting of operation when counting is started 1: generates inttm0n when counting is started. selection of ti0n pin input edge 00b: sets 00b because these are not used. start trigger selection 000b: selects only software start. slave/master selection 1: channel 1 is set as master channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel n. 1: selects ck01 as operation clock of channel n. (b) timer output register 0 (to0) bit n to0 to0n 0 0: outputs 0 from to0n. (c) timer output enable register 0 (toe0) bit n toe0 toe0n 0 0: stops the to0n output operation by counting operation. (d) timer output level register 0 (tol0) bit n tol0 tol0n 0 0: cleared to 0 when tom0n = 0 (toggle mode). (e) timer output mode register 0 (tom0) bit n tom0 tom0n 0 0: sets toggle mode. remark n = 0, 2, 4 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 294 figure 6-68. example of set contents of registers when multiple pwm output function (slave channel) is used (output two types of pwms) (a) timer mode register 0p, 0q (tmr0p, tmr0q) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0p cks0p 1/0 0 0 ccs0p 0 mas ter0p 0 sts0p2 1 sts0p1 0 sts0p0 0 cis0p1 0 cis0p0 0 0 0 md0p3 1 md0p2 0 md0p1 0 md0p0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr0q cks0q 1/0 0 0 ccs0q 0 mas ter0q 0 sts0q2 1 sts0q1 0 sts0q0 0 cis0q1 0 cis0q0 0 0 0 md0q3 1 md0q2 0 md0q1 0 md0q0 1 operation mode of channel p, q 100b: one-count mode start trigger during operation 1: trigger input is valid. selection of ti0p and ti0q pin input edge 00b: sets 00b because these are not used. start trigger selection 100b: selects inttm0n of master channel. slave/master selection 0: channel 0 is set as slave channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ck00 as operation clock of channel p, q. 1: selects ck01 as operation clock of channel p, q. * make the same setting as master channel. (b) timer output register 0 (to0) bit q bit p to0 to0q 1/0 to0p 1/0 0: outputs 0 from to0p or to0q. 1: outputs 1 from to0p or to0q. (c) timer output enable register 0 (toe0) bit q bit p toe0 toe0q 1/0 toe0p 1/0 0: stops the to0p or to0q output operation by counting operation. 1: enables the to0p or to0q output operation by counting operation. (d) timer output level register 0 (tol0) bit q bit p tol0 tol0q 1/0 tol0p 1/0 0: positive logic output (active-high) 1: inverted output (active-low) (e) timer output mode register 0 (tom0) bit q bit p tom0 tom0q 1 tom0p 1 1: sets the combination-operation mode. remark n = 0, 2, 4; p = n+1; q = n+2 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 295 figure 6-69. operation procedure when mult iple pwm output function is used (1/2) software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en bit of the per2 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) taus default setting sets the tps0 register. determines clock frequencies of ck00 and ck01. sets the tmr0n, tmr0p, and tmr0q registers of each channel to be used (determines operation mode of channels). an interval (period) value is set to the tdr0n register of the master channel, and a duty factor is set to the tdr0p and tdr0q registers of the slave channel. channel stops operating. (clock is supplied and some power is consumed.) channel default setting sets slave channel. the tom0p and tom0q bits of the tom0 register are set to 1 (combination-operation mode). clears the tol0p and tol0q bits to 0. sets the to0p and to0q bits and determines default level of the to0p and to0q outputs. sets toe0p or toe0q to 1 and enables operation of to0p and to0q. clears the port register and port mode register to 0. the to0p and to0q pins go into hi-z output state. the to0p and to0q default setting levels are output when the port mode register is in output mode and the port register is 0. to0p or to0q does not change because channel stops operating. the to0p and to0q pins output the to0p and to0q set levels. remarks 1. n = 0, 2, 4 2. p = n + 1; q = n + 2 chapter 6 timer array unit taus preliminary user?s manual u19291ej1v0ud 296 figure 6-69. operation procedure when mult iple pwm output function is used (2/2) software operation hardware status operation start sets toe0p and toe0q (slave) to 1 (only when operation is resumed). the ts0n bit (master), and ts0p and ts0q (slave) bits of the ts0 register are set to 1 at the same time. the ts0n, ts0p, and ts0q bits automatically return to 0 because they are trigger bits. te0n = 1, te0p, te0q = 1 when the master channel starts counting, inttm0n is generated. triggered by this interrupt, the slave channel also starts counting. during operation set values of the tmr0n, tmr0p, tmr0q, tom0, and toe0 registers cannot be changed. set values of the tdr0n, tdr0p, and tdr0q registers can be changed after inttm0n of the master channel is generated. the tcr0n, tcr0p, and tcr0q registers can always be read. the tsr0n, tsr0p, and tsr 0q registers are not used. set values of the tom0, tol0, to0, and toe0 registers can be changed. the counter of the master channel loads the tdr0n value to tcr0n and counts down. when the count value reaches tcr0n = 0000h, inttm0n output is generated. at the same time, the value of the tdr0n register is loaded to tcr0n, and the counter starts counting down again. at the slave channel 1, the values of tdr0p are transferred to tcr0p, triggered by inttm0n of the master channel, and the counter starts counting down. the output levels of to0p become active one count clock after generation of the inttm0n output from the master channel. it becomes inactive when tcr0p = 0000h, and the counting operation is stopped. at the slave channel 2, the values of tdr0q are transferred to tdr0q, triggered by inttm0n of the master channel, and the counter starts counting down. the output levels of to0q become active one count clock after generation of the inttm0n output from the master channel. it becomes inactive when tcr0q = 0000h, and the counting operation is stopped. after that, the above operation is repeated. the tt0n bit (master), tt0p, and tt0q (slave) bits are set to 1 at the same time. the tt0n, tt0p, and tt0q bits automatically return to 0 because they are trigger bits. te0n, te0p, te0q = 0, and count operation stops. tcr0n, tcr0p, and tcr0q hold count value and stops. the to0p and to0q output is not initialized but holds current status. operation stop toe0p or toe0q of slave channel is cleared to 0 and value is set to the to0p and to0q bits. the to0p and to0q pins output the to0p and to0q set levels. to hold the to0p and to0q pin output levels clears to0p and to0q bits to 0 after the value to be held is set to the port register. when holding the to0p and to0q pin output levels is not necessary switches the port mode register to input mode. the to0p and to0q pin output levels are held by port function. the to0p and to0q pin output levels go into hi-z output state. taus stop the tau0en bit of the per2 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. (the to0p and to0q bits are cleared to 0 and the to0p and to0q pins are set to port mode.) remarks 1. n = 0, 2, 4 2. p = n + 1; q = n + 2 operation is resumed. preliminary user?s manual u19291ej1v0ud 297 chapter 7 real-time counter 7.1 functions of real-time counter the real-time counter ha s the following features. ? having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years. ? constant-period interrupt function (period: 1 month to 0.5 seconds) ? alarm interrupt function (alarm: week, hour, minute) ? interval interrupt function ? pin output function of 1 hz ? pin output function of 512 hz or 16.384 khz or 32.768 khz 7.2 configuration of real-time counter the real-time counter includes the following hardware. table 7-1. configuration of real-time counter item configuration peripheral enable register 0 (per0) real-time counter control register 0 (rtcc0) real-time counter control register 1 (rtcc1) real-time counter control register 2 (rtcc2) sub-count register (rsubc) second count register (sec) minute count register (min) hour count register (hour) day count register (day) week count register (week) month count register (month) year count register (year) watch error correction register (subcud) alarm minute register (alarmwm) alarm hour register (alarmwh) control registers alarm week register (alarmww) chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 298 figure 7-1. block diagra m of real-time counter intrtc f sub rtce rcloe1 rcloe0 ampm ct2 ct1 ct0 rinte rcloe2 ict2 ict1 ict0 rtce ampm ct0 to ct2 rckdiv f sub rtc1hz/ p52 rckdiv rinte rtcdiv/rtccl/p12 intrtci rcloe2 f sub rwait wale walie wafg rwait rwst rifg rwst rifg 12-bit counter real-time counter control register 1 real-time counter control register 0 alarm week register (alarmww) (7-bit) alarm hour register (alarmwh) (6-bit) alarm minute register (alarmwm) (7-bit) year count register (year) (8-bit) month count register (month) (5-bit) week count register (week) (3-bit) day count register (day) (6-bit) hour count register (hour) (6-bit) minute count register (min) (7-bit) second count register (sec) (7-bit) wait control 0.5 seconds sub-count register (rsubc) (16-bit) count clock = 32.768 khz selector buffer buffer buffer buffer buffer buffer buffer count enable/ disable circuit watch error correction register (subcud) (8-bit) selector selector internal bus real-time counter control register 2 1 month 1 day 1 hour 1 minute chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 299 7.3 registers controlling real-time counter the real-time counter is controlle d by the following 16 registers. ? peripheral enable register 0 (per0) ? real-time counter control register 0 (rtcc0) ? real-time counter control register 1 (rtcc1) ? real-time counter control register 2 (rtcc2) ? sub-count register (rsubc) ? second count register (sec) ? minute count register (min) ? hour count register (hour) ? day count register (day) ? week count register (week) ? month count register (month) ? year count register (year) ? watch error correction register (subcud) ? alarm minute register (alarmwm) ? alarm hour register (alarmwh) ? alarm week register (alarmww) chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 300 (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripheral hardware macro. clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. when the real-time counter is used, be sure to set bit 7 (rtcen) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-2. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> 6 <5> <4> 3 <2> 1 0 per0 rtcen 0 adcen iicaen 0 sau0en 0 0 rtcen control of real-time count er (rtc) input clock supply note 0 stops supply of input clock. ? sfr used by the real-time counter (rtc) cannot be written. ? the real-time counter (rtc) is in the reset status. 1 supplies input clock. ? sfr used by the real-time counter (rtc) can be read/written. note the input clock that can be controlled by rtce n is used when the register that is used by the real-time counter (rtc) is accessed from the cpu. rtcen cannot control supply of the operating clock (f sub ) to rtc. cautions 1. when using the real-time counter, first set rtcen to 1, while oscillation of the subsystem clock (f sub ) is stable. if rtcen = 0, writing to a control register of the real-time counter is ignored, and, even if the register is read, only the default value is read. 2. clock supply to peripheral functions other than the real-time counter can be stopped in halt mode when the subsystem clock is used, by setting rtclpc of the operation speed mode control register (osmc) to 1. in that case, set rtcen to 1 and bits 0 to 6 of per0 to 0. fur thermore, set bits 0 to 7 of the per1 and per2 registers also to 0. 3. be sure to clear bits 0, 1, 3, and 6 (44-pin products: bits 0, 1, 3, 4, and 6) of the per0 register to 0. (2) real-time counter cont rol register 0 (rtcc0) the rtcc0 register is an 8-bit register that is used to start or stop the real-time co unter operation, control the rtccl and rtc1hz pins, and set a 12- or 24-hour system and the constant-per iod interrupt function. rtcc0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 301 figure 7-3. format of real-time c ounter control register 0 (rtcc0) address: fff9dh after reset: 00h r/w symbol <7> 6 <5> <4> 3 2 1 0 rtcc0 rtce 0 rcloe1 rcloe0 ampm ct2 ct1 ct0 rtce real-time counter operation control 0 stops counter operation. 1 starts counter operation. rcloe1 rtc1hz pin output control 0 disables output of rtc1hz pin (1 hz). 1 enables output of rtc1hz pin (1 hz). rcloe0 note rtccl pin output control 0 disables output of rtccl pin (32.768 khz). 1 enables output of rtccl pin (32.768 khz). ampm selection of 12-/24-hour system 0 12-hour system (a.m. and p.m. are displayed.) 1 24-hour system ? to change the value of ampm, set rwait (bit 0 of rtcc 1) to 1, and re-set the hour count register (hour). ? table 7-2 shows the displayed ti me digits that are displayed. ct2 ct1 ct0 constant-period interrupt (intrtc) selection 0 0 0 does not use constant-period interrupt function. 0 0 1 once per 0.5 s (synchronized with second count up) 0 1 0 once per 1 s (same time as second count up) 0 1 1 once per 1 m (second 00 of every minute) 1 0 0 once per 1 hour (minute 00 and second 00 of every hour) 1 0 1 once per 1 day (hour 00, minute 00, and second 00 of every day) 1 1 once per 1 month (day 1, hour 00 a.m., minute 00, and second 00 of every month) after changing the values of ct2 to ct0, clear the interrupt request flag. note rcloe0 and rcloe2 must not be enabled at the same time. caution if rcloe0 and rcloe1 are changed when rt ce = 1, the last wavef orm of the 32.768 khz and 1 hz output signals may become short. remark : don?t care chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 302 (3) real-time counter cont rol register 1 (rtcc1) the rtcc1 register is an 8-bit regist er that is used to control the alarm interrupt function and the wait time of the counter. rtcc1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-4. format of real-time count er control register 1 (rtcc1) (1/2) address: fff9eh after reset: 00h r/w symbol <7> <6> 5 <4> <3> 2 <1> <0> rtcc1 wale walie 0 wafg rifg 0 rwst rwait wale alarm operation control 0 match operation is invalid. 1 match operation is valid. to set the registers of alarm (walie flag of rt cc1, alarmwm register, alarmwh register, and alarmww register), disable wale (clear it to ?0?). walie control of alarm interrupt (intrtc) function operation 0 does not generate interrupt on matching of alarm. 1 generates interrupt on matching of alarm. wafg alarm detection status flag 0 alarm mismatch 1 detection of matching of alarm this is a status flag that indicates detection of matching wi th the alarm. it is valid only when wale = 1 and is set to ?1? one clock (32.768 khz) after matching of the alarm is detec ted. this flag is cleared w hen ?0? is written to it. writing ?1? to it is invalid. chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 303 figure 7-4. format of real-time count er control register 1 (rtcc1) (2/2) rifg constant-period interrupt status flag 0 constant-period interrupt is not generated. 1 constant-period interrupt is generated. this flag indicates the status of generation of the const ant-period interrupt. when the constant-period interrupt is generated, it is set to ?1?. this flag is cleared when ?0? is written to it. writing ?1? to it is invalid. rwst wait status flag of real-time counter 0 counter is operating. 1 mode to read or write counter value this status flag indicates whether the setting of rwait is valid. before reading or writing the counter value, confirm that the value of this flag is 1. rwait wait control of real-time counter 0 sets counter operation. 1 stops sec to year counters. mode to read or write counter value this bit controls the operation of the counter. be sure to write ?1? to it to read or write the counter value. because rsubc continues operation, complete reading or writ ing of it in 1 second, and clear this bit back to 0. when rwait = 1, it takes up to 1 clock (32.768 khz) until the counter value can be read or written. if rsubc overflows when rwait = 1, it counts up after rwai t = 0. if the second count register is written, however, it does not count up because rsubc is cleared. caution if writing is performed to the rtcc1 regist er with a 1-bit manipulati on instruction, the rifg flag and wafg flag may be cleared. therefore, to perform writing to the rtcc1 register, be sure to use an 8-bit manipulati on instruction. to prevent the ri fg flag and wafg flag from being cleared during writing, disable writing by se tting 1 to the corresponding bit. if the rifg flag and wafg flag are not used and the value may be changed, the rtcc1 register may be written by using a 1-bit manipulation instruction. remark fixed-cycle interrupts and alarm match interrupts use the same interrupt source (intrtc). when using these two types of interrupt s at the same time, which interrupt occurred can be judged by checking the fixed-cycle interrupt status flag (r ifg) and the alarm detecti on status flag (wafg) upon intrtc occurrence. chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 304 (4) real-time counter cont rol register 2 (rtcc2) the rtcc2 register is an 8-bit register that is used to control the interval interrupt function and the rtcdiv pin. rtcc2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-5. format of real-time c ounter control register 2 (rtcc2) address: fff9fh after reset: 00h r/w symbol <7> <6> <5> 4 3 2 1 0 rtcc2 rinte rcloe2 rckdiv 0 0 ict2 ict1 ict0 rinte ict2 ict1 ict0 interval interrupt (intrtci) selection 0 interval interrupt is not generated. 1 0 0 0 2 6 /f xt (1.953125 ms) 1 0 0 1 2 7 /f xt (3.90625 ms) 1 0 1 0 2 8 /f xt (7.8125 ms) 1 0 1 1 2 9 /f xt (15.625 ms) 1 1 0 0 2 10 /f xt (31.25 ms) 1 1 0 1 2 11 /f xt (62.5 ms) 1 1 1 2 12 /f xt (125 ms) rcloe2 note rtcdiv pin output control 0 output of rtcdiv pin is disabled. 1 output of rtcdiv pin is enabled. rckdiv selection of rtcdiv pin output frequency 0 rtcdiv pin outputs 512 hz. (1.95 ms) 1 rtcdiv pin outputs 16.384 khz. (0.061 ms) notes rcloe0 and rcloe2 must not be enabled at the same time. cautions 1. change ict2, ict1, and ict0 when rinte = 0. 2. when the output from rtcdiv pin is stoppe d, the output continu es after a maximum of two clocks of f xt and enters the low level. while 512 hz is output, and when the output is stopped immediately after entering the high leve l, a pulse of at least one clock width of f xt may be generated. chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 305 (5) sub-count re gister (rsubc) the rsubc register is a 16-bit regist er that counts the reference time of 1 second of the real-time counter. normally, it takes a value of 0000h to 7fffh and counts 1 second with a clock of 32.768 khz. rsubc can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. cautions 1. when a correction is made by using the subcud regi ster, the value may become 8000h or more. 2. this register is also cl eared by reset effected by wr iting the second count register. 3. the value read from this register is not guar anteed if it is read du ring operation, because a value that is changing is read. figure 7-6. format of sub-count register (rsubc) address: fff90h after reset: 0000h r symbol 7 6 5 4 3 2 1 0 rsubc subc7 subc6 subc5 subc4 subc3 subc2 subc1 subc0 address: fff91h after reset: 0000h r symbol 7 6 5 4 3 2 1 0 rsubc subc15 subc14 subc13 subc12 subc11 subc10 subc9 subc8 (6) second count register (sec) the sec register is an 8-bit register that takes a value of 0 to 59 (dec imal) and indicates the count value of seconds. it counts up when the sub-counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 59 to this register in bcd code. sec can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-7. format of second count register (sec) address: fff92h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 sec 0 sec40 sec20 sec10 sec8 sec4 sec2 sec1 chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 306 (7) minute count register (min) the min register is an 8-bit register that takes a valu e of 0 to 59 (decimal) and indicates the count value of minutes. it counts up when the second counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 59 to this register in bcd code. min can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-8. format of minute count register (min) address: fff93h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 min 0 min40 min20 min10 min8 min4 min2 min1 (8) hour count register (hour) the hour register is an 8-bit register that takes a va lue of 00 to 23 or 01 to 12, 21 to 32 (decimal) and indicates the count value of hours. it counts up when the minute counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in bcd code. hour can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 12h. however, the value of this register is 00h if the ampm bit (bit 3 of the rtcc0 regist er) is set to 1 after reset. figure 7-9. format of hour count register (hour) address: fff94h after reset: 12h r/w symbol 7 6 5 4 3 2 1 0 hour 0 0 hour20 hour10 ho ur8 hour4 hour2 hour1 caution bit 5 (hour20) of ho ur indicates am(0)/pm(1) if ampm = 0 (if the 12-hour system is selected). chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 307 table 7-2 shows the relationship between the setting valu e of the ampm bit, the hour register value, and time. table 7-2. displayed time digits 24-hour display (ampm bit = 1) 12-hour display (ampm bit = 1) time hour register time hour register 0 00h 0 a.m. 12h 1 01h 1 a.m. 01h 2 02h 2 a.m. 02h 3 03h 3 a.m. 03h 4 04h 4 a.m. 04h 5 05h 5 a.m. 05h 6 06h 6 a.m. 06h 7 07h 7 a.m. 07h 8 08h 8 a.m. 08h 9 09h 9 a.m. 09h 10 10h 10 a.m. 10h 11 11h 11 a.m. 11h 12 12h 0 p.m. 32h 13 13h 1 p.m. 21h 14 14h 2 p.m. 22h 15 15h 3 p.m. 23h 16 16h 4 p.m. 24h 17 17h 5 p.m. 25h 18 18h 6 p.m. 26h 19 19h 7 p.m. 27h 20 20h 8 p.m. 28h 21 21h 9 p.m. 29h 22 22h 10 p.m. 30h 23 23h 11 p.m. 31h the hour register value is set to 12-hour display when the ampm bit is ?0? and to 24-hour display when the ampm bit is ?1?. in 12-hour display, the fifth bit of the ho ur register displays 0 for am and 1 for pm. chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 308 (9) day count register (day) the day register is an 8-bit register that takes a value of 1 to 31 (dec imal) and indicates the count value of days. it counts up when the hour counter overflows. this counter counts as follows. ? 01 to 31 (january, march, may, july, august, october, december) ? 01 to 30 (april, june, september, november) ? 01 to 29 (february, leap year) ? 01 to 28 (february, normal year) when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 01 to 31 to this register in bcd code. day can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 01h. figure 7-10. format of day count register (day) address: fff96h after reset: 01h r/w symbol 7 6 5 4 3 2 1 0 day 0 0 day20 day10 day8 day4 day2 day1 chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 309 (10) week count register (week) the week register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of weekdays. it counts up in synchronization with the day counter. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 06 to this register in bcd code. week can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-11. format of week count register (week) address: fff95h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 week 0 0 0 0 0 week4 week2 week1 caution the value corresponding to th e month count register or the day count register is not stored in the week count register auto matically. after reset release, se t the week count register as follow. day week sunday 00h monday 01h tuesday 02h wednesday 03h thursday 04h friday 05h saturday 06h chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 310 (11) month count register (month) the month register is an 8-bit regist er that takes a value of 1 to 12 (decimal) and indicates the count value of months. it counts up when the day counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 01 to 12 to this register in bcd code. month can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 01h. figure 7-12. format of month count register (month) address: fff97h after reset: 01h r/w symbol 7 6 5 4 3 2 1 0 month 0 0 0 month10 month8 month4 month2 month1 (12) year count register (year) the year register is an 8-bit register that takes a value of 0 to 99 (dec imal) and indicates the count value of years. it counts up when the month counter overflows. values 00, 04, 08, ?, 92, and 96 indicate a leap year. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 99 to this register in bcd code. year can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-13. format of year count register (year) address: fff98h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 year year80 year40 year20 year10 year8 year4 year2 year1 chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 311 (13) watch error correction register (subcud) this register is used to correct the watch with high accura cy when it is slow or fast by changing the value that overflows from the sub-count register (rsubc) to t he second count register (reference value: 7fffh). subcud can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-14. format of watch e rror correction register (subcud) address: fff99h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 subcud dev f6 f5 f4 f3 f2 f1 f0 dev setting of watch error correction timing 0 corrects watch error when the second digits are at 00, 20, or 40 (every 20 seconds). 1 corrects watch error only when the second digits are at 00 (every 60 seconds). f6 setting of watch error correction value 0 increases by {(f5, f4, f3, f2, f1, f0) ? 1} 2. 1 decreases by {(/f5, /f4, /f3, /f2, /f1, /f0) + 1} 2. when (f6, f5, f4, f3, f2, f1, f0) = (*, 0, 0, 0, 0, 0, *), the watch error is not corrected. * is 0 or 1. /f5 to /f0 are the inverted values of the corresponding bits (000011 when 111100). range of correction value: (when f6 = 0) 2, 4, 6, 8, ? , 120, 122, 124 (when f6 = 1) ?2, ?4, ?6, ?8, ? , ?120, ?122, ?124 the range of value that can be corre cted by using the watch error corre ction register (subcud) is shown below. dev = 0 (correction every 20 seconds) dev = 1 (correction every 60 seconds) correctable range ?189.2 ppm to 189.2 ppm ?63.1 ppm to 63.1 ppm maximum excludes quantization error 1.53 ppm 0.51 ppm minimum resolution 3.05 ppm 1.02 ppm remark if a correctable range is ? 63.1 ppm or lower and 63.1 ppm or higher, set 0 to dev. chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 312 (14) alarm minute register (alarmwm) this register is used to set minutes of alarm. alarmwm can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. caution set a decimal value of 00 to 59 to this register in bcd code. if a value outside the range is set, the alarm is not detected. figure 7-15. format of ala rm minute register (alarmwm) address: fff9ah after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 alarmwm 0 wm40 wm20 wm10 wm8 wm4 wm2 wm1 (15) alarm hour register (alarmwh) this register is used to set hours of alarm. alarmwh can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 12h. however, the value of this register is 00h if the ampm bit (bit 3 of the rtcc0 regist er) is set to 1 after reset. caution set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in bcd code. if a value outside the range is set, the alarm is not detected. figure 7-16. format of alarm hour register (alarmwh) address: fff9bh after reset: 12h r/w symbol 7 6 5 4 3 2 1 0 alarmwh 0 0 wh20 wh10 wh8 wh4 wh2 wh1 caution bit 5 (wh20) of alarmwh indicates am(0)/pm(1) if ampm = 0 (if the 12-hour system is selected). (16) alarm week register (alarmww) this register is used to set date of alarm. alarmww can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-17. format of alarm week register (alarmww) address: fff9ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 alarmww 0 ww6 ww5 ww4 ww3 ww2 ww1 ww0 chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 313 here is an example of setting the alarm. day 12-hour display 24-hour display time of alarm sunday w w 0 monday w w 1 tuesday w w 2 wednesday w w 3 thursday w w 4 friday w w 5 saturday w w 6 hour 10 hour 1 minute 10 minute 1 hour 10 hour 1 minute 10 minute 1 every day, 0:00 a.m. 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 every day, 1:30 a.m. 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 every day, 11:59 a.m. 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 monday through friday, 0:00 p.m. 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 sunday, 1:30 p.m. 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 monday, wednesday, friday, 11:59 p.m. 0 1 0 1 0 1 0 3 1 5 9 2 3 5 9 chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 314 7.4 real-time counter operation 7.4.1 starting operation of real-time counter figure 7-18. procedure for starting operation of real-time counter setting ampm, ct2 to ct0 setting min rtce = 0 setting sec (clearing rsubc) start intrtc = 1? stops counter operation. selects 12-/24-hour system and interrupt (intrtc). sets second count register. sets minute count register. no yes setting hour sets hour count register. setting week sets week count register. setting day sets day count register. setting month sets month count register. setting year sets year count register. clearing if flags of interrupt clears interrupt request flags (rtcif, rtciif). clearing mk flags of interrupt clears interrupt mask flags (rtcmk, rtcimk). rtce = 1 starts counter operation. reading counter rtcen = 1 note supplies input clock. note first set rtcen to 1, while o scillation of the subsystem clock (f sub ) is stable. chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 315 yes rtce = 1 rwait = 1 no yes rwait = 0 no rwst = 1 ? rwst = 0 ? stop mode rtce = 1 stop mode waiting at least for 2 f sub clocks sets to counter operation start shifts to stop mode sets to counter operation start sets to stop the sec to year counters, reads the counter value, write mode checks the counter wait status sets the counter operation shifts to stop mode 7.4.2 shifting to stop mode after starting operation perform one of the following processing when shifting to stop mode immediately after setting rtce to 1. however, after setting rtce to 1, this processing is not required when shifting to stop mode after the first intrtc interrupt has occurred. ? shifting to stop mode when at least two subsystem clocks (f sub ) (about 62 s) have elapsed after setting rtce to 1 (see figure 7-19 , example 1 ). ? checking by polling rwst to become 1, after setting rtce to 1 and then setting rwait to 1. afterward, setting rwait to 0 and shifting to stop mode after checki ng again by polling that rwst has become 0 (see figure 7- 19 , example 2 ). figure 7-19. procedure for shifting to stop mode after setting rtce to 1 chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 316 7.4.3 reading/writing real-time counter read or write the counter after setting 1 to rwait first. figure 7-20. procedure for reading real-time counter reading min rwait = 1 reading sec start rwst = 1? stops sec to year counters. mode to read and write count values reads second count register. reads minute count register. no yes reading hour reads hour count register. reading week reads week count register. reading day reads day count register. reading month reads month count register. reading year reads year count register. rwait = 0 rwst = 0? note no yes sets counter operation. checks wait status of counter. end note be sure to confirm that rwst = 0 before setting stop mode. caution complete the series of opera tions of setting rwait to 1 to cl earing rwait to 0 within 1 second. remark sec, min, hour, week, day, month, and year may be read in any sequence. all the registers do not have to be set and only some registers may be read. chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 317 figure 7-21. procedure for writing real-time counter writing min rwait = 1 writing sec start rwst = 1? stops sec to year counters. mode to read and write count values no yes writing hour writing week writing day writing month writing year rwait = 0 rwst = 0? note no yes sets counter operation. checks wait status of counter. end writes second count register. writes minute count register. writes hour count register. writes week count register. writes day count register. writes month count register. writes year count register. note be sure to confirm that rwst = 0 before setting stop mode. caution complete the series of opera tions of setting rwait to 1 to cl earing rwait to 0 within 1 second. remark sec, min, hour, week, day, month, a nd year may be written in any sequence. all the registers do not have to be set an d only some registers may be written. chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 318 7.4.4 setting alarm of real-time counter set time of alarm after setting 0 to wale first. figure 7-22. alarm setting procedure wale = 0 setting alarmwm start intrtc = 1? match operation of alarm is invalid. sets alarm minute register. alarm processing yes walie = 1 interrupt is generated when alarm matches. setting alarmwh sets alarm hour register. setting alarmww sets alarm week register. wale = 1 match operation of alarm is valid. wafg = 1? no yes constant-period interrupt servicing match detection of alarm no remarks 1. alarmwm, alarmwh, and alarmww may be written in any sequence. 2. fixed-cycle interrupts and alarm match interrupts use the same interrupt source (intrtc). when using these two types of interrupt s at the same time, which interrupt occurred can be judged by checking the fixed-cycle interrupt status flag (rif g) and the alarm detection status flag (wafg) upon intrtc occurrence. chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 319 7.4.5 1 hz output of real-time counter figure 7-23. 1 hz output setting procedure rtce = 0 rtce = 1 start stops counter operation. rcloe1 = 1 enables output of rtc1hz pin (1 hz). starts counter operation. output start from rtc1hz pin 7.4.6 32.768 khz output of real-time counter figure 7-24. 32.768 khz output setting procedure rtce = 0 rtce = 1 start stops counter operation. rcloe0 = 1 enables output of rtccl pin (32.768 khz). starts counter operation. 32.768 khz output start from rtccl pin 7.4.7 512 hz, 16.384 khz output of real-time counter figure 7-25. 512 hz, 16.384 khz output setting procedure rtce = 0 rtce = 1 start stops counter operation. rcloe2 = 1 output of rtcdiv pin is enabled. 512 hz output: rckdiv = 0 16.384 khz output: rckdiv = 1 selects output frequency of rtcdiv pin. starts counter operation. 512 hz or 16.384 khz output start from rtcdiv pin chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 320 7.4.8 example of watch error correction of real-time counter the watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction register. example of calculating the correction value the correction value used when correcting the count value of the sub-count register (rsubc) is calculated by using the following expression. set dev to 0 when the correction range is ? 63.1 ppm or less, or 63.1 ppm or more. (when dev = 0) correction value note = number of correction counts in 1 minute 3 = (oscillation frequency target frequency ? 1) 32768 60 3 (when dev = 1) correction value note = number of correction counts in 1 minute = (oscillation frequency target frequency ? 1) 32768 60 note the correction value is the watch error correction value calculated by using bits 6 to 0 of the watch error correction regist er (subcud). (when f6 = 0) correction value = {(f5, f4, f3, f2, f1, f0) ? 1} 2 (when f6 = 1) correction value = ? {(/f5, /f4, /f3, /f 2, /f1, /f0) + 1} 2 when (f6, f5, f4, f3, f2, f1, f0) is (*, 0, 0, 0, 0, 0, *), watch error correction is not performed. ?*? is 0 or 1. /f5 to /f0 are bit-inverted values (000011 when 111100). remarks 1. the correction value is 2, 4, 6, 8, ? 120, 122, 124 or ? 2, ? 4, ? 6, ? 8, ? ? 120, ? 122, ? 124. 2. the oscillation frequency is the subsystem clock (f sub ). it can be calculated from the 32 khz output frequency of the rtccl pin or the output frequency of the rtc1hz pin 32768 when the watch error correction register is set to its initial value (00h). 3. the target frequency is the frequency resulting a fter correction performed by using the watch error correction register. chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 321 correction example <1> example of correcting from 32772.3 hz to 32768 hz (32772.3 hz ? 131.2 ppm) [measuring the oscillation frequency] the oscillation frequency note of each product is measured by outputti ng about 32 khz from the rtccl pin or outputting about 1 hz from the rtc1hz pin when the watch erro r correction register is set to its initial value (00h). note see 7.4.5 1 hz output of real-time counter for the setting procedure of outputting about 1 hz from the rtc1hz pin, and 7.4.6 32.768 khz output of real-time counter for the setting procedure of outputting about 32 khz from the rtccl pin. [calculating the correction value] (when the output frequency from t he rtccl pin is 32772.3 hz) if the target frequency is assu med to be 32768 hz (32772.3 hz ? 131.2 ppm), the correction range for ? 131.2 ppm is ? 63.1 ppm or less, so assume dev to be 0. the expression for calculating the correct ion value when dev is 0 is applied. correction value = number of correction counts in 1 minute 3 = (oscillation frequency target frequency ? 1) 32768 60 3 = (32772.3 32768 ? 1) 32768 60 3 = 86 [calculating the values to be set to (f6 to f0)] (when the correction value is 86) if the correction value is 0 or more (w hen delaying), assume f6 to be 0. calculate (f5, f4, f3, f2, f1, f0) from the correction value. { (f5, f4, f3, f2, f1, f0) ? 1} 2 = 86 (f5, f4, f3, f2, f1, f0) = 44 (f5, f4, f3, f2, f1, f0) = (1, 0, 1, 1, 0, 0) consequently, when correcting from 32 772.3 hz to 32768 hz (32772.3 hz ? 131.2 ppm), setting the correction register such that dev is 0 and the correction value is 86 (bits 6 to 0 of subcud: 0101100) results in 32768 hz (0 ppm). figure 7-26 shows the operation when (dev, f6, f5, f4, f3, f2, f1, f0) is (0, 0, 1, 0, 1, 1, 0, 0). chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 322 figure 7-26. operation when (dev, f6, f5, f4, f3 , f2, f1, f0) = (0, 0, 1, 0, 1, 1, 0, 0) rsubc count value sec 00 01 8055h 0000h 0001h 7fffh 0000h 8054h 40 8055h 0000h 8054h 8055h 0000h 8054h 19 0000h 0001h 7fffh 20 39 0000h 0001h 7fffh 0000h 0001h 7fffh 59 00 8055h 0000h 8054h 7fffh + 56h (86) 7fffh + 56h (86) 7fffh + 56h (86) 7fffh+56h (86) count start chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 323 correction example <2> example of correcting from 32767.4 hz to 32768 hz (32767.4 hz + 18.3 ppm) [measuring the oscillation frequency] the oscillation frequency note of each product is measured by outputti ng about 32 khz from the rtccl pin or outputting about 1 hz from the rtc1hz pin when the watch erro r correction register is set to its initial value (00h). note see 7.4.5 1 hz output of real-time counter for the setting procedure of outputting about 1 hz from the rtc1hz pin, and 7.4.6 32.768 khz output of real-time counter for the setting procedure of outputting about 32 khz from the rtccl pin. [calculating the correction value] (when the output frequency from t he rtccl pin is 0.9999817 hz) oscillation frequency = 32768 0.9999817 32767.4 hz assume the target frequency to be 32768 hz (32767.4 hz + 18.3 ppm) and dev to be 1. the expression for calculating the correct ion value when dev is 1 is applied. correction value = number of correction counts in 1 minute = (oscillation frequency target frequency ? 1) 32768 60 = (32767.4 32768 ? 1) 32768 60 = ? 36 [calculating the values to be set to (f6 to f0)] (when the correction value is ? 36) if the correction value is 0 or less (when quickening), assume f6 to be 1. calculate (f5, f4, f3, f2, f1, f0) from the correction value. ? {(/f5, /f4, /f3, /f2, /f1, /f0) ? 1} 2 = ? 36 (/f5, /f4, /f3, /f2, /f1, /f0) = 17 (/f5, /f4, /f3, /f2, /f1, /f0) = (0, 1, 0, 0, 0, 1) (f5, f4, f3, f2, f1, f0) = (1, 0, 1, 1, 1, 0) consequently, when correcting from 32767.4 hz to 327 68 hz (32767.4 hz + 18.3 ppm), setting the correction register such that dev is 1 and the correction value is ? 36 (bits 6 to 0 of subcud: 1101110) results in 32768 hz (0 ppm). figure 7-27 shows the operation when (dev, f6, f5, f4, f3, f2, f1, f0) is (1, 1, 1, 0, 1, 1, 1, 0). chapter 7 real-time counter preliminary user?s manual u19291ej1v0ud 324 figure 7-27. operation when (dev, f6, f5, f4, f3 , f2, f1, f0) = (1, 1, 1, 0, 1, 1, 1, 0) rsubc count value sec 00 01 7fdbh 0000h 0001h 7fffh 0000h 7fdah 40 19 0000h 0001h 7fffh 0000h 0001h 7fffh 20 39 0000h 0001h 7fffh 0000h 0001h 7fffh 0000h 0001h 7fffh 59 00 7fdbh 0000h 7fdah 7fffh ? 24h (36) 7fffh ? 24h (36) count start preliminary user?s manual u19291ej1v0ud 325 chapter 8 comparators/programmable gain amplifiers 8.1 features of comparator and programmable gain amplifier the features of the programmable gain amp lifiers and comparators are described below. { comparators ? a comparator is equipped with two channels (cmp0, cmp1). ? negative-side input pins (cmp0m, cmp1m) and a positiv e-side input pin (cmp0p, cmp1p) can be connected. ? the output signal of a programmabl e gain amplifier can be used as t he positive-side input signal of a comparator note . ? cmp0m and cmp1m pin inputs and the internal gener ation reference voltage (6 combinations for each comparator) can be selected as the reference voltage. ? the elimination width of the noise elim ination digital filter can be selected. ? an interrupt request is generated when the refe rence voltage is exceeded (intcmp0, intcmp1). { programmable gain amplifiers ? a programmable gain amplifier amplifies and outputs an analog voltage that is input. one among five amplification factor s can be selected. ? the output signal of a programmabl e gain amplifier can be used as t he positive-side input signal of a comparator note . ? the output signal of a programmable gain amplifier ca n be selected as the analog input of an a/d converter. note when using the output signals of the programmable ga in amplifiers as the positive-side input signals of the comparators, the output si gnal is simultaneously input to bot h channels of comparators 0 and 1. chapter 8 comparators/programmable gain amplifiers preliminary user?s manual u19291ej1v0ud 326 figure 8-1. block diagram of comp arator/programmable gain amplifier c1vre c1vrs2 c1vrs1 c1vrs0 c1en c1oe c1inv c1dfs0 c1dfs1 c1dfs2 cmp1p/p82 cmp1m/p83 av ref av ss c0vre c0vrs2 c0vrs1 c0vrs0 c0en c0oe c0inv c0dfs0 c0dfs1 c0dfs2 pgao/cmp0p/p80 cmp0m/p81 av ref av ss oaen oavg2 oavg1 oavg0 + ? + ? internal bus comparator 1 internal reference voltage setting register (c1rvm) comparator 1 control register (c1ctl) intcm1p programmable gain amplifier selector selector controller output reversal circuit noise filter internal bus comparator 0 internal reference voltage setting register (c0rvm) comparator 0 control register (c0ctl) intcm0p a/d converter programmable gain amplifier control register (oam) output reversal circuit noise filter selector selector controller chapter 8 comparators/programmable gain amplifiers preliminary user?s manual u19291ej1v0ud 327 8.2 configurations of comparator and programmable gain amplifier the comparators and programmable gain amplif iers consist of the following hardware. table 8-1. configurations of compar ator and programmable gain amplifier item configuration control registers peripheral enable register 1 (per1) programmable gain amplifier control register (oam) comparator 0 and 1 control registers (c0ctl, c1ctl) comparator 0 and 1 internal re ference voltage setting registers (c0rvm, c1rvm) port input mode register 8 (pim8) port mode register 8 (pm8) 8.3 registers controlling comparator s and programmable gain amplifiers the comparators and programmable gain amplif iers use the following eight registers. ? peripheral enable register 1 (per1) ? programmable gain amplifier control register (oam) ? comparator 0 and 1 control registers (c0ctl, c1ctl) ? comparator 0 and 1 internal reference voltage setting registers (c0rvm, c1rvm) ? port input mode register 8 (pim8) ? port mode register 8 (pm8) chapter 8 comparators/programmable gain amplifiers preliminary user?s manual u19291ej1v0ud 328 (1) peripheral enable register 1 (per1) this register is used to set whether each peripheral hardware macro can be used. power consumption and noise are reduced by stopping the clock supply to unused hardware. make sure to set bit 3 (oacmpen ) to 1 to use a comparator or a programmable gain amplifier. per1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. cautions 1. make sure to set oacmpen to 1 first, when setting the comparator or programmable gain amplifier. writing to the control register of the comparator or programmable gain amplifier will be ignored and all values read will be initialized when oacmpen is set to 0. 2. make sure to set bits 0 to 2 and bi ts 4 to 7 of the per1 register to ?0?. figure 8-2. format of peripheral enable register 1 (per1) address: f00f1h after reset: 00h r/w symbol 7 6 5 4 <3> 2 1 0 per1 0 0 0 0 oacmpen 0 0 0 oacmpen control of comparator and prog rammable gain amplifie r input clock supply 0 stops input clock supply. ? sfr used by the comparator and programmable gain amplifier cannot be written. ? the comparator and programmable gain amplifier is in the reset status. 1 supplies input clock. ? sfr used by the comparator and programmable gain amplifier can be read and written. chapter 8 comparators/programmable gain amplifiers preliminary user?s manual u19291ej1v0ud 329 (2) programmable gain amplif ier control register (oam) this register is used to enable or disable the oper ation of a programmable gain amplifier and set the amplification factor. oam can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 8-3. format of programmable ga in amplifier control register (oam) address: f0240h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 oam oaen 0 0 0 0 oavg2 oavg1 oavg0 oaen programmable gain amplifier operation control 0 stops operation 1 enables operation enables external input from the progr ammable gain amplifier input pin (pgai) inputs the programmable gain amplifier output signal as the positive-side input voltage of comparators 0 and 1 oavg2 oavg1 oavg0 input voltage amplification factor setting 0 0 1 4 0 1 0 6 0 1 1 8 1 0 0 10 1 0 1 12 other than the above setting prohibited cautions 1. set the amplification factor befo re enabling (oaen = 1) the operation of the programmable gain amplifier. changing the am plification factor setti ng in the operation enabled state (oaen = 1) is prohibited. 2. set the cnctl register after setting oam register. remark n = 0, 1 chapter 8 comparators/programmable gain amplifiers preliminary user?s manual u19291ej1v0ud 330 (3) comparator n control register (cnctl) this register is used to control the operation of comparator n, enable or disable comparator output, reverse the output, and set the noise elimination width. cnctl can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 8-4. format of comparat or n control register (cnctl) address: f0241h (c0ctl), f0242h (c1ctl) after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 cnctl cnen 0 0 cnoe cninv cndfs2 cndfs1 cndfs0 cnen comparator operation control 0 stops operation 1 enables operation enables input to the external pins on the positive and negative sides of comparator n note cnoe enabling or disabling of comparator output 0 disables output (output si gnal = fixed to low level) 1 enables output cninv output reversal setting 0 forward 1 reverse cndfs2 cndfs1 cndfs0 noise elimination width setting (f clk = 20 mhz) 0 0 0 noise filter unused 0 0 1 250 ns 0 1 0 500 ns 0 1 1 1 s 1 0 0 2 s other than the above setting prohibited note if oaen = 1 (oam register) and cnen is set to 1, a programmable gain amplifier output signal will be input to the positive-side input of comparator n. cautions 1. rewrite cninv and cndfs2 to cndf s0 after setting the comparator output to the disabled state (cnoe = 0). 2. with the noise eliminatio n width, an extra cpu clock (f clk ) may be eliminated from the setting value. (example: when f clk = 20 mhz, cndfs2 to cndfs0 = 0 01, noise elimination width = 250 to 300 ns) 3. to operate the comparator in combination with a programmable gain amplifier, set the operation of the comparator after setting the operation of the programmable gain amplifier (see figure 8-10 and figure 8-11). 4. the negative-side external pin input of th e comparator will be cutoff when cnvre of the cnrvm register is set (1), regardless of the value that enables or disables the comparator operation (cnen). remarks 1. f clk : cpu or peripheral hardware clock frequency 2. n = 0, 1 chapter 8 comparators/programmable gain amplifiers preliminary user?s manual u19291ej1v0ud 331 (4) comparator n internal referen ce voltage selection register (cnrvm) this register is used to set the internal reference voltag e of comparator n. the internal reference voltage can be selected from six voltages that use av ref . cnrvm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 8-5. format of comparator n internal reference voltage selection register (cnrvm) address: f0243h (c0rvm), f0244h (c1rvm) after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 cnrvm cnvre 0 0 0 0 cnvrs2 cnvrs1 cnvrs0 cnvre internal reference voltage operation control 0 stops operation 1 enables operation connects the internal reference voltage to the negative-side input of comparator n reference voltage setting cnvrs2 cnvrs1 cnvrs0 reference voltage settable with comparator 0 (n = 0) reference voltage settable with comparator 1 (n = 1) 0 0 0 setting prohibited 0 0 1 2av ref /16 3av ref /16 0 1 0 4av ref /16 5av ref /16 0 1 1 6av ref /16 7av ref /16 1 0 0 8av ref /16 9av ref /16 1 0 1 10av ref /16 11av ref /16 1 1 0 12av ref /16 13av ref /16 1 1 1 setting prohibited cautions 1. the operation of the comparator is c ontrolled by cnen when the operation of the internal reference voltage is stopped (cnvre = 0). 2. the negative-side external pin input of th e comparator will be cuto ff when cnvre is set (1), regardless of the value that enables or disables the comparator operation (cnen). 3. set the reference voltage before enabling th e operation of the inte rnal reference voltage (cnvre = 1). changing th e reference voltage setting in the operation enabled state (cnvre = 1) is prohibited. remark n = 0, 1 chapter 8 comparators/programmable gain amplifiers preliminary user?s manual u19291ej1v0ud 332 (5) port input mode register 8 (pim8) this register is used to enable or disable port 8 digital input in 1-bit units. set to digital input disable (used as analog input) to use a comparator or a programmable gain amplifier. set to digital input enable to use the port function or the external interrupt function, because digital input disable (used as analog input) is set by default. pim8 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 8-6. format of port input mode register 8 (pim8) address: f0048h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pim8 0 0 0 0 pim83 pim82 pim81 pim80 pim8n selection of enabling or disabling p8n pin digital input (n = 0 to 3) 0 disables digital input (used as analog input) 1 enables digital input (6) port mode register 8 (pm8) this register is used to set port 8 input or output in 1-bit units. set the pm80 to pm83 bits to 1 to use the p80/cm p0p/intp3/pgai, p81/cmp0m, p82/cmp1p/intp7, or p83/cmp1m pin as the positive-side or negative-side in put function of the comparator, or the programmable gain amplifier input function. the output latches of p80 to p83 may be 0 or 1 at this time. pm80 to pm83 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation se ts this register to ffh. figure 8-7. format of port mode register 8 (pm8) address: fff28h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm8 1 1 1 1 pm83 pm82 pm81 pm80 pm8n p8n pin i/o mode selection (n = 0 to 3) 0 output mode (output buffer on) 1 input mode (output buffer off) caution the port function that is alternatively us ed as the cmp0m, cmp1m pin can be used in the input mode, when the cmp0p, cmp1p pin is selected as the positive-side input of the comparator, and the internal reference voltage is used on the negative side. using the output mode, however, is prohibited. furthermore acc essing port register 8 (p8) is also prohibited. chapter 8 comparators/programmable gain amplifiers preliminary user?s manual u19291ej1v0ud 333 8.4 operations of comparator and programmable gain amplifier 8.4.1 starting comparator and progr ammable gain amplifier operation the procedures for starting the operation of a comparator and a programmable gain amplifier are described below, separately for each use method. { using only a comparator ? using the external pin input for the co mparator reference voltage (figure 8-8) ? using the internal reference voltage for t he comparator reference voltage (figure 8-9) { using a comparator and a programmable gain amplifie r (using the programmable gain amplifier output voltage as the comparator compare voltage input) ? using the external pin input for the co mparator reference voltage (figure 8-10) ? using the internal reference voltage for t he comparator reference voltage (figure 8-11) { using the programmable gain amplifier output volt age as the a/d converter analog input (figure 8-12) figure 8-8. using the external pin input for the co mparator reference voltage (using only a comparator) per1 register setting pim8 register setting start set to the digital input disable state. wait for at least two clocks cnen bit setting cnctl register setting cnoe bit setting wait operation start pm8 register setting set the pm8 register to the input mode. cancel the reset state of the comparator or programmable gain amplifier and start clock supply. use the cninv bit of cnctl to select forwarding or reversing of the output. use cndfs0 to cndfs2 to select the noise elimination width. enable the comparator operation by setting (1) the cnen bit of cnctl. input to the positive side and negative side of the comparator from the external pin will be enabled at the same time. enable the comparator output signal by setting (1) the cnoe bit of cnctl. chapter 8 comparators/programmable gain amplifiers preliminary user?s manual u19291ej1v0ud 334 figure 8-9. using the internal reference vo ltage for the comparator reference voltage (using only a comparator) per1 register setting pim8 register setting start set to the digital input disable state. cnrvm register setting cnvre bit setting cnen bit setting cnctl register setting cnoe bit setting operation start pm8 register setting set the pm8 register to the input mode. cancel the reset state of the comparator or programmable gain amplifier and start clock supply. enable the comparator output signal by setting (1) the cnoe bit of cnctl. select the internal reference voltage by using cnvrs0 to cnvrs2 of cnrvm. use the cninv bit of cnctl to select forwarding or reversing of the output. use cndfs0 to cndfs2 to select the noise elimination width. wait wait for at least two clocks set to use the internal reference voltage by setting (1) cnvre of cnrvm. the internal reference voltage will be input to the negative side of the comparator at the same time. enable the comparator operation by setting (1) the cnen bit of cnctl. input to the positive side of the comparator from the external pin will be enabled at the same time. chapter 8 comparators/programmable gain amplifiers preliminary user?s manual u19291ej1v0ud 335 figure 8-10. using the external pin input for the co mparator reference voltage (using a comparator and a programmable gain amplifier) per1 register setting oaen bit setting pim8 register setting oam register setting start set to the digital input disable state. set the amplification factor by using oavg0 to oavg2 of oam. cnen bit setting cnctl register setting cnoe bit setting operation start pm8 register setting set the pm8 register to the input mode. cancel the reset state of the comparator or programmable gain amplifier and start clock supply. use the cninv bit of cnctl to select forwarding or reversing of the output. use cndfs0 to cndfs2 to select the noise elimination width. enable the comparator output signal by setting (1) the cnoe bit of cnctl. wait wait for at least two clocks enable the programmable gain amplifier operation by setting (1) the oaen bit of oam. at the same time, enable the external input from the programmable gain amplifier input pin (pgai). the programmable gain amplifier output signal will be input as the positive-side input voltage of the comparator. enable the comparator operation by setting (1) the cnen bit of cnctl. input to the negative side of the comparator from the external pin will be enabled at the same time. remark n = 0, 1 chapter 8 comparators/programmable gain amplifiers preliminary user?s manual u19291ej1v0ud 336 figure 8-11. using the internal reference voltage for the comparator reference vo ltage (using a comparator and a programmable gain amplifier) per1 register setting oaen bit setting pim8 register setting oam register setting start set to the digital input disable state. set the amplification factor by using oavg0 to oavg2 of oam. cnrvm register setting cnvre bit setting cnen bit setting cnoe bit setting operation start pm8 register setting set the pm8 register to the input mode. cancel the reset state of the comparator or programmable gain amplifier and start clock supply. enable the comparator operation by setting (1) the cnen bit of cnctl. cnctl register setting enable the comparator output signal by setting (1) the cnoe bit of cnctl. use cnvrs0 to cnvrs2 of cnrvm to select the internal reference voltage. wait wait for at least two clocks enable the programmable gain amplifier operation by setting (1) the oaen bit of oam. at the same time, enable the external input from the programmable gain amplifier input pin (pgai). the programmable gain amplifier output signal will be input as the positive-side input voltage of the comparator. set to use the internal reference voltage by setting (1) cnvre of cnrvm. the internal reference voltage will be input to the negative side of the comparator at the same time. use the cninv bit of cnctl to select forwarding or reversing of the output. use cndfs0 to cndfs2 to select the noise elimination width. remark n = 0, 1 chapter 8 comparators/programmable gain amplifiers preliminary user?s manual u19291ej1v0ud 337 perform the following settings before selecting the programm able gain amplifier output signal as the analog input by using the analog input channel specification r egister (ads) of the a/d converter (refer to 11.4.1 basic operations of a/d converter ). figure 8-12. using the programmable gain amplifie r output voltage as the a/d converter analog input per1 register setting oaen bit setting pim8 register setting oam register setting start set to the digital input disable state. set the amplification factor by using oavg0 to oavg2 of oam. a/d converter register setting pm8 register setting set the pm8 register to the input mode. cancel the reset state of the comparator or programmable gain amplifier and start clock supply. enable the programmable gain amplifier operation by setting (1) the oaen bit of oam. at the same time, enable the external input from the programmable gain amplifier input pin (pgai). the programmable gain amplifier output signal will be input as the positive-side input voltage of the comparator. remark n = 0, 1 chapter 8 comparators/programmable gain amplifiers preliminary user?s manual u19291ej1v0ud 338 8.4.2 stopping comparator and pr ogrammable gain amplifier operation the procedures for stopping the operat ion of a comparator and a programmable gain amplifier are described below, separately for each use method. { using only a comparator (figure 8-13) { using the programmable gain amplifier output voltage as the comparator compare vo ltage input (figure 8-14) { using the programmable gain amplifier output volt age as the a/d converter analog input (figure 8-15) figure 8-13. using only a comparator per1 register setting operation in progress operation stop cnoe bit setting clear (0) the cnoe bit of cnctl. stop the clock supply to the comparator or programmable gain amplifier and initialize the setting register. figure 8-14. using the programmable ga in amplifier output voltage as the comparator compare voltage input per1 register setting oaen bit setting operation in progress operation stop cnoe bit setting clear (0) the cnoe bit of cnctl. clear (0) the oaen bit of oam and prohibit the programmable gain amplifier input. stop the clock supply to the comparator or programmable gain amplifier and initialize the setting register. figure 8-15. using the programmable gain amplifie r output voltage as the a/d converter analog input per1 register setting oaen bit setting operation in progress operation stop adcs bit setting clear (0) the adcs bit of a/d converter mode register (adm). clear (0) the oaen bit of oam and prohibit the programmable gain amplifier input. stop the clock supply to the comparator or programmable gain amplifier and initialize the setting register. remark n = 0, 1 preliminary user?s manual u19291ej1v0ud 339 chapter 9 clock output/buzzer output controller the number of output pins of the clo ck output and buzzer output controllers differs, depending on the product. furthermore, 44-pin products of the 78k0r/kc3-l are not provided with clock output and buzzer output controllers. output pin kc3-l (44-pin) kc3-l (48-pin) kd3-l ke3-l pclbuz0 ? pclbuz1 ? ? ? 9.1 functions of clock output/buzzer output controller the clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral ics. buzzer output is a function to output a square wave of buzzer frequency. one pin can be used to output a clock or buzzer sound. two output pins, pclbuz0 and pclbuz1, are available. pclbuzn outputs a clock selected by cl ock output select register n (cksn). figure 9-1 shows the block diagram of clock output/buzzer output controller. remark n = 0: 78k0r/kc3-l (48-pin), 78k0r/kd3-l n = 0, 1: 78k0r/ke3-l chapter 9 clock output/buzzer output controller preliminary user?s manual u19291ej1v0ud 340 figure 9-1. block diagram of clo ck output/buzzer output controller ? 78k0r/kc3-l (48-pin), 78k0r/kd3-l f main f sub pcloe0 0 0 0 pcloe0 5 3 pclbuz0 note /p140 csel0 ccs02 ccs01 ccs00 8 clock/buzzer controller prescaler prescaler selector internal bus clock output select register 0 (cks0) output latch (p140) f main /2 11 to f main /2 13 f main to f main /2 4 f sub to f sub /2 7 ? 78k0r/ke3-l f main f sub pcloe0 0 0 0 pcloe0 5 3 pclbuz0 note /p140 pclbuz1 note /p141 csel0 ccs02 ccs01 ccs00 pm141 pcloe1 0 0 0 csel1 ccs12 ccs11 ccs10 8 pcloe1 8 f main /2 11 to f main /2 13 clock/buzzer controller internal bus clock output select register 1 (cks1) prescaler prescaler selector selector clock/buzzer controller output latch (p141) internal bus clock output select register 0 (cks0) output latch (p140) f main /2 11 to f main /2 13 f main to f main /2 4 f main to f main /2 4 f sub to f sub /2 7 f sub to f sub /2 7 note the pclbuz0 and pclbuz1 pins can out put a clock of up to 10 mhz at 2.7 v v dd . setting a clock exceeding 5 mhz at v dd < 2.7 v is prohibited. chapter 9 clock output/buzzer output controller preliminary user?s manual u19291ej1v0ud 341 9.2 configuration of clock output/buzzer output controller the clock output/buzzer output controller includes the following hardware. table 9-1. configuration of clock output/buzzer output controller item configuration control registers clock output select registers n (cksn) port mode register 14 (pm14) (78k0r/ke3-l only) port register 14 (p14) remark n = 0: 78k0r/kc3-l (48-pin), 78k0r/kd3-l n = 0, 1: 78k0r/ke3-l 9.3 registers controlling clock output/buzzer output controller the following two registers are used to control the clock output/buzzer output controller. ? clock output select registers n (cksn) ? port mode register 14 (pm14) (78k0r/ke3-l only) (1) clock output select registers n (cksn) these registers set output enable/disa ble for clock output or for the buzzer frequency output pin (pclbuzn), and set the output clock. select the clock to be output from pclbuzn by using cksn. cksn are set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. remark n = 0: 78k0r/kc3-l (48-pin), 78k0r/kd3-l n = 0, 1: 78k0r/ke3-l chapter 9 clock output/buzzer output controller preliminary user?s manual u19291ej1v0ud 342 figure 9-2. format of clock output select register n (cksn) address: fffa5h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 cksn pcloen 0 0 0 cseln ccsn2 ccsn1 ccsn0 pcloen pclbuzn output enabl e/disable specification 0 output disable (default) 1 output enable pclbuzn output clock selection cseln ccsn2 ccsn1 ccsn0 f main = 5 mhz f main = 10 mhz f main = 20 mhz 0 0 0 0 f main 5 mhz 10 mhz note setting prohibited note 0 0 0 1 f main /2 2.5 mhz 5 mhz 10 mhz note 0 0 1 0 f main /2 2 1.25 mhz 2.5 mhz 5 mhz 0 0 1 1 f main /2 3 625 khz 1.25 mhz 2.5 mhz 0 1 0 0 f main /2 4 312.5 khz 625 khz 1.25 mhz 0 1 0 1 f main /2 11 2.44 khz 4.88 khz 9.76 khz 0 1 1 0 f main /2 12 1.22 khz 2.44 khz 4.88 khz 0 1 1 1 f main /2 13 610 hz 1.22 khz 2.44 khz 1 0 0 0 f sub 32.768 khz 1 0 0 1 f sub /2 16.384 khz 1 0 1 0 f sub /2 2 8.192 khz 1 0 1 1 f sub /2 3 4.096 khz 1 1 0 0 f sub /2 4 2.048 khz 1 1 0 1 f sub /2 5 1.024 khz 1 1 1 0 f sub /2 6 512 hz 1 1 1 1 f sub /2 7 256 hz note use the output clock within a rang e of 10 mhz. furthermore, w hen using the output clock at v dd < 2.7 v, use it within 5 mhz. cautions 1. change the output clock after disabling clock output (pcloen = 0). 2. if the selected clock (f main or f sub ) stops during clock output (pcloen = 1), the output becomes undefined. remarks 1. n = 0: 78k0r/kc3-l (48-pin), 78k0r/kd3-l n = 0, 1: 78k0r/ke3-l 2. f main : main system clock frequency 3. f sub : subsystem clock frequency chapter 9 clock output/buzzer output controller preliminary user?s manual u19291ej1v0ud 343 (2) port mode register 14 (pm14) (78k0r/ke3-l only) this register sets p141 input/output of port 14 in 1-bit units. when using the p140/pclb uz0 and p141/pclbuz1 pins for clock output/buzzer output, clear pm141 and the output latches of p140 and p141 to 0. pm14 is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 9-3. format of port mode register 14 (pm14) address: fff2eh after reset: feh r/w symbol 7 6 5 4 3 2 1 0 pm14 1 1 1 1 1 1 pm141 0 pm141 p141 pin i/o mode selection 0 output mode (output buffer on) 1 input mode (output buffer off) 9.4 operations of clock output/buzzer output controller one pin can be used to output a clock or buzzer sound. pclbuz0 outputs a clock/buzzer selected by clock output select register 0 (cks0). pclbuz1 outputs a clock/buzzer selected by clock output select register 1 (cks1). 9.4.1 operation as output pin pclbuzn is output as the following procedure. <1> select the output frequency with bits 0 to 3 (ccsn0 to ccsn2, cseln) of the clo ck output select register (cksn) of the pclbuzn pin (out put in disabled status). <2> set bit 7 (pcloen) of cksn to 1 to enable clock/buzzer output. remarks 1. the controller is designed not to output a pulse with a narrow width when it is used to output a clock and when clock output is enabled or disabled. as s hown in figure 9-4, be sure to start output from the low period of the clock (marked with * in the figure). when stopping output, do so after the high- level period of the clock. 2. n = 0: 78k0r/kc3-l (48-pin), 78k0r/kd3-l n = 0, 1: 78k0r/ke3-l figure 9-4. remote control output application example pcloen clock output ** preliminary user?s manual u19291ej1v0ud 344 chapter 10 watchdog timer 10.1 functions of watchdog timer the watchdog timer operates on the internal low-speed oscillation clock. the watchdog timer is used to detect an inadvertent program loop. if a program loop is detected, an internal reset signal is generated. program loop is detected in the following cases. ? if the watchdog timer counter overflows ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte ? if data is written to wdte during a window close period when a reset occurs due to the watchdog timer, bit 4 (wdrf) of the reset control flag register (resf) is set to 1. for details of resf, see chapter 19 reset function . when 75% of the overflow time is reached, an interval interrupt can be generated. chapter 10 watchdog timer preliminary user?s manual u19291ej1v0ud 345 10.2 configuration of watchdog timer the watchdog timer includes the following hardware. table 10-1. configuration of watchdog timer item configuration control register watchdog timer enable register (wdte) how the counter operation is controlled, overflow time, wi ndow open period, and interval interrupt are set by the option byte. table 10-2. setting of op tion bytes and watchdog timer setting of watchdog timer option byte (000c0h) watchdog timer interval interrupt bit 7 (wdtint) window open period bits 6 and 5 (window1, window0) controlling counter operation of watchdog timer bit 4 (wdton) overflow time of watchdog timer bits 3 to 1 (wdcs2 to wdcs0) controlling counter operation of watchdog timer (in halt/stop mode) bit 0 (wdstbyon) remark for the option byte, see chapter 23 option byte . figure 10-1. block diag ram of watchdog timer f il wdton of option byte (000c0h) wdtint of option byte (000c0h) interval time controller (count value overflow time 3/4) interval time interrupt wdcs2 to wdcs0 of option byte (000c0h) clock input controller 20-bit counter selector overflow signal reset output controller internal reset signal count clear signal window size decision signal window size check watchdog timer enable register (wdte) write detector to wdte except ach internal bus window1 and window0 of option byte (000c0h) f il /2 7 to f il /2 17 chapter 10 watchdog timer preliminary user?s manual u19291ej1v0ud 346 10.3 register controlling watchdog timer the watchdog timer is controlled by the watchdog timer enable register (wdte). (1) watchdog timer enable register (wdte) writing ?ach? to wdte clears the watchdog timer counter and starts counting again. this register can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 9ah or 1ah note . figure 10-2. format of watchdog timer enable register (wdte) 0 1 2 3 4 5 6 7 symbol wdte address: fffabh after reset: 9ah/1ah note r/w note the wdte reset value differs depending on the wdton setting value of the option byte (000c0h). to operate watchdog timer, set wdton to 1. wdton setting value wdte reset value 0 (watchdog timer count operation disabled) 1ah 1 (watchdog timer count operation enabled) 9ah cautions 1. if a value other than ?ach? is writte n to wdte, an internal r eset signal is generated. 2. if a 1-bit memory manipulation instructio n is executed for wdte, an internal reset signal is generated. 3. the value read from wdte is 9ah/1ah (this differs fr om the written value (ach)). chapter 10 watchdog timer preliminary user?s manual u19291ej1v0ud 347 10.4 operation of watchdog timer 10.4.1 controlling operation of watchdog timer 1. when the watchdog timer is used, its operati on is specified by the option byte (000c0h). ? enable counting operation of the watchdog timer by setting bit 4 (wdton) of the option byte (000c0h) to 1 (the counter starts operating after a reset release) (for details, see chapter 23 ). wdton watchdog timer counter 0 counter operation disabled (counting stopped after reset) 1 counter operation enabled (counting started after reset) ? set an overflow time by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (000c0h) (for details, see 10.4.2 and chapter 23 ). ? set a window open period by using bits 6 and 5 (window1 and window0) of the option byte (000c0h) (for details, see 10.4.3 and chapter 23 ). 2. after a reset release, the watchdog timer starts counting. 3. by writing ?ach? to wdte after the watchdog timer starts counting and before the overflow time set by the option byte, the watchdog timer is cl eared and starts counting again. 4. after that, write wdte the second time or later afte r a reset release during the window open period. if wdte is written during a window close period, an internal reset signal is generated. 5. if the overflow time expires without ?ach? wri tten to wdte, an internal reset signal is generated. an internal reset signal is generated in the following cases. ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte cautions 1. when data is written to wdte for th e first time after reset re lease, the watchdog timer is cleared in any timing regardl ess of the window open time, as long as the register is written before the overflow time, and the wa tchdog timer starts counting again. 2. if the watchdog timer is cleared by writi ng ?ach? to wdte, the actual overflow time may be different from the overflow time set by the option byte by up to 2/f il seconds. 3. the watchdog timer can be cleared imme diately before the c ount value overflows. chapter 10 watchdog timer preliminary user?s manual u19291ej1v0ud 348 cautions 4. the operation of the watchdog time r in the halt and stop modes differs as follows depending on the set value of bit 0 (wds tbyon) of the option byte (000c0h). wdstbyon = 0 wdstbyon = 1 in halt mode in stop mode watchdog timer operation stops. watchdog timer operation continues. if wdstbyon = 0, the watchdog timer resum es counting after the halt or stop mode is released. at this time, the counter is cleared to 0 and counting starts. when operating with the x1 oscillation clock after releasi ng the stop mode, the cpu starts operating after the oscillation stabilization time has elapsed. therefore, if the period between the stop mode release a nd the watchdog timer overflow is short, an overflow occurs during the o scillation stabilization time, causing a reset. consequently, set the ov erflow time in consideration of the oscillation stabilization time when operating with the x1 oscillation clock a nd when the watchdog timer is to be cleared after the stop mode release by an interval interrupt. 5. the watchdog timer continues its operati on during self-programming of the flash memory and eeprom tm emulation. during processing, the in terrupt acknowledge time is delayed. set the overflow time and window size taking this delay into consideration. 10.4.2 setting overflow time of watchdog timer set the overflow time of the watchdog timer by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (000c0h). if an overflow occurs, an internal reset signal is generat ed. the present count is cleared and the watchdog timer starts counting again by writing ?ach? to wdte dur ing the window open period before the overflow time. the following overflow times can be set. table 10-3. setting of over flow time of watchdog timer wdcs2 wdcs1 wdcs0 overflow time of watchdog timer (f il = 33 khz (max.)) 0 0 0 2 7 /f il (3.88 ms) 0 0 1 2 8 /f il (7.76 ms) 0 1 0 2 9 /f il (15.52 ms) 0 1 1 2 10 /f il (31.03 ms) 1 0 0 2 12 /f il (124.12 ms) 1 0 1 2 14 /f il (496.48 ms) 1 1 0 2 15 /f il (992.97 ms) 1 1 1 2 17 /f il (3971.88 ms) caution the watchdog timer conti nues its operation during self-program ming of the flash memory and eeprom emulation. during processing, the inte rrupt acknowledge time is delayed. set the overflow time and window size taki ng this delay into consideration. remark f il : internal low-speed oscillation clock frequency chapter 10 watchdog timer preliminary user?s manual u19291ej1v0ud 349 10.4.3 setting window open period of watchdog timer set the window open period of the watchdog timer by usi ng bits 6 and 5 (window1, window0) of the option byte (000c0h). the outline of the window is as follows. ? if ?ach? is written to wdte during the window open per iod, the watchdog timer is cleared and starts counting again. ? even if ?ach? is written to wdte during the window cl ose period, an abnormality is detected and an internal reset signal is generated. example : if the window open period is 25% window close period (75%) window open period (25%) counting starts overflow time counting starts again when ?ach? is written to wdte. internal reset signal is generated if ?ach? is written to wdte. caution when data is writte n to wdte for the first time after reset release, the watchdog timer is cleared in any timing regardless of the window open time , as long as the register is written before the overflow time, and the watchdog timer starts counting again. the window open period can be set is as follows. table 10-4. setting window open period of watchdog timer window1 window0 window open period of watchdog timer 0 0 25% 0 1 50% 1 0 75% 1 1 100% cautions 1. the watchdog timer continues its operation during self-programmi ng of the flash memory and eeprom emulation. during processing, the interrupt acknowledge ti me is delayed. set the overflow time and window size t aking this delay into consideration. 2. when bit 0 (wdstbyon) of the option byte (000c0h) = 0, the window open period is 100% regardless of the values of window1 and window0. 3. do not set the window open period to 25% if the watchdog timer corresponds to either of the conditions below. ? when stopping all main system clocks (internal high-speed osc illation clock, x1 clock, and external main system clock) by use of the stop mode or software. chapter 10 watchdog timer preliminary user?s manual u19291ej1v0ud 350 remark if the overflow time is set to 2 10 /f il , the window close time and open time are as follows. setting of window open period 25% 50% 75% 100% window close time 0 to 28.44 ms 0 to 18.96 ms 0 to 9.48 ms none window open time 28.44 to 31.03 ms 18.96 to 31.03 ms 9.48 to 31.03 ms 0 to 31.03 ms preliminary user?s manual u19291ej1v0ud 351 chapter 11 a/d converter the number of analog input channels of the a/d converter differs, depending on the product. 78k0r/kc3-l (44-pin) 78k0r/kc3-l (48-pin) 78k0r/kd3-l 78k0r/ke3-l analog input channels 10 ch (ani0 to ani9) 11 ch (ani0 to ani10) 11 ch (ani0 to ani10) 12 ch (ani0 to ani11) 11.1 function of a/d converter the a/d converter is a 10-bit resolution converter that co nverts analog input signals into digital values, and is configured to control a total of thirty channels of analog inputs, including up to twelve channels of a/d converter analog inputs (ani0 to ani11) and a progra mmable gain amplifier output (pgao). the a/d converter has the following function. ? 10-bit resolution a/d conversion 10-bit resolution a/d conversion is carried out repeatedly for one analog input channel selected from ani0 to ani11. each time an a/d conversion operation en ds, an interrupt request (intad) is generated. figure 11-1. block diag ram of a/d converter intad adcs admd fr2 fr1 adce fr0 av ss 5 ani0/p20 ani1/p21 ani2/p22 ani3/p23 ani4/p24 ani5/p25 lv1 lv0 6 adpc3 adpc2 adpc1 adpc0 5 adpc4 ads3 ads2 ads1 ads0 adoas av ref av ss ani6/p26 ani7/p27 ani8/p150 ani9/p151 ani10/p152 ani11/p153 adcs bit sample & hold circuit a/d voltage comparator array selector selector successive approximation register (sar) programmable gain amplifier output signal (pgao) from pgai pin controller a/d conversion result register (adcr) a/d port configuration register (adpc) analog input channel specification register (ads) internal bus a/d converter mode register (adm) remark ani0 to ani9: 78k0r/kc3-l (44-pin) ani0 to ani10: 78k0r/kc3-l (48-pin) and 78k0r/kd3-l ani0 to ani11: 78k0r/ke3-l chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 352 11.2 configuration of a/d converter the a/d converter includes the following hardware. (1) ani0 to ani11 pins these are the analog input pins of the twelve channels of the a/d converter. they input analog signals to be converted into digital signals. pins other than the one selected as the analog input pin can be used as i/o port pins. remark ani0 to ani9: 78k0r/kc3-l (44-pin) ani0 to ani10: 78k0r/kc3-l (48-pin) and 78k0r/kd3-l ani0 to ani11: 78k0r/ke3-l (2) pgao this is the programmable gain amp lifier output signal from pgai pin. the a/d converter can perform a/d conversion by selecting the output signal of the programmable gain amplifier as the analog input. (3) sample & hold circuit the sample & hold circuit samples each of the analog inpu t voltages sequentially sent from the input circuit, and sends them to the a/d voltage compar ator. this circuit also holds the sampled analog input voltage during a/d conversion. (4) a/d voltage comparator this a/d voltage comparator compares the voltage generated from the voltag e tap of the array with the analog input voltage. if the analog input voltage is found to be greater t han the reference voltage (1/2 av ref ) as a result of the comparison, the most significant bit (msb) of the successive approximation register (sar) is set. if the analog input voltage is less than the reference voltage (1/2 av ref ), the msb of the sar is reset. after that, bit 10 of the sar register is automatically set, and the next com parison is made. the voltage tap of the array is selected by the value of bit 11, to which the result has been already set. bit 11 = 0: (1/4 av ref ) bit 11 = 1: (3/4 av ref ) the voltage tap of the array and the analog input voltage are compared and bit 10 of the sar register is manipulated according to the result of the comparison. analog input voltage voltage tap of array: bit 10 = 1 analog input voltage voltage tap of array: bit 10 = 0 comparison is continued like this to bit 0 of the sar register. (5) array the array generates the comparison volt age input from an analog input pin. chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 353 (6) successive approximation register (sar) the sar register is a 12-bit register that sets voltage tap data whose val ues from the array match the voltage values of the analog input pins, 1 bit at a ti me starting from the most significant bit (msb). if data is set in the sar register all the way to the least significant bit (lsb) (end of a/d conversion), the contents of the sar register (conversion result s) are held in the a/d conversion re sult register (adcr). when all the specified a/d conversion op erations have ended, an a/d conversion end interrupt request signal (intad) is generated. (7) 10-bit a/d conversion r esult register (adcr) the a/d conversion result is loaded from the successive approximation register to th is register each time a/d conversion is completed, and the adcr re gister holds the a/d conversion result in its higher 10 bits (the lower 6 bits are fixed to 0). (8) 8-bit a/d conversion result register (adcrh) the a/d conversion result is loaded from the successive approximation register to th is register each time a/d conversion is completed, and the adcrh register stores the higher 8 bi ts of the a/d conversion result. (9) controller this circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well as starting and stopping of t he conversion operation. when a/d c onversion has been completed, this controller generates intad. (10) av ref pin this pin inputs the reference voltage of the a/d converter, the programmabl e gain amplifier, the power supply pins and a/d converter of the comparator, and the compar ator. when all pins of ports 2, 15, and 8 are used as the analog port pins, make the potential of av ref be such that 1.8 v av ref v dd . when one or more of the pins of ports 2, 15, and 8 are used as the digital port pins, make av ref the same potential as v dd . the analog signal input to ani0 to ani11 is converted into a digital signal, based on the voltage applied across av ref and av ss . (11) av ss pin this is the ground potential pin of the a/d converter. al ways use this pin at the same potential as that of the v ss pin even when the a/d converter is not used. remark ani0 to ani9: 78k0r/kc3-l (44-pin) ani0 to ani10: 78k0r/kc3-l (48-pin) and 78k0r/kd3-l ani0 to ani11: 78k0r/ke3-l chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 354 11.3 registers used in a/d converter the a/d converter uses the following seven registers. ? peripheral enable register 0 (per0) ? a/d converter mode register (adm) ? a/d port configuration register (adpc) ? analog input channel specification register (ads) ? port mode registers 2, 15, 8 (pm2, pm15, pm8) ? 10-bit a/d conversion result register (adcr) ? 8-bit a/d conversion result register (adcrh) (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripher al hardware macro. clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. when the a/d converter is used, be sure to se t bit 5 (adcen) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 11-2. format of periphera l enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> 6 <5> <4> 3 <2> 1 0 per0 rtcen 0 adcen iicaen 0 sau0en 0 0 adcen control of a/d conv erter input clock supply 0 stops supply of input clock. ? sfr used by the a/d converter cannot be written. ? the a/d converter is in the reset status. 1 supplies input clock. ? sfr used by the a/d converter can be read/written. cautions 1. when setting the a/d conver ter, be sure to set adcen to 1 fi rst. if adcen = 0, writing to a control register of the a/d converter is ignored , and, even if the register is read, only the default value is read. 2. be sure to clear bits 0, 1, 3, and 6 (bits 0, 1, 3, 4, and 6 for 44-pin products of 78k0r/kc3- l) of the per0 register, to 0. chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 355 (2) a/d converter mode register (adm) this register sets the conversion time for analog inpu t to be a/d converted, and starts/stops conversion. adm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 11-3. format of a/d converter mode register (adm) adce lv0 note 1 lv1 note 1 fr0 note 1 fr1 note 1 fr2 note 1 admd adcs a/d conversion operation control stops conversion operation enables conversion operation adcs 0 1 <0> 1 2 3 4 5 6 <7> adm address: fff30h after reset: 00h r/w symbol a/d conversion operation mode specification select mode scan mode admd 0 1 a/d voltage comparator operation control note 2 stops a/d voltage comparator operation enables a/d voltage comparator operation (a/d voltage comparator: 1/2av ref operation) adce 0 1 notes 1. for details of fr2 to fr0, lv 1, lv0, and a/d conversion, see table 11-2 a/d conversion time selection . 2. the operation of the a/d volt age comparator is controlled by adcs and adce, and it takes 1 s from operation start to operation stab ilization. therefore, when adcs is set to 1 after 1 s or more has elapsed from the time adce is set to 1, the conversi on result at that time has priority over the first conversion result. otherwise, ignor e data of the first conversion. table 11-1. settings of adcs and adce adcs adce a/d co nversion operation 0 0 stop status (dc power consumption path does not exist) 0 1 conversion waiting mode (a/d voltage comparator: 1/2av ref operation, only comparator consumes power) 1 0 setting prohibited 1 1 conversion mode (a/d voltage comparator: 1/2av ref operation) chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 356 figure 11-4. timing chart when a/ d voltage comparator is used adce a/d voltage comparator adcs conversion operation conversion operation conversion stopped conversion waiting a/d voltage comparator: 1/2av ref operation note note to stabilize the internal circuit, the time from the rising of the adce bit to the falling of the adcs bit must be 1 s or longer. caution a/d conversion must be sto pped before rewriting bits fr0 to fr2, lv1, and lv0 to values other than the identical data. chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 357 table 11-2. a/d conversion time selection (1/3) (1) 4.0 v av ref 5.5 v a/d converter mode register (adm) conversion time selection fr2 fr1 fr0 lv1 lv0 mode f clk = 2 mhz f clk = 5 mhz f clk = 10 mhz f clk = 20 mhz conversion clock (f ad ) 0 0 0 setting prohibited 34.2 s 17.1 s f clk /20 0 0 1 34.4 s 17.2 s 8.6 s f clk /10 0 1 0 setting prohibited 27.6 s 13.8 s 6.9 s f clk /8 0 1 1 52.0 s 20.8 s 10.4 s 5.2 s f clk /6 1 0 0 35.0 s 14.0 s 7.0 s f clk /4 1 0 1 26.5 s 10.6 s 5.3 s f clk /3 1 1 0 18.0 s 7.2 s f clk /2 1 1 1 0 0 standard 9.5 s setting prohibited setting prohibited setting prohibited f clk 0 1 voltage boost setting prohibited ? 0 0 0 64.4 s 32.2 s 16.1 s f clk /20 0 0 1 setting prohibited 32.4 s 16.2 s 8.1 s f clk /10 0 1 0 65.0 s 26.0 s 13.0 s 6.5 s f clk /8 0 1 1 49.0 s 19.6 s 9.8 s 4.9 s f clk /6 1 0 0 33.0 s 13.2 s 6.6 s 3.3 s f clk /4 1 0 1 25.0 s 10.0 s 5.0 s 2.5 s f clk /3 1 1 0 17.0 s 6.8 s 3.4 s f clk /2 1 1 1 1 0 high speed 1 9.0 s 3.6 s setting prohibited setting prohibited f clk 0 0 0 setting prohibited 34.2 s 17.1 s f clk /20 0 0 1 34.4 s 17.2 s 8.6 s f clk /10 0 1 0 setting prohibited 27.6 s 13.8 s 6.9 s f clk /8 0 1 1 52.0 s 20.8 s 10.4 s 5.2 s f clk /6 1 0 0 35.0 s 14.0 s 7.0 s 3.5 s f clk /4 1 0 1 26.5 s 10.6 s 5.3 s f clk /3 1 1 0 18.0 s 7.2 s 3.6 s f clk /2 1 1 1 1 1 high speed 2 9.5 s 3.8 s setting prohibited setting prohibited f clk cautions 1. when rewriting fr2 to fr0, lv1, and lv0 to other than the same data, stop a/d conversion once (adcs = 0) beforehand. 2. the above conversion time does not include cl ock frequency errors. select conversion time, taking clock frequency erro rs into consideration. remark f clk : cpu/peripheral hardware clock frequency chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 358 table 11-2. a/d conversion time selection (2/3) (2) 2.7 v av ref 5.5 v a/d converter mode register (adm) conversion time selection fr2 fr1 fr0 lv1 lv0 mode f clk = 2 mhz f clk = 5 mhz f clk = 10 mhz f clk = 20 mhz conversion clock (f ad ) 0 0 0 setting prohibited 34.2 s 17.1 s f clk /20 0 0 1 34.4 s 17.2 s 8.6 s f clk /10 0 1 0 setting prohibited 27.6 s 13.8 s f clk /8 0 1 1 52.0 s 20.8 s 10.4 s f clk /6 1 0 0 35.0 s 14.0 s f clk /4 1 0 1 26.5 s 10.6 s f clk /3 1 1 0 18.0 s f clk /2 1 1 1 0 0 standard 9.5 s setting prohibited setting prohibited setting prohibited f clk 0 1 voltage boost setting prohibited ? 1 0 high speed 1 setting prohibited ? 0 0 0 setting prohibited 34.2 s 17.1 s f clk /20 0 0 1 34.4 s 17.2 s 8.6 s f clk /10 0 1 0 setting prohibited 27.6 s 13.8 s 6.9 s f clk /8 0 1 1 52.0 s 20.8 s 10.4 s 5.2 s f clk /6 1 0 0 35.0 s 14.0 s 7.0 s 3.5 s f clk /4 1 0 1 26.5 s 10.6 s 5.3 s f clk /3 1 1 0 18.0 s 7.2 s 3.6 s f clk /2 1 1 1 1 1 high speed 2 9.5 s 3.8 s setting prohibited setting prohibited f clk cautions 1. when rewriting fr2 to fr0, lv1, and lv0 to other than the same data, stop a/d conversion once (adcs = 0) beforehand. 2. the above conversion time does not include cl ock frequency errors. select conversion time, taking clock frequency erro rs into consideration. remark f clk : cpu/peripheral hardware clock frequency chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 359 table 11-2. a/d conversion time selection (3/3) (3) 1.8 v av ref 4.0 v a/d converter mode register (adm) conversion time selection fr2 fr1 fr0 lv1 lv0 mode f clk = 2 mhz f clk = 5 mhz f clk = 10 mhz f clk = 20 mhz conversion clock (f ad ) 0 0 standard setting prohibited 0 0 0 setting prohibited 48.2 s 24.1 s f clk /20 0 0 1 48.4 s 24.2 s f clk /10 0 1 0 38.8 s f clk /8 0 1 1 setting prohibited 29.2 s f clk /6 1 0 0 49.0 s f clk /4 1 0 1 37.0 s f clk /3 1 1 0 25.0 s f clk /2 1 1 1 0 1 voltage boost setting prohibited setting prohibited setting prohibited setting prohibited f clk 1 0 high speed 1 setting prohibited ? 1 1 high speed 2 setting prohibited ? other than above setting prohibited cautions 1. when rewriting fr2 to fr0, lv1, and lv0 to other than the same data, stop a/d conversion once (adcs = 0) beforehand. 2. the above conversion time does not include cl ock frequency errors. select conversion time, taking clock frequency erro rs into consideration. remark f clk : cpu/peripheral hardware clock frequency figure 11-5. a/d converter sa mpling and a/d conversion timing adcs wait period conversion time conversion time sampling sampling timing intad adcs 1 or ads rewrite sampling sar clear sar clear transfer to adcr, intad generation successive conversion chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 360 (3) 10-bit a/d conversion r esult register (adcr) this register is a 16-bit register that stores the a/d conversion result in t he select mode. the lower 6 bits are fixed to 0. each time a/d conversion ends, the conver sion result is loaded from the successive approximation register. the higher 8 bits of the conversion result are stored in fff1fh and the lower 2 bits are stored in the higher 2 bits of fff1eh. adcr can be read by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 11-6. format of 10-bit a/d conversion result register (adcr) symbol address: fff1fh, fff1eh after reset: 0000h r fff1fh fff1eh 0 0 0 0 0 0 adcr caution when writing to a/d conver ter mode register (adm), analog input channel speci fication register (ads), and a/d port configuration register (adpc) , the contents of adcr may become undefined. read the conversion result fo llowing conversion completion befo re writing to adm, ads, and adpc. using timing other than th e above may cause an incorrect conversion result to be read. (4) 8-bit a/d conversion result register (adcrh) this register is an 8-bit register that stores the a/d conversion result. the higher 8 bits of 10-bit resolution are stored. adcrh can be read by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 11-7. format of 8-bit a/d c onversion result register (adcrh) symbol adcrh address: fff1fh after reset: 00h r 76543210 caution when writing to a/d conver ter mode register (adm), analog input channel speci fication register (ads), and a/d port configuration register (adpc), the contents of adcrh may become undefined. read the conversion result followin g conversion completion before writing to adm, ads, and adpc. using timing other than the abo ve may cause an incorrect conversion result to be read. chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 361 (5) analog input channel specification register (ads) this register specifies the input channel of the analog voltage to be a/d converted. ads can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 11-8. format of analog input chan nel specification register (ads) (1/2) address: fff31h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 ads 0 adoas 0 0 ads3 ads2 ads1 ads0 { select mode (admd = 0) adoas ads3 ads2 ads1 ads0 analog input channel input source 0 0 0 0 0 ani0 p20/ani0 pin 0 0 0 0 1 ani1 p21/ani1 pin 0 0 0 1 0 ani2 p22/ani2 pin 0 0 0 1 1 ani3 p23/ani3 pin 0 0 1 0 0 ani4 p24/ani4 pin 0 0 1 0 1 ani5 p25/ani5 pin 0 0 1 1 0 ani6 p26/ani6 pin 0 0 1 1 1 ani7 p27/ani7 pin 0 1 0 0 0 ani8 p150/ani8 pin 0 1 0 0 1 ani9 p151/ani9 pin 0 1 0 1 0 ani10 p152/ani10 pin 0 1 0 1 1 ani11 p153/ani11 pin 1 pgao programmable gain amplifier output signal other than the above setting prohibited notes 1. setting permitted 2. setting prohibited cautions 1. be sure to clea r bits 4, 5, and 7 to ?0?. 2 set a channel to be used for a/d conversion in the input mode by using port mode registers 2, 15, and 8 (pm2, pm15, pm8). 3. do not set the pin that is set by adpc as digital i/o by ads. 4. select the output signal (pgao) of the programmable gain amplifier from pgai pin as the analog input after setting the operation of the pr ogrammable gain amplifier (refer to 11.4.1 basic operations of a/d converter). remarks 1. : don?t care 2. p20/ani0 to p27/ani9, p150/ani8, p151/ani9: 78k0r/kc3-l (44-pin) p20/ani0 to p27/ani9, p150/ani8 to p152/an i10: 78k0r/kc3-l (48-pin) and 78k0r/kd3-l p20/ani0 to p27/ani9, p150/ani8 to p153/ani11: 78k0r/ke3-l kc3-l (44-pin) kc3-l (48-pin) kd3-l ke3-l note 1 note 1 note 1 note 2 note 1 note 1 note 2 chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 362 figure 11-8. format of analog input chan nel specification register (ads) (2/2) address: fff31h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 ads 0 adoas 0 0 ads3 ads2 ads1 ads0 { scan mode (admd = 1) analog input channel adoas ads3 ads2 ads1 ads0 scan 0 scan 1 scan 2 scan 3 0 0 0 0 0 ani0 ani1 ani2 ani3 0 0 0 0 1 ani1 ani2 ani3 ani4 0 0 0 1 0 ani2 ani3 ani4 ani5 0 0 0 1 1 ani3 ani4 ani5 ani6 0 0 1 0 0 ani4 ani5 ani6 ani7 0 0 1 0 1 ani5 ani6 ani7 ani8 0 0 1 1 0 ani6 ani7 ani8 ani9 0 0 1 1 1 ani7 ani8 ani9 ani10 1 0 0 0 0 pgao ani0 ani1 ani2 1 0 0 0 1 pgao ani1 ani2 ani3 1 0 0 1 0 pgao ani2 ani3 ani4 1 0 0 1 1 pgao ani3 ani4 ani5 1 0 1 0 0 pgao ani4 ani5 ani6 1 0 1 0 1 pgao ani5 ani6 ani7 1 0 1 1 0 pgao ani6 ani7 ani8 1 0 1 1 1 pgao ani7 ani8 ani9 other than the above setting prohibited notes 1. setting permitted 2. setting prohibited cautions 1. be sure to clea r bits 4, 5, and 7 to ?0?. 2 set a channel to be used for a/d conversion in the input mode by using port mode registers 2, 15, and 8 (pm2, pm15, pm8). 3. do not set the pin that is set by adpc as digital i/o by ads. 4. select the output signal (pgao) of the pr ogrammable gain amplifier from pgai pin as the analog input after setting the operation of the pr ogrammable gain amplifier (refer to 11.4.1 basic operations of a/d converter). remarks 1. : don?t care 2. p20/ani0 to p27/ani9, p150/ani8, p151/ani9: 78k0r/kc3-l (44-pin) p20/ani0 to p27/ani9, p150/ani8 to p152/an i10: 78k0r/kc3-l (48-pin) and 78k0r/kd3-l p20/ani0 to p27/ani9, p150/ani8 to p153/ani11: 78k0r/ke3-l kc3-l (44-pin) kc3-l (48-pin) kd3-l ke3-l note 1 note 1 note 1 note 1 note 2 chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 363 (6) a/d port configuration register (adpc) this register switches the ani0/p20 to ani7/p27 and ani8/p150 to ani11/p153 pins to analog input of a/d converter or digital i/o of port. adpc can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 10h. figure 11-9. format of a/d port configuration register (adpc) address: f0017h after reset: 10h r/w symbol 7 6 5 4 3 2 1 0 adpc 0 0 0 adpc4 adpc3 adpc2 adpc1 adpc0 analog input (a)/digita l i/o (d) switching port 15 port 2 adp c4 adp c3 adp c2 adp c1 adp c0 ani11 /p153 ani10 /p152 ani9 /p151 ani8 /p150 ani7 /p27 ani6 /p26 ani5 /p25 ani4 /p24 ani3 /p23 ani2 /p22 ani1 /p21 ani0 /p20 0 0 0 0 0 a a a a a a a a a a a a 0 0 0 0 1 a a a a a a a a a a a d 0 0 0 1 0 a a a a a a a a a a d d 0 0 0 1 1 a a a a a a a a a d d d 0 0 1 0 0 a a a a a a a a d d d d 0 0 1 0 1 a a a a a a a d d d d d 0 0 1 1 0 a a a a a a d d d d d d 0 0 1 1 1 a a a a a d d d d d d d 0 1 0 0 0 a a a a d d d d d d d d 0 1 0 0 1 a a a d d d d d d d d d 0 1 0 1 0 a a d d d d d d d d d d 0 1 0 1 1 a d d d d d d d d d d d 1 0 0 0 0 d d d d d d d d d d d d other than the above setting prohibited cautions 1. set a channel to be u sed for a/d conversion in the input mode by usi ng port mode register 2 and 15 (pm2, pm15). 2. do not set the pin that is set by adpc as di gital i/o by the analog in put channel specification register (ads). remark p20/ani0 to p27/ani9, p150/ani8, p151/ani9: 78k0r/kc3-l (44-pin) p20/ani0 to p27/ani9, p150/ani8 to p152/an i10: 78k0r/kc3-l (48-pin) and 78k0r/kd3-l p20/ani0 to p27/ani9, p150/ani8 to p153/ani11: 78k0r/ke3-l chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 364 (7) port input mode register 8 (pim8) this register enables or disables the digital input of port 8 in 1-bit units. disable the digital input (used as analog input) to use the pgai pin as the analog input. enable the digital input to use the port function, or the external interrupt and time r hi-z control functions, because the digital input is disabled (used as analog input) in the initial state. pim8 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 11-10. format of port input mode register 8 (pim8) address: f0048h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pim8 0 0 0 0 pim83 pim82 pim81 pim80 pim8n selection of enabling or disabli ng p8n pin digital input (n = 0 to 3) 0 disables digital input (used as analog input) 1 enables digital input chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 365 (8) port mode registers 2, 15, and 8 (pm2, pm15, pm8) when using the ani0/p20 to ani7/p27, ani8/p150 to ani11/p153, and pgai/p80 pins for analog input port, set pm20 to pm27, pm150 to pm153, and pm80 to 1. the out put latches of p20 to p27, p150 to p153, and p80 at this time may be 0 or 1. if pm20 to pm27, pm150 to pm153, and pm80 are set to 0, they cannot be used as analog input port pins. pm2, pm15, and pm8 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh. caution if a pin is set as an analog input por t, not the pin level bu t ?0? is always read. remark p20/ani0 to p27/ani9, p150/ani8, p151/ani9: 78k0r/kc3-l (44-pin) p20/ani0 to p27/ani9, p150/ani8 to p152/an i10: 78k0r/kc3-l (48-pin) and 78k0r/kd3-l p20/ani0 to p27/ani9, p150/ani8 to p153/ani11: 78k0r/ke3-l figure 11-11. formats of port mode re gisters 2, 15, and 8 (pm2, pm15, pm8) address: fff22h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 address: fff28h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm8 1 1 1 1 pm83 pm82 pm81 pm80 address: fff2fh after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm15 1 1 1 1 pm153 pm152 pm151 pm150 pmmn pmn pin i/o mode selection (mn = 20 to 27, 150 to 153, 80 to 83) 0 output mode (output buffer on) 1 input mode (output buffer off) remark the figure shown above presents the format of port m ode register 2, 8 and 15 of 78k0r/ke3-l products. for the format of port mode register of other products, see (1) port mode registers (pmxx) in 4.3 registers controlling port function. chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 366 the ani0/p20 to ani7/p27, ani8/p150 to ani11/p153, a nd pgai/p80 pins are as shown below depending on the settings of adpc, ads, pm2, pm15, and pm8. table 11-3. setting functions of ani0/p20 to ani 7/p27, ani8/p150 to ani11/ p153, and pgai/p80 pins adpc pm2, pm15, and pm8 ads ani0/p20 to ani7/p27, ani8/p150 to ani11/p153, and pgai/p80 pins input mode ? digital input digital i/o selection output mode ? digital output selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited remark p20/ani0 to p27/ani9, p150/ani8, p151/ani9: 78k0r/kc3-l (44-pin) p20/ani0 to p27/ani9, p150/ani8 to p152/an i10: 78k0r/kc3-l (48-pin) and 78k0r/kd3-l p20/ani0 to p27/ani9, p150/ani8 to p153/ani11: 78k0r/ke3-l chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 367 11.4 a/d converter operations 11.4.1 basic operations of a/d converter <1> set bit 5 (adcen) of peripheral enable register 0 (per0) to 1 to start the supply of the input clock to the a/d converter. <2> set the a/d conversion time by using bits 5 to 1 (fr2 to fr0, lv1, and lv0) of adm, and set the operation mode by using bit 6 (admd) of adm. <3> set bit 0 (adce) of a/d converter mode register (adm) to 1 to start the oper ation of the a/d voltage comparator. <4> set the channels for a/d conversion to analog input by using the a/d port configuration register (adpc) and set to input mode by using port mode registers (pm2, pm15, and pm8). <5> set the programmable gain amplifier operation to set the programmable gain amplifier output (pgai pin) for the analog input channel (refer to 8.4.1 starting comparator and programmable gain amplifier operation ). <6> select one channel for a/d conversion using the analog input channel specification register (ads). <7> start the conversion operation by setting bit 7 (adcs) of adm to 1. (<8> to <14> are operations performed by hardware.) <8> the voltage input to the selected analog input c hannel is sampled by the sample & hold circuit. <9> when sampling has been done for a certain time, the sa mple & hold circuit is placed in the hold state and the sampled voltage is held until the a/ d conversion operation has ended. <10> bit 9 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <11> the voltage difference between the series resistor string voltage tap a nd sampled voltage is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set to 1. if the analog input is smaller than (1/2) av ref , the msb is reset to 0. <12> next, bit 8 of sar is automatically set to 1, and t he operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 9, as described below. ? bit 9 = 1: (3/4) av ref ? bit 9 = 0: (1/4) av ref the voltage tap and sampled voltage are compared and bit 8 of sar is manipulated as follows. ? sampled voltage voltage tap: bit 8 = 1 ? sampled voltage < voltage tap: bit 8 = 0 <13> comparison is continued in this way up to bit 0 of sar. <14> upon completion of the comparison of 10 bits, an effective digital result value remains in sar, and the result value is transferred to the a/d conversion resu lt register (adcr, adcrh) and then latched. at the same time, the a/d conversion end in terrupt request (intad) can also be generated. <15> repeat steps <8> to <14>, until adcs is cleared to 0. to stop the a/d converter, clear adcs to 0. to restart a/d conversion from the st atus of adce = 1, start from <7>. to start a/d conversion again when adce = 0, set adce to 1, wait for 1 s or longer, and start <7>. to change a channel of a/d conversion, start from <6>. caution make sure the period of <3> to <7> is 1 s or more. remark two types of a/d conversion re sult registers are available. ? adcr (16 bits): store 10-bit a/d conversion value ? adcrh (8 bits): store 8-bit a/d conversion value chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 368 figure 11-12. basic operation of a/d converter conversion time sampling time sampling a/d conversion undefined conversion result a/d converter operation sar adcr intad conversion result a/d conversion operations are performed continuously unti l bit 7 (adcs) of a/d converter mode register (adm) is reset (0) by software. if a write operation is performed to the analog input chan nel specification register (ads) during an a/d conversion operation, the conversion operation is in itialized, and if the adcs bit is set (1), conversion starts again from the beginning. reset signal generation clears the a/d conversion re sult register (adcr, adcrh) to 0000h or 00h. chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 369 11.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani 0 to ani11, pgai) and the theoretical a/d conversion result (stored in the 10-bit a/d conversion result regi ster (adcr)) is shown by the following expression. sar = int ( 1024 + 0.5) adcr = sar 64 or ( ? 0.5) v ain < ( + 0.5) where, int( ): function which returns integer part of value in parentheses v ain : analog input voltage av ref : av ref pin voltage adcr: a/d conversion result register (adcr) value sar: successive approximation register figure 11-13 shows the relationship between the analo g input voltage and the a/d conversion result. figure 11-13. relationship between analog i nput voltage and a/d conversion result 1023 1022 1021 3 2 1 0 ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h a/d conversion result sar adcr 1 2048 1 1024 3 2048 2 1024 5 2048 input voltage/av ref 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 remark ani0 to ani9: 78k0r/kc3-l (44-pin) ani0 to ani10: 78k0r/kc3-l (48-pin) and 78k0r/kd3-l ani0 to ani11: 78k0r/ke3-l v ain av ref av ref 1024 av ref 1024 adcr 64 adcr 64 chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 370 11.4.3 a/d converter operation modes the select mode and scan mode are provided as the a/d converter operation modes. (1) select mode one analog input specified by the anal og input channel specification register (ads), while the admd bit of a/d converter mode register (adm) is 0, is a/d converted. when a/d conversion is complete, the conversion result is stored in the a/d conversion result register (adcr) and the a/d conversion end interrupt request signal (intad) is generated. after a/d conversion has been completed, a/d conversion is repeated successively, unless the adcs bit is set to 0. if anything is written to adm or ads during conversion, a/ d conversion is aborted. in this case, a/d conversion is started again from the beginning. figure 11-14. example of select mode operation timing ani1 a/d conversion operation data 1 (ani1) data 2 (ani1) data 1 data 2 data 1 (ani1) data 2 (ani1) adcr, adcrh intad conversion start set adcs bit = 1 conversion stop set adcs bit = 0 data 3 (ani1) data 3 data 3 (ani1) data 4 (ani1) data 4 data 4 (ani1) conversion end chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 371 (2) scan mode the four analog input channels of sc ans 0 to 3, which are specified by the analog input channel specification register (ads), while the admd bit of a/d converter mode register (adm) is 1, are a/d converted successively. a/d conversion is performed in sequence, starting from the analog input channel specified by scan 0. when a/d conversion of one analog input is complete, the conv ersion result is stored in the a/d conversion result register (adcr) and the a/d conversion end in terrupt request signal (intad) is generated. the a/d conversion results of all the analog input channels are stored in adcr. it is therefore recommended to save the contents of adcr to ram, once a/d conv ersion of one analog input channel has been completed. after a/d conversion has been completed, a/d conversion is repeated successively, unless the adcs bit is set to 0. if anything is written to adm or ads during conversion, a/ d conversion is aborted. in this case, a/d conversion is started again from the anal og input channel of scan 0. figure 11-15. example of scan mode operation timing a/d conversion operation data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 6 (ani1) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) adcr, adcrh intad conversion start set adcs bit = 1 conversion stop set adcs bit = 0 ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 data 8 data 5 (ani0) data 7 (ani2) data 8 (ani3) data 5 (ani0) data 6 (ani1) data 7 (ani2) data 8 (ani3) chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 372 the setting methods are described below. <1> set bit 5 (adcen) of peripheral enable register 0 (per0) to 1. <2> select the conversion time by using bits 5 to 1 (fr2 to fr0, lv1, and lv 0) of adm, and select the operation mode by using bit 6 (admd) of adm. <3> set bit 0 (adce) of a/d converter mode register (adm) to 1. <4> set the channel to be used in the analog input m ode by using bits 4 to 0 (adpc4 to adpc0) of the a/d port configuration register (adpc), bits 7 to 0 (pm27 to pm20) of port mode register 2 (pm2), bits 3 to 0 (pm153 to pm150) of port mode register 15 (pm15), and bit 0 (pm80) of port mode register 8 (pm8). <5> set the programmable gain amplifier operation to set the programmable gain amplifier output (pgai pin) for the analog input channel (refer to 8.4.1 starting comparator and programmable gain amplifier operation ). <6> select a channel to be used by using bits 6 and 3 to 0 (adoas, ads3 to ads0) of the analog input channel specification register (ads). <7> set bit 7 (adcs) of adm to 1 to start a/d conversion. <8> when one a/d conversion has been completed, an interrupt request signal (intad) is generated. <9> transfer the a/d conversion data to the a/d conversion result register (adcr, adcrh). chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 373 11.5 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input vo ltage that can be identif ied. that is, the perce ntage of the analog input voltage per bit of digital output is called 1lsb (least si gnificant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same digita l code, so a quantization error cannot be avoided. note that the quantization erro r is not included in the overall error, zero -scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 11-16. overall error figur e 11-17. quanti zation error ideal line 0 ...... 0 1 ...... 1 digital output overall error analog input av ref 0 0......0 1 ...... 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av ref (4) zero-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (1/2lsb) when the digital output changes from 0......000 to 0......001. if the actual measurement value is greater than the theore tical value, it shows the difference between the actual measurement value of the analog in put voltage and the theoretical val ue (3/2lsb) when the digital output changes from 0??001 to 0??010. chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 374 (5) full-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (full-scale ? 3/2lsb) when the digital output chan ges from 1......110 to 1......111. (6) integral linearity error this shows the degree to which the conversion charac teristics deviate from the ideal linear relationship. it expresses the maximum value of the di fference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) differential linearity error while the ideal width of code output is 1lsb, this indi cates the difference between the actual measurement value and the ideal value. figure 11-18. zero-scale error figure 11-19. full-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av ref ? 3 full-scale error ideal line analog input (lsb) digital output (lower 3 bits) av ref ? 2av ref ? 1 av ref figure 11-20. integral linearity error figure 11-21. differential linearity error 0 av ref digital output analog input integral linearity error ideal line 1 ...... 1 0 ...... 0 0 av ref digital output analog input differential linearity error 1 ...... 1 0 ...... 0 ideal 1lsb width (8) conversion time this expresses the time from the start of samp ling to when the digital output is obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the anal og voltage to be sampled by the sample & hold circuit. sampling time conversion time chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 375 11.6 cautions for a/d converter (1) operating current in stop mode the a/d converter stops operating in the stop mode. at this time, th e operating current can be reduced by clearing bit 7 (adcs) and bit 0 (adce) of a/d converter mode register (adm) to 0. to restart from the standby status, clear bit 0 (adif) of interrupt request flag register 1l (if1l) to 0 and start operation. (2) input range of ani0 to ani11 observe the rated range of the ani0 to an i11 input voltage. if a voltage of av ref or higher and av ss or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. (3) conflicting operations <1> conflict between a/d conversion result regist er (adcr, adcrh) write and adcr or adcrh read by instruction upon the end of conversion adcr or adcrh read has priority. after the read op eration, the new co nversion result is written to adcr or adcrh. <2> conflict between adcr or adcrh write and a/d converter mode regi ster (adm) write, analog input channel specification register (ads), or a/d port configuration register (a dpc) write upon the end of conversion adm, ads, or adpc write has priority. adcr or adcrh write is not performed, nor is the conversion end interrupt signal (intad) generated. (4) noise countermeasures to maintain the 10-bit resolution, attent ion must be paid to noise input to the av ref pin and pins ani0 to ani11. <1> connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. <2> the higher the output impedance of the analog input source, the greater the influence. to reduce the noise, connecting external c as shown in figure 11-22 is recommended. <3> do not switch these pins wit h other pins during conversion. <4> the accuracy is improved if the halt mode is set immediately after the start of conversion. remark ani0 to ani9: 78k0r/kc3-l (44-pin) ani0 to ani10: 78k0r/kc3-l (48-pin) and 78k0r/kd3-l ani0 to ani11: 78k0r/ke3-l chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 376 figure 11-22. analog input pin connection reference voltage input c = 100 to 1,000 pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref av ss v ss ani0 to ani11 (5) ani0/p20 to ani7/p27 a nd ani8/p150 to ani11/p153 <1> the analog input pins (ani0 to an11) are also used as input port pins (p20 to p27, p150 to p153). when a/d conversion is performed with any of ani0 to ani11 selected, do not access p20 to p27 and p150 to p153 while conversion is in progress; otherwis e the conversion resolution may be degraded. it is recommended to select pins used as p20 to p27 and p150 to p153 starting with t he ani0/p20 that is the furthest from av ref . <2> if a digital pulse is applied to the pins adjacent to t he pins currently used for a/ d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. t herefore, do not apply a pulse to the pins adjacent to the pi n undergoing a/d conversion. (6) input impedance of ani0 to ani11 pins this a/d converter charges a sampling capacitor for sampling during sampling time. therefore, only a leakage current fl ows when sampling is not in progre ss, and a current that charges the capacitor flows during sampling. consequently, the input impedance fluctuates depending on whether sampling is in progress, and on the other states. to make sure that sampling is effective, however, it is recommended to keep the ou tput impedance of the analog input source to within 1 k , and to connect a capacitor of about 100 pf to the ani0 to ani11 pins (see figure 11- 22 ). (7) av ref pin input impedance a series resistor string of several tens of k is connected between the av ref and av ss pins. therefore, if the output impedance of t he reference voltage source is high, this will result in a series connection to the series resistor string between the av ref and av ss pins, resulting in a large reference voltage error. remark p20/ani0 to p27/ani9, p150/ani8, p151/ani9: 78k0r/kc3-l (44-pin) p20/ani0 to p27/ani9, p150/ani8 to p152/an i10: 78k0r/kc3-l (48-pin) and 78k0r/kd3-l p20/ani0 to p27/ani9, p150/ani8 to p153/ani11: 78k0r/ke3-l chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 377 (8) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if th e analog input channel specification register (ads) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pre-change analog input may be set just before the ads rewrit e. caution is therefore re quired since, at this time, when adif is read immediately after the ads rewrite, ad if is set despite the fact a/d conversion for the post- change analog input has not ended. when a/d conversion is stopped and then resumed, clear ad if before the a/d conversion operation is resumed. figure 11-23. timing of a/d conver sion end interrupt request generation ads rewrite (start of anin conversion) a/d conversion adcr adif anin anin anim anim anin anin anim anim ads rewrite (start of anim conversion) adif is set but anim conversion has not ended. remarks 1. 78k0r/kc3-l (44-pin): n = 0 to 9 78k0r/kc3-l (48-pin), 78k0r/kd3-l: n = 0 to 10 78k0r/ke3-l: n = 0 to 11 2. 78k0r/kc3-l (44-pin): m = 0 to 9 78k0r/kc3-l (48-pin), 78k0r/kd3-l: m = 0 to 10 78k0r/ke3-l: m = 0 to 11 (9) conversion results just after a/d conversion start the first a/d conversion value immediately after a/d conv ersion starts may not fall wit hin the rating range if the adcs bit is set to 1 within 1 s after the adce bit was set to 1, or if t he adcs bit is set to 1 with the adce bit = 0. take measures such as pollin g the a/d conversion end interrupt r equest (intad) and removing the first conversion result. (10) a/d conversion result regist er (adcr, adcrh) read operation when a write operation is performed to a/d converter mode register (adm), analog input channel specification register (ads), and a/d port config uration register (adpc), the c ontents of adcr and adcrh may become undefined. read the conversion result following conversion completion before writing to adm, ads, or adpc. using a timing other than the above may cause an incorrect conversion result to be read. chapter 11 a/d converter preliminary user?s manual u19291ej1v0ud 378 (11) internal equivalent circuit the equivalent circuit of the analog input block is shown below. figure 11-24. internal equi valent circuit of anin pin anin c1 c2 r1 table 11-4. resistance and capacitance valu es of equivalent circui t (reference values) av ref mode r1 c1 c2 standard 5.2 k high speed 1 5.2 k 4.0 v v dd 5.5 v high speed 2 7.8 k standard 18.6 k 2.7 v v dd < 4.0 v high speed 2 7.8 k 1.8 v v dd < 4.0 v voltage boost 169.8 k 8 pf 6.26 pf remarks 1. the resistance and capacitance values shown in table 11-4 are not guaranteed values. 2. 78k0r/kc3-l (44-pin): n = 0 to 9 78k0r/kc3-l (48-pin): n = 0 to 10 78k0r/kd3-l: n = 0 to 10 78k0r/ke3-l: n = 0 to 11 preliminary user?s manual u19291ej1v0ud 379 chapter 12 serial array unit the serial array unit has four serial channels per unit and can use two or more of various serial interfaces (3-wire serial (csi), uart, and simplified i 2 c) in combination. function assignment of each channel support ed by the 78k0r/kx3-l is as shown below. channel used as csi used as uart used as simplified i 2 c 0 csi00 ? 1 csi01 uart0 (supporting lin-bus) ? 2 csi10 iic10 3 ? uart1 ? (example of combination) when ?uart0? is used for c hannels 0 and 1, csi00 and csi01 cannot be used, but csi10, uart1, or iic10 can be used. 12.1 functions of serial array unit each serial interface supported by the 78k0r/kx3-l has the following features. 12.1.1 3-wire serial i/o (csi00, csi01, csi10) this is a clocked communication function that uses thr ee lines: serial clock (sck) and serial data (si and so) lines. [data transmission/reception] ? data length of 7 or 8 bits ? phase control of transmit/receive data ? msb/lsb first selectable ? level setting of transmit/receive data [clock control] ? master/slave selection ? phase control of i/o clock ? setting of transfer period by prescaler and internal counter of each channel ? maximum transfer rate during master communication: max. f clk /4, during slave communication: max. f mck /6 note [interrupt function] ? transfer end interrupt/buffer empty interrupt [error detection flag] ? overrun error note use the clocks within a range sa tisfying the sck cycle time (t kcy ) characteristics (see chapter 28 electrical specifi cations (target) ). chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 380 12.1.2 uart (uart0, uart1) this is a start-stop synchronization function using two lines: serial data transmission (t x d) and serial data reception (r x d) lines. it transmits or receives data in asynchr onization with the party of communication (by using an internal baud rate). full-duplex uart communication ca n be realized by using two channels, one dedicated to transmission (even channel) and the other to reception (odd channel). [data transmission/reception] ? data length of 5, 7, or 8 bits ? select the msb/lsb first ? level setting of transmit/recei ve data and select of reverse ? parity bit appending and parity check functions ? stop bit appending [interrupt function] ? transfer end interrupt/buffer empty interrupt ? error interrupt in case of framing error, parity error, or overrun error [error detection flag] ? framing error, parity error, or overrun error the lin-bus is accepted in uart0 (0 and 1 channels) [lin-bus functions] ? wakeup signal detection ? sync break field (sbf) detection ? sync field measurement, baud rate calculation 12.1.3 simplified i 2 c (iic10) this is a clocked communication function to communicate wit h two or more devices by using two lines: serial clock (scl) and serial data (sda). this simplified i 2 c is designed for single communicati on with a device such as eeprom, flash memory, or a/d converter, and ther efore, it functions only as a master and does not have a function to detect wait states. make sure by using software, as well as operating the control regist ers, that the ac specif ications of the start and stop conditions are observed. [data transmission/reception] ? master transmission, master reception (onl y master function with a single master) ? ack output function note and ack detection function ? data length of 8 bits (when an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is used for r/w control.) ? manual generation of start condition and stop condition [interrupt function] ? transfer end interrupt [error detection flag] ? parity error (ack error) * [functions not supported by simplified i 2 c] ? slave transmission, slave reception ? arbitration loss detection function ? wait detection functions note when receiving the last data, ack will not be output if 0 is written to the soe02 (soe0 register) bit and serial communication data output is stopped. see the processing flow in 12.7.3 (2) for details. remark to use an i 2 c bus of full function, see chapter 13 serial interface iica . external interrupt (intp0) or timer array unit taus is used. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 381 12.2 configuration of serial array unit the serial array unit includes the following hardware. table 12-1. configuration of serial array unit item configuration shift register 8 bits buffer register lower 8 bits of serial data register 0n (sdr0n) note serial clock i/o sck00, sck01, sck10 pins (for 3-wire serial i/o), scl10 pin (for simplified i 2 c) serial data input si00, si01, si10 pins (for 3-wire serial i/o), r x d0 pin (for uart supporting lin-bus), r x d1 pins (for uart) serial data output so00, so01, so10 pins (for 3-wire serial i/o), t x d0 pin (for uart supporting lin-bus), t x d1 pin (for uart), output controller serial data i/o sda10 pin (for simplified i 2 c) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 382 figure 12-1 shows the block diagram of the serial array unit. figure 12-1. block diagram of serial array unit inttm02 prs 013 4 prs 003 prs 012 prs 011 prs 010 prs 002 prs 001 prs 000 4 f clk f clk /2 0 to f clk /2 11 f clk /2 0 to f clk /2 11 cks00 md001 ccs00 sts00 md002 0 soe02 soe01 soe00 pm75 sau0en se03 se02 se01 se00 st03 st02 st01 st00 ss03 ss02 ss01 ss00 txe 00 rxe 00 dap 00 ckp 00 eoc 00 fect 00 pect 00 ovct 00 ptc 001 slc 000 ptc 000 dir 00 slc 001 dls 002 dls 001 dls 000 tsf 00 ovf 00 bff 00 fef 00 pef 00 ck01 ck00 mck tclk sck ck01 ck00 ck01 ck00 ck01 ck00 snfen 10 snfen 00 snfen00 snfen10 pm73 0 sol02 0 sol00 1 1 cko02 cko01 cko00 so02 so01 so00 0 0 00 0 0 00 serial output enable register 0 (soe0) serial channel enable status register 0 (se0) serial channel stop register 0 (st0) serial channel start register 0 (ss0) noise filter enable register 0 (nfen0) serial output level register 0 (sol0) serial output register 0 (so0) serial clock select register 0 (sps0) selector selector peripheral enable register 0 (per0) prescaler shift register serial data register 00 (sdr00) (buffer register block) (clock division setting block) output latch (p73) selector clock controller selector interrupt controller output controller communication controller serial flag clear trigger register 00 (sir00) communication status error information clear serial status register 00 (ssr00) error controller channel 0 (lin-bus supported) channel 1 (lin-bus supported) edge/level detection serial communication operation setting register 00 (scr00) when uart0 serial mode register 00 (smr00) communication controller error controller edge/level detection channel 2 channel 3 edge/level detection edge/level detection communication controller communication controller error controller when uart1 output latch (p75) mode selection csi00 or uart0 (for transmission) serial data output pin (when csi00: so00) (when uart0: t x d0) serial transfer end interrupt (when csi00: intcsi00) (when uart0: intst0) edge detection serial clock i/o pin (when csi00: sck00) serial data input pin (when csi00: si00) (when uart0: rxd0) serial transfer end interrupt (when csi01: intcsi01) (when uart0: intsr0) mode selection csi01 or uart0 (for reception) serial transfer error interrupt (intsre0) serial data output pin (when csi01: so01) serial data input pin (when csi01: si01) serial clock i/o pin (when csi01: sck01) selector serial data input pin (when csi10: si10) (when iic10: sda10) (when uart1: r x d1) mode selection csi10 or iic10 or uart1 (for transmission) serial clock i/o pin (when csi10: sck10) (when iic10: scl10) noise elimination enabled/ disabled serial data output pin (when csi10: so10) (when iic10: sda10) (when uart1: t x d1) serial transfer end interrupt (when csi10: intcsi10) (when iic10: intiic10) (when uart1: intst1) mode selection uart1 (for reception) serial transfer end interrupt (when uart1: intsr1) serial transfer error interrupt (intsre1) noise elimination enabled/ disabled chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 383 (1) shift register this is an 8-bit register that converts para llel data into serial data or vice versa. during reception, it converts data inpu t to the serial pin into parallel data. when data is transmitted, the value set to this register is output as serial data from the serial output pin. the shift register cannot be dire ctly manipulated by program. to read or write the shift register, use the lo wer 8 bits of serial data register 0n (sdr0n). 7 6 5 4 3 2 1 0 shift register (2) lower 8 bits of the seria l data register 0n (sdr0n) sdr0n is the transmit/receive data regist er (16 bits) of channel n. bits 7 to 0 function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (mck). when data is received, parallel data converted by the shift register is stored in the lower 8 bits. when data is to be transmitted, set transmit to be transferred to the shift register to the lower 8 bits. the data stored in the lower 8 bits of this register is as follows, depending on the setting of bits 0 to 2 (dls0n0 to dls0n2) of the scr0n register, regardl ess of the output s equence of the data. ? 5-bit data length (stored in bits 0 to 4 of sdr0n register) (settable in uart mode only) ? 7-bit data length (stored in bits 0 to 6 of sdr0n register) ? 8-bit data length (stored in bits 0 to 7 of sdr0n register) sdr0n can be read or written in 16-bit units. the lower 8 bits of sdr0n of sdr0n can be read or written note as the following sfr, depending on the communication mode. ? csip communication ? siop (csip data register) ? uartq reception ? rxdq (uartq receive data register) ? uartq transmission ? txdq (uartq transmit data register) ? iic10 communication ? sio10 (iic10 data register) reset signal generation clears this register to 0000h. remarks 1. after data is received, ?0? is stored in bits 0 to 7 in bit portions that exceed the data length. 2. n: channel number (n = 0 to 3), p: csi number (p = 00, 01, 10), q: uart number (q = 0, 1) note writing in 8-bit units is prohibited when the operation is stopped (se0n = 0). chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 384 figure 12-2. format of serial data register 0n (sdr0n) address: fff10h, fff11h (sdr00), fff12h, fff13h (sdr01), after reset: 0000h r/w fff44h, fff45h (sdr02), fff46h, fff47h (sdr03) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n 0 (n = 0 to 3) 7 6 5 4 3 2 1 0 shift register caution be sure to clear bit 8 to ?0?. remarks 1. for the function of the hi gher 7 bits of sdr0n, see 12.3 registers controlling serial array unit . 2. n: channel number (n = 0 to 3), fff11h (sdr00) fff10h (sdr00) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 385 12.3 registers controlling serial array unit serial array unit is controlled by the following registers. ? peripheral enable register 0 (per0) ? serial clock select register 0 (sps0) ? serial mode register 0n (smr0n) ? serial communication operation setting register 0n (scr0n) ? serial data register 0n (sdr0n) ? serial status register 0n (ssr0n) ? serial flag clear trigger register 0n (sir0n) ? serial channel enable status register 0 (se0) ? serial channel start register 0 (ss0) ? serial channel stop register 0 (st0) ? serial output enable register 0 (soe0) ? serial output level register 0 (sol0) ? serial output register 0 (so0) ? input switch control register (isc) ? noise filter enable register 0 (nfen0) ? port input mode registers 3, 7 (pim3, pim7) ? port output mode registers 3, 7 (pom3, pom7) ? port mode registers 3, 7 (pm3, pm7) ? port registers 3, 7 (p3, p7) remark n: channel number (n = 0 to 3) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 386 (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripheral hardware macro. clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. when serial array unit is used, be sure to set bit 2 (sau0en) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 12-3. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> 6 <5> <4> 3 <2> 1 0 per0 rtcen 0 adcen iicaen 0 sau0en 0 0 sau0en control of serial array unit input clock supply 0 stops supply of input clock. ? sfr used by serial array unit cannot be written. ? serial array unit is in the reset status. 1 supplies input clock. ? sfr used by serial array unit can be read/written. cautions 1. when setting serial array unit, be sure to set sau0en to 1 fi rst. if sau0en = 0, writing to a control register of serial array unit is ignored, and, even if the register is read, only the default value is read (except for input switch control register (isc), noise filter enable register (nfen0), port input mode registers (pim3, pim7), port output mode registers (pom3, pom7), port mode registers (pm3 , pm7), and port registers (p3, p7)). 2. after setting the per0 register to 1, be su re to set the sps0 register after 4 or more clocks have elapsed. 3. be sure to clear bits 0, 1, 3, and 6 (bits 0, 1, 3, 4, and 6 for 44-pin products of 78k0r/kc3-l) of per0 register to 0. (2) serial clock select register 0 (sps0) sps0 is a 16-bit register that is us ed to select two types of operation cl ocks (ck00, ck01) that are commonly supplied to each channel. ck01 is selected by bits 7 to 4 of sps0, and ck00 is selected by bits 3 to 0. rewriting sps0 is prohibited when the register is in operation (when se0n = 1). sps0 can be set by a 16-bit memo ry manipulation instruction. the lower 8 bits of sps0 can be set with an 8-bi t memory manipulation instruction with sps0l. reset signal generation clears this register to 0000h. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 387 figure 12-4. format of serial clock select register 0 (sps0) address: f0126h, f0127h (sps0), f0166h, f0167h (sps1) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sps0 0 0 0 0 0 0 0 0 prs 013 prs 012 prs 011 prs 010 prs 003 prs 002 prs 001 prs 000 section of operation clock (ck0p) note 1 prs 0p3 prs 0p2 prs 0p1 prs 0p0 f clk = 2 mhz f clk = 5 mhz f clk = 10 mhz f clk = 20 mhz 0 0 0 0 f clk 2 mhz 5 mhz 10 mhz 20 mhz 0 0 0 1 f clk /2 1 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 0 f clk /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 0 0 1 1 f clk /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 0 1 0 0 f clk /2 4 125 khz 313 khz 625 khz 1.25 mhz 0 1 0 1 f clk /2 5 62.5 khz 156 khz 313 khz 625 khz 0 1 1 0 f clk /2 6 31.3 khz 78.1 khz 156 khz 313 khz 0 1 1 1 f clk /2 7 15.6 khz 39.1 khz 78.1 khz 156 khz 1 0 0 0 f clk /2 8 7.81 khz 19.5 khz 39.1 khz 78.1 khz 1 0 0 1 f clk /2 9 3.91 khz 9.77 khz 19.5 khz 39.1 khz 1 0 1 0 f clk /2 10 1.95 khz 4.88 khz 9.77 khz 19.5 khz 1 0 1 1 f clk /2 11 977 hz 2.44 khz 4.88 khz 9.77 khz 1 1 1 1 inttm02 note 2 other than above setting prohibited notes 1. when changing the clock selected for f clk (by changing the system clock control register (ckc) value), do so after having stopped (st0 = 000fh) t he operation of the serial array unit (sau). when selecting inttm02 for the operation clock, also stop the timer array unit taus (tt0 = 00ffh). 2. sau can be operated at a fixed division rati o of the subsystem cloc k, regardless of the f clk frequency (main system clock, subsystem clock), by setting the tis02 bit of the tis0 register of taus to 1, selecting f sub /4 for the input clock, and selecting inttm 02 using the sps0 register. when changing f clk , however, sau and taus must be stopped as described in note 1 above. cautions 1. be sure to clear bits 15 to 8 to ?0?. 2. after setting the per0 register to 1, be su re to set the sps0 register after 4 or more clocks have elapsed. remarks 1. f clk : cpu/peripheral hardware clock frequency f sub : subsystem clock frequency 2. p = 0, 1 chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 388 (3) serial mode register 0n (smr0n) smr0n is a register that sets an oper ation mode of channel n. it is al so used to select an operation clock (mck), specify whether the serial clock (sck) may be inpu t or not, set a start trigger, an operation mode (csi, uart, or i 2 c), and an interrupt source. this register is also us ed to invert the level of the receive data only in the uart mode. rewriting smr0n is prohibited when the register is in operation (when se0n = 1). however, the md0n0 bit can be rewritten during operation. smr0n can be set by a 16-bit memory manipulation instruction. reset signal generation sets this register to 0020h. figure 12-5. format of serial m ode register 0n (smr0n) (1/2) address: f0110h, f0111h (smr00) to f0116h, f0117h (smr03) after reset: 0020h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks 0n ccs 0n 0 0 0 0 0 sts 0n 0 sis 0n0 1 0 0 md 0n2 md 0n1 md 0n0 cks 0n selection of operation cl ock (mck) of channel n 0 prescaler output clock ck00 set by prs register 1 prescaler output clock ck01 set by prs register operation clock mck is used by the edge detector. in addition, depending on the setting of the ccs0n bit and the higher 7 bits of the sdr0n register, a transfer clock (tclk) is generated. ccs 0n selection of transfer clock (tclk) of channel n 0 divided operation clock mck specified by cks0n bit 1 clock input from sck pin (slave transfer in csi mode) transfer clock tclk is used for the sh ift register, communication controller, output controller, interrupt controller, and error controller. when ccs0n = 0, the division ratio of mck is set by the higher 7 bits of the sdr0n register. sts 0n selection of start trigger source 0 only software trigger is valid (selected for csi, uart transmission, and simplified i 2 c). 1 valid edge of r x d pin (selected for uart reception) transfer is started when the above source is satisfied after 1 is set to the ss0 register. caution be sure to clear bits 13 to 9, 7, 4, and 3 to ?0?. be sure to set bit 5 to ?1?. remark n: channel number (n = 0 to 3) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 389 figure 12-5. format of serial m ode register 0n (smr0n) (2/2) address: f0110h, f0111h (smr00) to f0116h, f0117h (smr03) after reset: 0020h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks 0n ccs 0n 0 0 0 0 0 sts 0n 0 sis 0n0 1 0 0 md 0n2 md 0n1 md 0n0 sis 0n0 controls inversion of level of receive data of channel n in uart mode 0 falling edge is detected as the start bit. the input communication data is captured as is. 1 rising edge is detected as the start bit. the input communication data is inverted and captured. md 0n2 md 0n1 setting of operation mode of channel n 0 0 csi mode 0 1 uart mode 1 0 simplified i 2 c mode 1 1 setting prohibited md 0n0 selection of interrupt source of channel n 0 transfer end interrupt 1 buffer empty interrupt for successive transmission, the next transmit data is written by setting md0n0 to 1 when sdr0n data has run out. remark n: channel number (n = 0 to 3) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 390 (4) serial communication operati on setting register 0n (scr0n) scr0n is a communication operation setting regi ster of channel n. it is used to set a data transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit, stop bit, and data length. rewriting scr0n is prohibited when the register is in operation (when se0n = 1). scr0n can be set by a 16-bit memory manipulation instruction. reset signal generation sets this register to 0087h. figure 12-6. format of serial communication operation setting regist er 0n (scr0n) (1/3) address: f0118h, f0119h (scr00) to f011eh, f011fh (scr03) after reset: 0087h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe 0n rxe 0n dap 0n ckp 0n 0 eoc 0n ptc 0n1 ptc 0n0 dir 0n 0 slc 0n1 slc 0n0 0 dls 0n2 dls 0n1 dls 0n0 txe 0n rxe 0n setting of operation mode of channel n 0 0 does not start communication. 0 1 reception only 1 0 transmission only 1 1 transmission/reception dap 0n ckp 0n selection of data and clock phase in csi mode 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sckp sop si p input timing 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sckp sop si p input timing 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sckp sop si p input timing 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sckp sop si p input timing be sure to set dap0n, ckp0n = 0, 0 in the uart mode and simplified i 2 c mode. caution be sure to clear bits 3, 6, and 11 to ?0?. be sure to set bit 2 to ?1?. remark n: channel number (n = 0 to 3), p: csi number (p = 00, 01, 10) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 391 figure 12-6. format of serial communication operation setting regist er 0n (scr0n) (2/3) address: f0118h, f0119h (scr00) to f011eh, f011fh (scr03) after reset: 0087h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe 0n rxe 0n dap 0n ckp 0n 0 eoc 0n ptc 0n1 ptc 0n0 dir 0n 0 slc 0n1 slc 0n0 0 dls 0n2 dls 0n1 dls 0n0 eoc 0n selection of masking of error interrupt signal (intsrex (x = 0 , 1)) 0 masks error interrupt intsrex (intsrx is not masked). 1 enables generation of error interrupt intsre x (intsrx is masked if an error occurs). set eoc0n = 0 in the csi mode, simplified i 2 c mode, and during uart transmission. set eoc0n = 1 during uart reception. setting of parity bit in uart mode ptc 0n1 ptc 0n0 transmission reception 0 0 does not output the parity bit. receives without parity 0 1 outputs 0 parity. no parity judgment 1 0 outputs even parity. judged as even parity. 1 1 outputs odd parity. judges as odd parity. be sure to set ptc0n1, ptc0n0 = 0, 0 in the csi mode and simplified i 2 c mode. dir 0n selection of data transfer sequence in csi and uart modes 0 inputs/outputs data with msb first. 1 inputs/outputs data with lsb first. be sure to clear dir0n = 0 in the simplified i 2 c mode. slc 0n1 slc 0n0 setting of stop bit in uart mode 0 0 no stop bit 0 1 stop bit length = 1 bit 1 0 stop bit length = 2 bits 1 1 setting prohibited when the transfer end interrupt is selected, the interr upt is generated when all stop bits have been completely transferred. set 1 bit (slc0n1, slc0n0 = 0, 1) during uart reception and in the simplified i 2 c mode. set no stop bit (slc0n1, slc0n0 = 0, 0) in the csi mode. caution be sure to clear bits 3, 6, and 11 to ?0?. be sure to set bit 2 to ?1?. remark n: channel number (n = 0 to 3) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 392 figure 12-6. format of serial communication operation setting regist er 0n (scr0n) (3/3) address: f0118h, f0119h (scr00) to f011eh, f011fh (scr03) after reset: 0087h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe 0n rxe 0n dap 0n ckp 0n 0 eoc 0n ptc 0n1 ptc 0n0 dir 0n 0 slc 0n1 slc 0n0 0 dls 0n2 dls 0n1 dls 0n0 dls 0n2 dls 0n1 dls 0n0 setting of data length in csi and uart modes 1 0 0 5-bit data length (stored in bits 0 to 4 of sdr0n register) (settable in uart mode only) 1 1 0 7-bit data length (stored in bits 0 to 6 of sdr0n register) 1 1 1 8-bit data length (stored in bits 0 to 7 of sdr0n register) other than above setting prohibited be sure to set dls0n0 = 1 in the simplified i 2 c mode. caution be sure to clear bits 3, 6, and 11 to ?0?. be sure to set bit 2 to ?1?. remark n: channel number (n = 0 to 3) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 393 (5) higher 7 bits of the seria l data register 0n (sdr0n) sdr0n is the transmit/receive data regist er (16 bits) of channel n. bits 7 to 0 function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (mck). if the ccs0n bit of serial mode register 0n (smr0n) is cleared to 0, the clock set by dividing the operating clock by the higher 7 bits of sdr 0n is used as the transfer clock. for the function of the lower 8 bits of sdr0n, see 12.2 configuration of serial array unit . sdr0n can be read or written in 16-bit units. however, the higher 7 bits can be written or read only when the operation is stopped (se0n = 0). during operation (se0n = 1), a value is written only to the lower 8 bits of sdr0n. when sdr0n is read during operation, 0 is always read. reset signal generation clears this register to 0000h. figure 12-7. format of serial data register 0n (sdr0n) address: fff10h, fff11h (sdr00), fff12h, fff13h (sdr01), after reset: 0000h r/w fff44h, fff45h (sdr02), fff46h, fff47h (sdr03) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n 0 sdr0n[15:9] transfer clock setting by dividing the oper ating clock (mck) 0 0 0 0 0 0 0 mck/2 0 0 0 0 0 0 1 mck/4 0 0 0 0 0 1 0 mck/6 0 0 0 0 0 1 1 mck/8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 mck/254 1 1 1 1 1 1 1 mck/256 cautions 1. be sure to clear bit 8 to ?0?. 2. setting sdr0n[15:9] = (0000000b, 0000001 b) is prohibited when uart is used. remarks 1. for the function of the lower 8 bits of sdr0n, see 12.2 configuration of serial array unit . 2. n: channel number (n = 0 to 3) fff11h (sdr00) fff10h (sdr00) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 394 (6) serial status register 0n (ssr0n) ssr0n is a register that indicates the communication status and error occurrence status of channel n. the errors indicated by this register are a fr aming error, parity error, and overrun error. ssr0n can be read by a 16-bit memory manipulation instruction. the lower 8 bits of ssr0n can be set with an 8-bit memory manipulation instruction with ssr0nl. reset signal generation clears this register to 0000h. figure 12-8. format of serial st atus register 0n (ssr0n) (1/2) address: f0100h, f0101h (ssr00) to f0106h, f0107h (ssr03) after reset: 0000h r symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssr0n 0 0 0 0 0 0 0 0 0 tsf 0n bff 0n 0 0 fef 0n pef 0n ovf 0n tsf 0n communication status indica tion flag of channel n 0 communication is not under execution. 1 communication is under execution. because this flag is an updating flag, it is automatically cleared when the communication operation is completed. this flag is cleared also when the st0n/ss0n bit is set to 1. bff 0n buffer register status indication flag of channel n 0 valid data is not stored in the sdr0n register. 1 valid data is stored in the sdr0n register. this is an updating flag. it is automatic ally cleared when transfer from the sdr 0n register to the shift register is completed. during reception, it is automatically clear ed when data has been read from the sdr0n register. this flag is cleared also when the st0n/ss0n bit is set to 1. this flag is automatically set if transmit data is writt en to the sdr0n register when the txe0n bit of the scr0n register = 1 (transmission or reception mode in each communi cation mode). it is automatically set if receive data is stored in the sdr0n register when the rxe0n bit of t he scr0n register = 1 (transmission or reception mode in each communication mode). it is also set in case of a reception error. if data is written to the sdr0n register when bff0n = 1, t he transmit/receive data stored in the register is discarded and an overrun error (ovf0n = 1) is detected. remark n: channel number (n = 0 to 3) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 395 figure 12-8. format of serial st atus register 0n (ssr0n) (2/2) address: f0100h, f0101h (ssr00) to f0106h, f0107h (ssr03) after reset: 0000h r symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssr0n 0 0 0 0 0 0 0 0 0 tsf 0n bff 0n 0 0 fef 0n pef 0n ovf 0n fef 0n framing error detecti on flag of channel n 0 no error occurs. 1 a framing error occurs during uart reception. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 396 (7) serial flag clear trigger register 0n (sir0n) sir0n is a trigger register that is used to clear each error flag of channel n. when each bit (fect0n, pect0n, ovct0n) of this register is set to 1, the corresponding bit (fef0n, pef0n, ovf0n) of serial status register 0n is cleared to 0. because sir0n is a trigger register, it is cleared immediately when the corresponding bit of ssr0n is cleared. sir0n can be set by a 16-bit memory manipulation instruction. the lower 8 bits of sir0n can be set with an 8-bi t memory manipulation instruction with sir0nl. reset signal generation clears this register to 0000h. figure 12-9. format of serial flag clear trigger register 0n (sir0n) address: f0108h, f0109h (sir00) to f010eh, f010fh (sir03) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sir0n 0 0 0 0 0 0 0 0 0 0 0 0 0 fec t0n pec t0n ovc t0n fec t0n clear trigger of fram ing error of channel n 0 no trigger operation 1 clears the fef0n bit of the ssr0n register to 0. pec t0n clear trigger of parity error flag of channel n 0 no trigger operation 1 clears the pef0n bit of the ssr0n register to 0. ovc t0n clear trigger of overrun error flag of channel n 0 no trigger operation 1 clears the ovf0n bit of the ssr0n register to 0. caution be sure to clear bits 15 to 3 to ?0?. remarks 1. n: channel number (n = 0 to 3) 2. when the sir0n register is read, 0000h is always read. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 397 (8) serial channel enable status register 0 (se0) se0 indicates whether data transmission/reception ope ration of each channel is enabled or stopped. when 1 is written a bit of serial channel start register 0 ( ss0), the corresponding bit of this register is set to 1. when 1 is written a bit of serial channel stop regi ster 0 (st0), the corresponding bit is cleared to 0. channel n that is enabled to operate cannot rewrite by software the value of ck o0n of the serial output register 0 (so0) to be described below, and a value refl ected by a communication oper ation is output from the serial clock pin. channel n that stops operation can set the value of cko 0n of the so0 register by software and output its value from the serial clock pin. in this way, any waveform , such as that of a start condition/stop condition, can be created by software. se0 can be read by a 16-bit memory manipulation instruction. the lower 8 bits of se0 can be set with an 1-bit or 8-bit memory manipulation instruction with se0l. reset signal generation clears this register to 0000h. figure 12-10. format of serial channe l enable status register 0 (se0) address: f0120h, f0121h after reset: 0000h r symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 se0 0 0 0 0 0 0 0 0 0 0 0 0 se0 3 se0 2 se0 1 se0 0 se0 n indication of operation enable/stop status of channel n 0 operation stops (stops with the values of the control r egister and shift register, and the statuses of the serial clock i/o pin, serial data output pin, and the fef, pef, and ovf error flags retained note ). 1 operation is enabled. note bits 6 and 5 (tsf0n, bff0n) of the ssr0n register are cleared. remark n: channel number (n = 0 to 3) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 398 (9) serial channel start register 0 (ss0) ss0 is a trigger register that is used to enab le starting communication/count by each channel. when 1 is written a bit of this register (ss0n), the corre sponding bit (se0n) of serial channel enable status register 0 (se0) is set to 1. because ss0n is a trigger bit, it is cleared immediately when se0n = 1. ss0 can be set by a 16-bit memory manipulation instruction. the lower 8 bits of ss0 can be set with an 1-bit or 8-bit memory manipulation instruction with ss0l. reset signal generation clears this register to 0000h. figure 12-11. format of serial channel start register 0 (ss0) address: f0122h, f0123h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 ss01 ss00 ss0n operation start trigger of channel n 0 no trigger operation 1 sets se0n to 1 and enters the communication wait st atus (if a communication oper ation is already under execution, the operation is stopped and the start condition is awaited). caution be sure to clear bits 15 to 4 to ?0?. remarks 1. n: channel number (n = 0 to 3) 2. when the ss0 register is read, 0000h is always read. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 399 (10) serial channel stop register 0 (st0) st0 is a trigger register that is used to enab le stopping communication/count by each channel. when 1 is written a bit of this regi ster (st0n), the corresponding bit (se0n) of serial channel enable status register 0 (se0) is cleared to 0. because st0n is a trigger bit, it is cleared immediately when se0n = 0. st0 can set written by a 16-bit memory manipulation instruction. the lower 8 bits of st0 can be set with an 1-bit or 8-bit memory manipulation instruction with st0l. reset signal generation clears this register to 0000h. figure 12-12. format of serial channel stop register 0 (st0) address: f0124h, f0125h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 st0 0 0 0 0 0 0 0 0 0 0 0 0 st0 3 st0 2 st0 1 st0 0 st0n operation stop trigger of channel n 0 no trigger operation 1 clears se0n to 0 and stops the communication operation. (stops with the values of the contro l register and shift register, and the st atuses of the serial clock i/o pin, serial data output pin, and the fef, pef, and ovf error flags retained note ). note bits 6 and 5 (tsf0n, bff0n) of the ssr0n register are cleared. caution be sure to clear bits 15 to 4 to ?0?. remarks 1. n: channel number (n = 0 to 3) 2. when the st0 register is read, 0000h is always read. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 400 (11) serial output enable register 0 (soe0) soe0 is a register that is used to enable or stop output of the serial comm unication operation of each channel. channel n that enables serial output cannot rewrite by software the value of so0n of the serial output register 0 (so0) to be described below, and a value reflected by a communication operation is output from the serial data output pin. for channel n, whose serial output is stopped, the so0n value of the so0 register can be set by software, and that value can be output from the serial data output pin. in this way, any waveform of the start condition and stop condition can be created by software. soe0 can be set by a 16-bit memory manipulation instruction. the lower 8 bits of soe0 can be set with an 1-bit or 8-bit memory manipulation instruction with soe0l. reset signal generation clears this register to 0000h. figure 12-13. format of serial output enable register 0 (soe0) address: f012ah, f012bh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe 02 soe 01 soe 00 soe 0n serial output enable/disable of channel n 0 stops output by serial communication operation. 1 enables output by serial communication operation. caution be sure to clear bits 15 to 3 to ?0?. remark n: channel number (n = 0 to 2) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 401 (12) serial output register 0 (so0) so0 is a buffer register for serial output of each channel. the value of bit n of this regi ster is output from the serial data output pin of channel n. the value of bit (n + 8) of this register is outp ut from the serial clock output pin of channel n. so0n of this register can be rewritten by software only when serial output is disabled (soe0n = 0). when serial output is enabled (soe0n = 1), rewriting by softw are is ignored, and the value of the register can be changed only by a serial communication operation. cko0n of this register can be rewritten by software only when the channel operation is stopped (se0n = 0). while channel operation is enabled (se0n = 1), rewriting by software is ignored, and the value of cko0n can be changed only by a serial communication operation. when using the p30/so10/txd1 , p31/si10/rxd1/sda10/intp1, p32/sck10/scl10/intp2, p70/kr0/so01/intp4, p72/kr2/sck01/intp6, p73/ kr3/so00/txd0, or p75/kr5/sck00 pin as a port function pin, set the corresponding cko0n and so0n bits to ?1?. so0 can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0f0fh. figure 12-14. format of serial output register 0 (so0) address: f0128h, f0129h after reset: 0f0fh r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko 02 cko 01 cko 00 0 0 0 0 1 so 02 so 01 so 00 cko 0n serial clock output of channel n 0 serial clock output value is ?0?. 1 serial clock output value is ?1?. so 0n serial data output of channel n 0 serial data output value is ?0?. 1 serial data output value is ?1?. caution be sure to set bits 11 and 3 to ?1?. and be sure to clear bits 15 to 12 and 7 to 4 to ?0?. remark n: channel number (n = 0 to 2) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 402 (13) serial output level register 0 (sol0) sol0 is a register that is used to set inve rsion of the data output level of each channel. this register can be set only in the uart mode. be sure to set 0000h in the csi mode and simplifies i 2 c mode. inverting channel n by using this register is reflect ed on pin output only when serial output is enabled (soe0n = 1). when serial output is disabled (soe0n = 0), the value of the so0n bit is output as is. rewriting sol0 is prohibited when the regi ster is in operation (when se0n = 1). sol0 can be set by a 16-bit memory manipulation instruction. the lower 8 bits of sol0 can be set with an 8-bi t memory manipulation instruction with sol0l. reset signal generation clears this register to 0000h. figure 12-15. format of serial output level register 0 (sol0) address: f0134h, f0135h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sol0 0 0 0 0 0 0 0 0 0 0 0 0 0 sol 02 0 sol 00 sol 0n selects inversion of the level of the transmit data of channel n in uart mode 0 communication data is output as is. 1 communication data is inverted and output. caution be sure to clear bits 15 to 3, and 1 to ?0?. remark n: channel number (n = 0, 2) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 403 (14) input switch control register (isc) isc is used to realize a lin-bus communication operatio n by uart0 in coordination with an external interrupt and the timer array unit taus. when bit 0 is set to 1, the input signal of the serial data input (r x d0) pin is selected as an external interrupt (intp0) that can be used to detect a wakeup signal. when bit 1 is set to 1, the input signal of the serial data input (r x d0) pin is selected as a timer input, so that the pulse widths of a sync break field and a sync field can be measured by the timer. isc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 12-16. format of input switch control register (isc) address: fff3ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 0 0 0 isc2 isc1 isc0 isc1 switching channel 7 input of timer array unit taus 0 uses the input signal of the ti07 pin as a timer input (normal operation). 1 input signal of r x d0 pin is used as timer input (wakeup signal detection). isc0 switching external interrupt (intp0) input 0 uses the input signal of the intp0 pin as an external interrupt (normal operation). 1 uses the input signal of the r x d0 pin as an external interrupt (to measure the pulse widths of t he sync break field and sync field). caution be sure to clear bits 7 to 3 to ?0?. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 404 (15) noise filter enable register 0 (nfen0) nfen0 is used to set whether the noise filter can be used for the input sig nal from the serial data input pin to each channel. disable the noise filter of the pin used for csi or simplified i 2 c communication, by clearing the corresponding bit of this register to 0. enable the noise filter of the pin used for uart comm unication, by setting the corresponding bit of this register to 1. when the noise filter is enabled, cpu/ peripheral hardware clock (f clk ) is synchronized with 2-clock match detection. nfen0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 12-17. format of noise filter enable register 0 (nfen0) address: f0060h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 nfen0 0 0 0 0 0 snfen10 0 snfen00 snfen10 use of noise filter of r x d1/sda10/si10/intp1/p31 pin 0 noise filter off 1 noise filter on set snfen10 to 1 to use the r x d1 pin. clear snfen10 to 0 to use the sda10, si10, intp1, and p31 pins. snfen00 use of noise filter of r x d0/si00/kr4/p74 pin 0 noise filter off 1 noise filter on set snfen00 to 1 to use the r x d0 pin. clear snfen00 to 0 to use the si00, kr4, and p74 pins. caution be sure to clear bits 7 to 3, and 1 to ?0?. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 405 (16) port input mode registers 3, 7 (pim3, pim7) these registers set the input buffer of ports 3 and 7 in 1-bit units. pim3 and pim7 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 12-18. format of port input m ode registers 3 and 7 (pim3 and pim7) address f0043h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pim3 0 0 0 0 0 pim32 pim31 0 address f0047h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pim7 0 0 pim75 pim74 0 pim72 pim71 0 pimmn pmn pin input buffer selection (m = 3, 7; n = 1, 2, 4, 5) 0 normal input buffer 1 ttl input buffer (17) port output mode registers 3, 7 (pom3, pom7) these registers set the output mode of ports 3 and 7 in 1-bit units. pom3 and pom7 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 12-19. format of port output mode registers 3 and 7 (pom3 and pom7) address f0053h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pom3 0 0 0 0 0 pom32 pom31 pom30 address f0057h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pom7 0 0 pom75 0 pom73 pom72 0 pom70 pommn pmn pin output buffer selection (m = 3, 7; n = 0 to 3, 5) 0 normal output mode 1 n-ch open-drain output (v dd tolerance) mode chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 406 (18) port mode registers 3, 7 (pm3, pm7) these registers set input/output of ports 3 and 7 in 1-bit units. when using the p30/so10/txd1 , p31/si10/rxd1/sda10/intp1, p32/sck10/scl10/intp2, p70/kr0/so01/intp4, p72/kr2/sck01/intp6, p73/kr 3/so00/txd0, and p75/kr5/sck00 pins for serial data output or serial clock output, clear the pm30 to pm32, pm70, pm72, pm73, and pm75 bits to 0, and set the output latches of p30 to p32, p70, p72, p73, and p75 to 1. when using the p31/si10/rxd1/sda10/intp1, p 32/sck10/scl10/intp2, p71/kr1/si01/intp5, p72/kr2/sck01/intp6, p74/kr4/si00/rx d0, and p75/kr5/sck00 pins for serial data input or serial clock input, set the pm31, pm32, pm71, pm72, pm74, and pm75 bits to 1. at this time, the output latches of p31, p32, p71, p72, p74, and p75 may be 0 or 1. pm3 and pm7 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation se ts these registers to ffh. figure 12-20. format of port mode registers 3 and 7 (pm3 and pm7) address: fff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 1 1 pm32 pm31 pm30 address: fff27h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm7 1 1 pm75 pm74 pm73 pm72 pm71 pm70 pmmn pmn pin i/o mode selection (m = 3, 7; n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 407 12.4 operation stop mode each serial interface of serial array unit has the operation stop mode. in this mode, serial communication cannot be ex ecuted, thus reducing the power consumption. in addition, the p30/so10/txd1, p31/ si10/rxd1/sda10/intp1, p32/sck10/ scl10/intp2, p70/kr0/so01/intp4, p71/kr1/si01/intp5, p72/kr2/sck0 1/intp6, p73/kr3/so00/txd0, p74/ kr4/si00/rxd0, and p75/kr5/sck00 pins can be used as port function pins in this mode. 12.4.1 stopping the operation by units the stopping of the operation by units is set by using peripheral enable register 0 (per0). per0 is used to enable or disable use of each peripheral ha rdware macro. clock supply to a hardware macro that is not used is stopped in order to r educe the power consumption and noise. to stop the operation of serial array unit, set bit 2 (sau0en) to 0. figure 12-21. peripheral enable register 0 (per 0) setting when stopping the operation by units cautions 1. if sau0en = 0, writing to a control regist er of serial array unit is ignored, and, even if the register is read, only the default value is r ead (except for input switch control register (isc), noise filter enable register (nfen0), port input mode registers (pim3, pim7), port output mode registers (pom3, pom7), port m ode registers (pm3, pm7), and port registers (p3, p7)). 2. be sure to clear bits 6, 3, 1, and 0 to ?0?. remark : setting disabled (fixed by hardware) : bits not used with serial array units (dependi ng on the settings of other peripheral functions) 0/1: set to 0 or 1 depending on the usage of the user (a) peripheral enable register 0 (per0) 7 6 5 4 3 2 1 0 per0 rtcen 0 adcen iicaen 0 sau0en 0/1 0 0 control of sau input clock 0: stops supply of input clock 1: su pp lies in p ut cloc k chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 408 12.4.2 stopping the operation by channels the stopping of the operation by channels is se t using each of the following registers. figure 12-22. each register setting when stopping the operation by channels (1/2) (a) serial channel enable status register 0 (s e0) ? this register indicates whether data transmission/reception operation of eac h channel is enabled or stopped. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 se0 0 0 0 0 0 0 0 0 0 0 0 0 se03 0/1 se02 0/1 se01 0/1 se00 0/1 0: operation stops * the se0 register is a read-only status register, w hose operation is stopped by using the st0 register. with a channel whose operation is stopped, the value of cko0n of the so0 register can be set by software. (b) serial channel stop register 0 (st0) ? this register is a trigger register that is used to enable stopping communication/count by each channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 st0 0 0 0 0 0 0 0 0 0 0 0 0 st03 0/1 st02 0/1 st01 0/1 st00 0/1 1: clears se0n to 0 and stops the communication operation * because st0n is a trigger bit, it is cleared immediately when se0n = 0. (c) serial output enable register 0 (soe0) ? this regist er is a register that is used to enable or stop output of the serial communication operation of each channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 soe01 0/1 soe00 0/1 0: stops output by serial communication operation * for channel n, whose serial output is stopped, the so0n value of the so0 register can be set by software. (d) serial output register 0 (so0) ?thi s register is a buffer register for serial output of each channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 0/1 cko01 0/1 cko00 0/1 0 0 0 0 1 so02 0/1 so01 0/1 so00 0/1 1: serial clock output value is ?1? 1: serial data output value is ?1? * when using pins corresponding to each c hannel as port function pins, set the corresponding cko0n and so0n bits to ?1?. remark n: channel number (n = 0 to 3) : setting disabled (fixed by hardware), 0/1: set to 0 or 1 depending on the usage of the user chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 409 12.5 operation of 3-wire serial i/o (csi00, csi01, csi10) communication this is a clocked communication function that uses thr ee lines: serial clock (sck) and serial data (si and so) lines. [data transmission/reception] ? data length of 7 or 8 bits ? phase control of transmit/receive data ? msb/lsb first selectable ? level setting of transmit/receive data [clock control] ? master/slave selection ? phase control of i/o clock ? setting of transfer period by prescaler and internal counter of each channel ? maximum transfer rate during master co mmunication: max. f clk /4, during slave communication: max. f mck /6 note [interrupt function] ? transfer end interrupt/buffer empty interrupt [error detection flag] ? overrun error note use the clocks within a range sa tisfying the sck cycle time (t kcy ) characteristics (see chapter 28 electrical specifi cations (target) ). the channels supporti ng 3-wire serial i/o (csi00, csi01, csi10) are channels 0 to 2 of sau. channel used as csi used as uart used as simplified i 2 c 0 csi00 uart0 (supporting lin-bus) ? 1 csi01 ? 2 csi10 uart1 iic10 3 ? ? 3-wire serial i/o (csi00, csi01, ci s10) performs the following six ty pes of communic ation operations. ? master transmission (see 12.5.1 .) ? master reception (see 12.5.2 .) ? master transmission/reception (see 12.5.3 .) ? slave transmission (see 12.5.4 .) ? slave reception (see 12.5.5 .) ? slave transmission/reception (see 12.5.6 .) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 410 12.5.1 master transmission master transmission is that the 78k0r/kx3-l outputs a transfer clock and transmits data to another device. 3-wire serial i/o csi00 csi01 csi10 target channel channel 0 of sau channel 1 of sau channel 2 of sau pins used sck00, so00 sc k01, so01 sck10, so10 intcsi00 intcsi01 intcsi10 interrupt transfer end interrupt (in single-transfer mode) or buff er empty interrupt (in continuous transfer mode) can be selected. error detection flag none transfer data length 7 or 8 bits transfer rate max. f clk /4 [mhz], min. f clk /(2 2 11 128) [mhz] note f clk : system clock frequency data phase selectable by dap0n bit ? dap0n = 0: data output starts from the start of the operation of the serial clock. ? dap0n = 1: data output starts half a clock before the start of the serial clock operation. clock phase selectable by ckp0n bit ? ckp0n = 0: forward ? ckp0n = 1: reverse data direction msb or lsb first note use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 28 electrical specifications (target) ). remark n: channel number (n = 0 to 2) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 411 (1) register setting figure 12-23. example of contents of registers for master transmission of 3-wire serial i/o (csi00, csi01, csi10) (a) serial output register 0 (so0) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 0/1 cko01 0/1 cko00 0/1 0 0 0 0 1 so02 0/1 so01 0/1 so00 0/1 communication starts when these bits are 1 if the data phase is forward (ckp0n = 0). if the phase is reversed (ckp0n = 1), communication starts when these bits are 0. (b) serial output enable register 0 (soe0) ? se ts only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 soe01 0/1 soe00 0/1 (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 0/1 ss00 0/1 (d) serial mode register 0n (smr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks0n 0/1 ccs0n 0 0 0 0 0 0 sts0n 0 0 sis00 0 1 0 0 md0n2 0 md0n1 0 md0n0 0/1 operation mode of channel n 0: transfer end interrupt 1: buffer empty interrupt (e) serial communication operati on setting register 0n (scr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe0n 1 rxe0n 0 dap0n 0/1 ckp0n 0/1 0 eoc0n 0 ptc0n1 0 ptc0n0 0 dir0n 0/1 0 slc0n1 0 slc0n0 0 0 dls0n2 1 dls0n1 1 dls0n0 0/1 (f) serial data register 0n (sdr0n) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n baud rate setting 0 transmit data setting remark n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) : setting is fixed in the csi master transmission mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 412 (2) operation procedure figure 12-24. initial setting pr ocedure for master transmission caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. starting initial setting setting per0 register setting sps0 register setting smr0n register setting scr0n register setting sdr0n register setting so0 register changing setting of soe0 register setting port writing to ss0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. manipulate the so0n and cko0n bits and set an initial output level. set the soe0n bit to 1 and enable data output of the target channel. enable data output and clock output of the target channel by setting a port register and a port mode register. set transmit data to the siop register (bits 7 to 0 of the sdr0n register) and start communication. se0n = 1 when the ss0n bit of the target channel is set to 1. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 413 figure 12-25. procedure for stopping master transmission remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the so0 register (see figure 12-26 procedure for resuming master transmission ). starting setting to stop setting st0 register stopping communication write 1 to the st0n bit of the target channel. stop communication in midway. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 414 figure 12-26. procedure for resuming master transmission starting setting for resumption port manipulation changing setting of sps0 register changing setting of sdr0n register changing setting of smr0n register changing setting of so0 register port manipulation writing to ss0 register starting communication disable data output and clock output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if an incorrect transfer baud rate is set. change the setting if the setting of the smr0n register is incorrect. manipulate the so0n and cko0n bits and set an initial output level. enable data output and clock output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. sets transmit data to the siop register (bits 7 to 0 of the sdr0n register) and start communication. (essential) (selective) (selective) (selective) (selective) ( essential ) (essential) (essential) change the setting if the setting of the scr0n register is incorrect. (selective) changing setting of scr0n register cleared by using sir0n registe r if fef, pef, or ovf flag remains set. (selective) clearing error flag set the soe0 register and enable data output of the target channel. (selective) changing setting of soe0 register set the soe0 register and stop data output of the target channel. (selective) changing setting of soe0 register chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 415 (3) processing flow (in si ngle-transmission mode) figure 12-27. timing chart of master tr ansmission (in single-transmission mode) ss0n se0n sdr0n sckp pin sop pin shift register 0n intcsip tsf0n data transmission (8-bit length) data transmission (8-bit length) data transmission (8-bit length) transmit data 3 transmit data 2 transmit data 1 transmit data 1 transmit data 2 transmit data 3 shift operation shift operation shift operation remark n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 416 figure 12-28. flowchart of master tr ansmission (in single-transmission mode) caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. starting csi communication writing 1 to ss0n bit writing transmit data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting output transfer end interrupt g enerated? transmission completed? no no yes yes setting sau0en bit of per0 register to 1 setting transfer rate by sps0 register port manipulation clearing sau0en bit of per0 register to 0 end of communication chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 417 (4) processing flow (in continuous transmission mode) figure 12-29. timing chart of master tran smission (in continuous transmission mode) ss0n se0n sdr0n sckp pin sop pin shift register 0n intcsip tsf0n data transmission (8-bit length) data transmission (8-bit length) transmit data 2 transmit data 1 transmit data1 transmit data 3 bff0n md0n0 transmit data 2 <1> <2> <2> <2> <3> <3> <3> <5> <4> ( note ) shift operation shift operation shift operation transmit data 3 data transmission (8-bit length) note when transmit data is written to the sdr0n register while bff0n = 1, the transmit data is overwritten. caution the md0n0 bit can be re written even during operation. however, rewrite it before transfer of the last bi t is started, so that it will be rewritten before the transfer end interrupt of the last transmit data. remark n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 418 figure 12-30. flowchart of master transm ission (in continuous transmission mode) starting csi communication writing 1 to ss0n bit writing transmit data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. <1> select the buffer empty interrupt. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0; setting output n o n o n o y es setting sau0en bit of per0 register to 1 setting transfer rate by sps0 register port manipulation end of communication clearing 0 to md0n0 bit y es n o y es n o communication continued? y es y es clearing sau0en bit of per0 register to 0 <2> <3> <4> <5> transmitting next data? buffer empty interrupt generated? transfer end interrupt generated? tsf0n = 1? writing 1 to md0n0 bit caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. remark <1> to <5> in the figure correspond to <1> to <5> in figure 12-29 timing chart of master transmission (in continuous transmission mode) . chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 419 12.5.2 master reception master reception is that the 78 k0r/kx3-l outputs a transfer clock and receives data from other device. 3-wire serial i/o csi00 csi01 csi10 target channel channel 0 of sau channel 1 of sau channel 2 of sau pins used sck00, si00 sck01, si01 sck10, si10 intcsi00 intcsi01 intcsi10 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error detection flag overrun error detection flag (ovf0n) only transfer data length 7 or 8 bits transfer rate max. f clk /4 [mhz], min. f clk /(2 2 11 128) [mhz] note f clk : system clock frequency data phase selectable by dap0n bit ? dap0n = 0: data input starts from the start of the operation of the serial clock. ? dap0n = 1: data input starts half a clock be fore the start of the serial clock operation. clock phase selectable by ckp0n bit ? ckp0n = 0: forward ? ckp0n = 1: reverse data direction msb or lsb first note use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 28 electrical specifications (target) ). remark n: channel number (n = 0 to 2) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 420 (1) register setting figure 12-31. example of contents of regist ers for master reception of 3-wire serial i/o (csi00, csi01, csi10) (a) serial output register 0 (so0) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 0/1 cko01 0/1 cko00 0/1 0 0 0 0 1 so02 so01 so00 communication starts when these bits are 1 if the data phase is forward (ckp0n = 0). if the phase is reversed (ckp0n = 1), communication starts when these bits are 0. (b) serial output enable register 0 (soe0) ? se ts only the bits of the target channel to 0. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 soe01 0/1 soe00 0/1 (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 0/1 ss00 0/1 (d) serial mode register 0n (smr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks0n 0/1 ccs0n 0 0 0 0 0 0 sts0n 0 0 sis0n0 0 1 0 0 md0n2 0 md0n1 0 md0n0 0 operation mode of channel n 0: transfer end interrupt (e) serial communication operati on setting register 0n (scr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe0n 0 rxe0n 1 dap0n 0/1 ckp0n 0/1 0 eoc0n 0 ptc0n1 0 ptc0n0 0 dir0n 0/1 0 slc0n1 0 slc0n0 0 0 dls0n2 1 dls0n1 1 dls0n0 0/1 (f) serial data register 0n (sdr0n) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n baud rate setting 0 receive data register (write ffh as dummy data.) remark n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) : setting is fixed in the csi master transmission mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 421 (2) operation procedure figure 12-32. initial setting procedure for master reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. figure 12-33. procedure for stopping master reception remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the so0 register (see figure 12-34 procedure for resuming master reception ). starting initial setting setting per0 register setting sps0 register setting smr0n register setting scr0n register setting sdr0n register setting so0 register setting port writing to ss0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. manipulate the cko0n bit and set an initial output level. enable clock output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. set dummy data to the siop register (bits 7 to 0 of the sdr0n register) and start communication. starting setting to stop setting st0 register stopping communication write 1 to the st0n bit of the target channel. stop communication in midway. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 422 figure 12-34. procedure for resuming master reception starting setting for resumption port manipulation changing setting of sps0 register changing setting of sdr0n register changing setting of smr0n register changing setting of so0 register port manipulation writing to ss0 register starting communication disable clock output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if an incorrect transfer baud rate is set. change the setting if the setting of the smr0n register is incorrect. manipulate the cko0n bit and set a clock output level. enable clock output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. sets dummy data to the siop register (bits 7 to 0 of the sdr0n register) and start communication. (essential) (selective) (selective) ( selective ) (selective) ( essential ) (essential) (essential) change the setting if the setting of the scr0n register is incorrect. (selective) changing setting of scr0n register cleared by using sir0n register if fef, pef, or ovf flag remains set. (selective) clearing error flag clear the soe0 register to 0 and stop data output of the target channel. (essential) changing setting of soe0 register chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 423 (3) processing flow (in single-reception mode) figure 12-35. timing chart of master reception (in single-reception mode) ss0n se0n sdr0n sckp pin sip pin shift register 0n intcsip tsf0n receive data 3 receive data 2 receive data 1 dummy data for reception dummy data dummy data receive data 1 receive data 2 receive data 3 write read write read read write reception & shift operation reception & shift operation reception & shift operation data transmission/reception (8-bit length) data transmission/reception (8-bit length) data transmission/reception (8-bit length) remark n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 424 figure 12-36. flowchart of master reception (in single-reception mode) starting csi communication writing 1 to ss0n bit writing dummy data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting sckp output transfer end interrupt generated? reception completed? no no yes yes setting sau0en bit of per0 register to 1 setting transfer rate by sps0 register port manipulation clearing sau0en bit of per0 register to 0 end of communication reading siop (= sdr0n[7:0]) register starting reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 425 12.5.3 master transmission/reception master transmission/reception is that the 78k0r/kx3-l outputs a transfer clock and transmits/receives data to/from other device. 3-wire serial i/o csi00 csi01 csi10 target channel channel 0 of sau channel 1 of sau channel 2 of sau pins used sck00, si00, so00 sck01, si01, so01 sck10, si10, so10 intcsi00 intcsi01 intcsi10 interrupt transfer end interrupt (in single-transfer mode) or buff er empty interrupt (in continuous transfer mode) can be selected. error detection flag overrun error detection flag (ovf0n) only transfer data length 7 or 8 bits transfer rate max. f clk /4 [mhz], min. f clk /(2 2 11 128) [mhz] note f clk : system clock frequency data phase selectable by dap0n bit ? dap0n = 0: data i/o starts at the start of the operation of the serial clock. ? dap0n = 1: data i/o starts half a clock before the start of the serial clock operation. clock phase selectable by ckp0n bit ? ckp0n = 0: forward ? ckp0n = 1: reverse data direction msb or lsb first note use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 28 electrical specifications (target) ). remark n: channel number (n = 0 to 2) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 426 (1) register setting figure 12-37. example of contents of registers for master transmission/reception of 3-wire serial i/o (csi00, csi01, csi10) (a) serial output register 0 (so0) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 0/1 cko01 0/1 cko00 0/1 0 0 0 0 1 so02 0/1 so01 0/1 so00 0/1 communication starts when these bits are 1 if the data phase is forward (ckp0n = 0). if the phase is reversed (ckp0n = 1), communication starts when these bits are 0. (b) serial output enable register 0 (soe0) ? se ts only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 soe01 0/1 soe00 0/1 (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 0/1 ss00 0/1 (d) serial mode register 0n (smr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks0n 0/1 ccs0n 0 0 0 0 0 0 sts0n 0 0 sis0n0 0 1 0 0 md0n2 0 md0n1 0 md0n0 0/1 operation mode of channel n 0: transfer end interrupt 1: buffer empty interrupt (e) serial communication operati on setting register 0n (scr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe0n 1 rxe0n 1 dap0n 0/1 ckp0n 0/1 0 eoc0n 0 ptc0n1 0 ptc0n0 0 dir0n 0/1 0 slc0n1 0 slc0n0 0 0 dls0n2 1 dls0n1 1 dls0n0 0/1 (f) serial data register 0n (sdr0n) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n baud rate setting 0 transmit data setting/receive data register remark n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) : setting is fixed in the csi master transmission mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 427 (2) operation procedure figure 12-38. initial setting procedur e for master transmission/reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. figure 12-39. procedure for stoppi ng master transmission/reception remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the so0 register (see figure 12-40 procedure for resumi ng master transmission/reception ). starting initial setting setting per0 register setting sps0 register setting smr0n register setting scr0n register setting sdr0n register setting so0 register changing setting of soe0 register setting port writing to ss0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. manipulate the so0n and cko0n bits and set an initial output level. set the soe0n bit to 1 and enable data output of the target channel. enable data output and clock output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. set transmit data to the siop register (bits 7 to 0 of the sdr0n register) and start communication. starting setting to stop setting st0 register stopping communication write 1 to the st0n bit of the target channel. stop communication in midway. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 428 figure 12-40. procedure for resumi ng master transmission/reception starting setting for resumption port manipulation changing setting of sps0 register changing setting of sdr0n register changing setting of smr0n register changing setting of so0 register port manipulation writing to ss0 register starting communication disable data output and clock output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if an incorrect transfer baud rate is set. change the setting if the setting of the smr0n register is incorrect. manipulate the so0n and cko0n bits and set an initial output level. enable data output and clock output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. sets transmit data to the siop register (bits 7 to 0 of the sdr0n register) and start communication. (essential) (selective) (selective) (selective) (selective) (essential) (essential) (essential) change the setting if the setting of the scr0n register is incorrect. (selective) changing setting of scr0n register cleared by using sir0n registe r if fef, pef, or ovf flag remains set. (selective) clearing error flag set the soe0 register and stop data output of the target channel. ( selective ) changing setting of soe0 register set the soe0 register and enable data output of the target channel. (selective) changing setting of soe0 register chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 429 (3) processing flow (in single -transmission/reception mode) figure 12-41. timing chart of master transmission/ reception (in single-trans mission/reception mode) ss0n se0n sdr0n sckp pin sip pin shift register 0n intcsip tsf0n receive data 3 receive data 2 receive data 1 transmit data 1 transmit data 2 transmit data 3 receive data 1 receive data 2 receive data 3 write read write read read write sop pin transmit data 3 transmit data 2 transmit data 1 reception & shift operation reception & shift operation reception & shift operation data transmission/reception (8-bit length) data transmission/reception (8-bit length) data transmission/reception (8-bit length) remark n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 430 figure 12-42. flowchart of master transmission/ reception (in single- tr ansmission/reception mode) starting csi communication writing 1 to ss0n bit writing transmit data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting output and sckp output transfer end interrupt generated? transmission/reception completed? no no yes yes setting sau0en bit of per0 register to 1 setting transfer rate by sps0 register port manipulation clearing sau0en bit of per0 register to 0 end of communication reading siop (=sdr0n[7:0]) register starting transmission/reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 431 (4) processing flow (in continu ous transmission/reception mode) figure 12-43. timing chart of master transmission/re ception (in continuous transmission/reception mode) <4> <5> ss0n se0n sdr0n sckp pin sip pin shift register 0n intcsip tsf0n transmit data 1 transmit data 3 receive data 3 write read read read write sop pin bff0n <1> <2> <3> <2> <3> <4> <2> <7> <8> ( note 1 ) transmit data 2 write <6> <3> ( note 2 ) ( note 2 ) reception & shift operation md0n0 receive data 2 receive data 1 receive data 1 receive data 2 receive data 3 transmit data 3 transmit data 2 transmit data 1 reception & shift operation reception & shift operation data transmission/reception (8-bit length) data transmission/reception (8-bit length) data transmission/reception (8-bit length) notes 1. when transmit data is written to the sdr0n re gister while bff0n = 1, the transmit data is overwritten. 2. the transmit data can be read by reading the sdr0n register during this period. at this time, the transfer operation is not affected. caution the md0n0 bit can be re written even during operation. however, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data. remarks 1. <1> to <8> in the figure correspond to <1> to <8> in figure 12-44 flowchart of master transmission/reception (in contin uous transmission/reception mode ). 2. n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 432 figure 12-44. flowchart of master transmission/r eception (in continuous tr ansmission/reception mode) starting csi communication writing 1 to ss0n bit reading receive data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. <1> select the buffer empty interrupt. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting output and sckp output y es y es n o n o setting sau0en bit of per0 register to 1 setting transfer rate by sps0 register port manipulation end of communication clearing 0 to md0n0 bit n o transfer end interrupt generated? y es n o communication continued? y es y es clearing sau0en bit of per0 register to 0 communication data exists? writing transmit data to siop (=sdr0n[7:0]) tsf0n = 1? reading receive data to siop (=sdr0n[7:0]) writing 1 to md0n0 bit buffer empty interrupt generated? <2> <3> <5> <6> <7> <4> <8> n o caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. remark <1> to <8> in the figure correspond to <1> to <8> in figure 12-43 timing chart of master transmission/reception (in continuo us transmission/reception mode) . chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 433 12.5.4 slave transmission slave transmission is that the 78k0r/kx3-l transmits data to another device in the state of a transfer clock being input from another device. 3-wire serial i/o csi00 csi01 csi10 target channel channel 0 of sau channel 1 of sau channel 2 of sau pins used sck00, so00 sc k01, so01 sck10, so10 intcsi00 intcsi01 intcsi10 interrupt transfer end interrupt (in single-transfer mode) or buff er empty interrupt (in continuous transfer mode) can be selected. error detection flag overrun error detection flag (ovf0n) only transfer data length 7 or 8 bits transfer rate the smaller of f clk /6 [mhz] and f mck /2 [mhz] is the maximum transfer rate notes 1, 2 . data phase selectable by dap0n bit ? dap0n = 0: data output starts from the start of the operation of the serial clock. ? dap0n = 1: data output starts half a clock before the start of the serial clock operation. clock phase selectable by ckp0n bit ? ckp0n = 0: forward ? ckp0n = 1: reverse data direction msb or lsb first notes 1. because the external serial clock input to pins sck00, sck01, and sck10 is sampled internally and used, the maximum transfer rate is the smaller of f clk /6 [mhz] and f mck /2 [mhz]. 2. use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 28 electrical specifications (target) ). remarks 1. f mck : operation clock (mck) frequency of target channel f clk : system clock frequency 2. n: channel number (n = 0 to 2) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 434 (1) register setting figure 12-45. example of contents of register s for slave transmission of 3-wire serial i/o (csi00, csi01, csi10) (a) serial output register 0 (so0) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 cko01 cko00 0 0 0 0 1 so02 0/1 so01 0/1 so00 0/1 (b) serial output enable register 0 (soe0) ? se ts only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 soe01 0/1 soe00 0/1 (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 0/1 ss00 0/1 (d) serial mode register 0n (smr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks0n 0/1 ccs0n 1 0 0 0 0 0 sts0n 0 0 sis0n0 0 1 0 0 md0n2 0 md0n1 0 md0n0 0/1 operation mode of channel n 0: transfer end interrupt 1: buffer empty interrupt (e) serial communication operati on setting register 0n (scr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe0n 1 rxe0n 0 dap0n 0/1 ckp0n 0/1 0 eoc0n 0 ptc0n1 0 ptc0n0 0 dir0n 0/1 0 slc0n1 0 slc0n0 0 0 dls0n2 1 dls0n1 1 dls0n0 0/1 (f) serial data register 0n (sdr0n) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n baud rate setting 0 transmit data setting remark n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) : setting is fixed in the csi master transmission mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 435 (2) operation procedure figure 12-46. initial setting pr ocedure for slave transmission caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. starting initial setting setting per0 register setting sps0 register setting smr0n register setting scr0n register setting sdr0n register setting so0 register changing setting of soe0 register setting port writing to ss0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set bits 15 to 9 to 0000000b for baud rate setting. manipulate the so0n bit and set an initial output level. set the soe0n bit to 1 and enable data output of the target channel. enable data output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. set transmit data to the siop register (bits 7 to 0 of the sdr0n register) and wait for a clock from the master. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 436 figure 12-47. procedure for stopping slave transmission remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the so0 register (see figure 12-48 procedure for resuming slave transmission ). starting setting to stop setting st0 register stopping communication write 1 to the st0n bit of the target channel. stop communication in midway. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 437 figure 12-48. procedure for resuming slave transmission starting setting for resumption port manipulation changing setting of sps0 register changing setting of smr0n register changing setting of so0 register port manipulation writing to ss0 register disable data output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if the setting of the smr0n register is incorrect. manipulate the so0n and cko0n bits and set an initial output level. enable data output of the target channel by setting a port register and a port mode register. set the ss0n bit of the target channel to 1 and set se0n to 1. sets transmit data to the siop register (bits 7 to 0 of the sdr0n register) and wait for a clock from the master. (selective) (selective) (selective) (selective) ( essential ) (essential) (essential) change the setting if the setting of the scr0n register is incorrect. (selective) changing setting of scr0n register cleared by using sir0n registe r if fef, pef, or ovf flag remains set. (selective) clearing error flag set the soe0 register and enable data output of the target channel. (selective) changing setting of soe0 register stop the target fo r communication or wait until the target completes its operation. (essential) manipulating target for communication starting target for communication starts the target for communication. (essential) starting communication set the soe0 register and stop data output of the target channel. (selective) changing setting of soe0 register chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 438 (3) processing flow (in si ngle-transmission mode) figure 12-49. timing chart of slave tr ansmission (in single-transmission mode) ss0n se0n sdr0n sckp pin sop pin shift register 0n intcsip tsf0n data transmission (8-bit length) data transmission (8-bit length) data transmission (8-bit length) transmit data 3 transmit data 2 transmit data 1 transmit data 1 transmit data 2 transmit data 3 shift operation shift operation shift operation remark n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 439 figure 12-50. flowchart of slave tran smission (in single-transmission mode) caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. starting csi communication writing 1 to ss0n bit writing transmit data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting output transfer end interrupt g enerated? transmission completed? no no yes yes setting sau0en bit of per0 register to 1 setting transfer rate by sps0 register port manipulation clearing sau0en bit of per0 register to 0 end of communication chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 440 (4) processing flow (in continuous transmission mode) figure 12-51. timing chart of slave transm ission (in continuous transmission mode) ss0n se0n sdr0n sckp pin sop pin shift register 0n intcsip tsf0n data transmission (8-bit length) data transmission (8-bit length) transmit data 2 transmit data 1 transmit data 3 bff0n md0n0 transmit data 2 <1> <2> <2> <2> <3> <3> <3> <5> <4> ( note ) shift operation shift operation shift operation transmit data 3 data transmission (8-bit length) transmit data 1 note when transmit data is written to the sdr0n register while bff0n = 1, the transmit data is overwritten. caution the md0n0 bit can be rewritten even during ope ration. however, rewrite it before transfer of the last bit is started. remark n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 441 figure 12-52. flowchart of slave transmission (in continuous transmission mode) starting csi communication writing 1 to ss0n bit writing transmit data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. <1> select the buffer empty interrupt. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting output n o n o n o y es setting sau0en bit of per0 register to 1 setting transfer rate by sps0 register port manipulation end of communication clearing 0 to md0n0 bit y es n o y es n o communication continued? y es y es clearing sau0en bit of per0 register to 0 <2> <3> <4> <5> transmitting next data? buffer empty interrupt generated? transfer end interrupt generated? tsf0n = 1? writing 1 to md0n0 bit caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. remark <1> to <5> in the figure correspond to <1> to <5> in figure 12-51 timing chart of slave transmission (in continuous transmission mode) . chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 442 12.5.5 slave reception slave reception is that the 78k0r/kx3 -l receives data from another device in the state of a transfer clock being input from another device. 3-wire serial i/o csi00 csi01 csi10 target channel channel 0 of sau channel 1 of sau channel 2 of sau pins used sck00, si00 sck01, si01 sck10, si10 intcsi00 intcsi01 intcsi10 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error detection flag overrun error detection flag (ovf0n) only transfer data length 7 or 8 bits transfer rate the smaller of f clk /6 [mhz] and f mck /2 [mhz] is the maximum transfer rate notes 1, 2 . data phase selectable by dap0n bit ? dap0n = 0: data input starts from the start of the operation of the serial clock. ? dap0n = 1: data input starts half a clock be fore the start of the serial clock operation. clock phase selectable by ckp0n bit ? ckp0n = 0: forward ? ckp0n = 1: reverse data direction msb or lsb first notes 1. because the external serial clock input to pins sck00, sck01, and sck10 is sampled internally and used, the maximum transfer rate is the smaller of f clk /6 [mhz] and f mck /2 [mhz]. 2. use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 28 electrical specifications (target) ). remarks 1. f mck : operation clock (mck) frequency of target channel f clk : system clock frequency 2. n: channel number (n = 0 to 2) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 443 (1) register setting figure 12-53. example of contents of regist ers for slave reception of 3-wire serial i/o (csi00, csi01, csi10) (a) serial output register 0 (so0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 cko01 cko00 0 0 0 0 1 so02 so01 so00 (b) serial output enable register 0 (soe0) ? se ts only the bits of the target channel to 0. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 soe01 0/1 soe00 0/1 (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 0/1 ss00 0/1 (d) serial mode register 0n (smr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks0n 0/1 ccs0n 1 0 0 0 0 0 sts0n 0 0 sis0n0 0 1 0 0 md0n2 0 md0n1 0 md0n0 0 operation mode of channel n 0: transfer end interrupt (e) serial communication operati on setting register 0n (scr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe0n 0 rxe0n 1 dap0n 0/1 ckp0n 0/1 0 eoc0n 0 ptc0n1 0 ptc0n0 0 dir0n 0/1 0 slc0n1 0 slc0n0 0 0 dls0n2 1 dls0n1 1 dls0n0 0/1 (f) serial data register 0n (sdr0n) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n 0000000 (baud rate setting) 0 receive data register remark n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) : setting is fixed in the csi master transmission mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 444 (2) operation procedure figure 12-54. initial setting procedure for slave reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. figure 12-55. procedure for stopping slave reception starting initial settings setting per0 register setting sps0 register setting smr0n register setting scr0n register setting sdr0n register setting port writing to ss0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set bits 15 to 9 to 0000000b for baud rate setting. enable data input and clock input of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. wait for a clock from the master. starting setting to stop setting st0 register stopping communication write 1 to the st0n bit of the target channel. stop communication in midway. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 445 figure 12-56. procedure for resuming slave reception starting setting for resumption port manipulation changing setting of sps0 register changing setting of smr0n register changing setting of so0 register port manipulation writing to ss0 register starting communication disable clock output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if the setting of the smr0n register is incorrect. manipulate the cko0n bit and enable reception. enable clock output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. wait for a clock from the master. (essential) (selective) (selective) (selective) (essential) (essential) (essential) change the setting if the setting of the scr0n register is incorrect. (selective) changing setting of scr0n register cleared by using sir0n register if fef, pef, or ovf flag remains set. (selective) clearing error flag clear the soe0 register to 0 and stop data output of the target channel. (essential) changing setting of soe0 register manipulating target for communication stop the target for communication or wait until the target completes its operation. change the setting if the setting of the sdr0n register is incorrect. (selective) changing setting of sdr0n register (essential) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 446 (3) processing flow (in single-reception mode) figure 12-57. timing chart of slave reception (in sing le-reception mode) ss0n se0n sdr0n sckp pin sip pin shift register 0n intcsip tsf0n data reception (8-bit length) data reception (8-bit length) data reception (8-bit length) receive data 3 receive data 2 receive data 1 receive data 1 receive data 2 receive data 3 read read read reception & shift operation reception & shift operation reception & shift operation remark n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 447 figure 12-58. flowchart of slave reception (in singl e-reception mode) starting csi communication writing 1 to ss0n bit writing 1 to st0n bit perform initial setting when se0n = 0. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting sckp output transfer end interrupt generated? reception completed? no no yes yes setting sau0en bit of per0 register to 1 setting transfer rate by sps0 register port manipulation clearing sau0en bit of per0 register to 0 end of communication reading siop (=sdr0n[7:0]) register starting reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 448 12.5.6 slave transmission/reception slave transmission/reception is that the 78k0r/kx3-l transmi ts/receives data to/from another device in the state of a transfer clock being input from another device. 3-wire serial i/o csi00 csi01 csi10 target channel channel 0 of sau channel 1 of sau channel 2 of sau pins used sck00, si00, so00 sck01, si01, so01 sck10, si10, so10 intcsi00 intcsi01 intcsi10 interrupt transfer end interrupt (in single-transfer mode) or buff er empty interrupt (in continuous transfer mode) can be selected. error detection flag overrun error detection flag (ovf0n) only transfer data length 7 or 8 bits transfer rate the smaller of f clk /6 [mhz] and f mck /2 [mhz] is the maximum transfer rate notes 1, 2 . data phase selectable by dap0n bit ? dap0n = 0: data i/o starts from the start of the operation of the serial clock. ? dap0n = 1: data i/o starts half a clock before the start of the serial clock operation. clock phase selectable by ckp0n bit ? ckp0n = 0: forward ? ckp0n = 1: reverse data direction msb or lsb first notes 1. because the external serial clock input to pins sck00, sck01, and sck10 is sampled internally and used, the maximum transfer rate is the smaller of f clk /6 [mhz] and f mck /2 [mhz]. 2. use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 28 electrical specifications (target) ). remarks 1. f mck : operation clock (mck) frequency of target channel f clk : system clock frequency 2. n: channel number (n = 0 to 2) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 449 (1) register setting figure 12-59. example of contents of registers fo r slave transmission/recepti on of 3-wire serial i/o (csi00, csi01, csi10) (a) serial output register 0 (so0) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 cko01 cko00 0 0 0 0 1 so02 0/1 so01 0/1 so00 0/1 (b) serial output enable register 0 (soe0) ? se ts only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 soe01 0/1 soe00 0/1 (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 0/1 ss00 0/1 (d) serial mode register 0n (smr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks0n 0/1 ccs0n 1 0 0 0 0 0 sts0n 0 0 sis0n0 0 1 0 0 md0n2 0 md0n1 0 md0n0 0/1 operation mode of channel n 0: transfer end interrupt 1: buffer empty interrupt (e) serial communication operati on setting register 0n (scr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe0n 1 rxe0n 1 dap0n 0/1 ckp0n 0/1 0 eoc0n 0 ptc0n1 0 ptc0n0 0 dir0n 0/1 0 slc0n1 0 slc0n0 0 0 dls0n2 1 dls0n1 1 dls0n0 0/1 (f) serial data register 0n (sdr0n) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n 0000000 (baud rate setting) 0 transmit data setting/receive data register remark n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) : setting is fixed in the csi master transmission mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 450 (2) operation procedure figure 12-60. initial setting proce dure for slave transmission/reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. starting initial setting setting per0 register setting sps0 register setting smr0n register setting scr0n register setting sdr0n register setting so0 register changing setting of soe0 register setting port writing to ss0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set bits 15 to 9 to 0000000b for baud rate setting. manipulate the so0n bit and set an initial output level. set the soe0n bit to 1 and enable data output of the target channel. enable data output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. set transmit data to the siop register (bits 7 to 0 of the sdr0n register) and wait for a clock from the master. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 451 figure 12-61. procedure for stopping slave transmission/reception remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the so0 register (see figure 12-62 procedure for resu ming slave transmission/reception ). starting setting to stop setting st0 register stopping communication write 1 to the st0n bit of the target channel. stop communication in midway. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 452 figure 12-62. procedure for resu ming slave transmission/reception starting setting for resumption manipulating target for communication port manipulation changing setting of sps0 register changing setting of smr0n register changing setting of so0 register port manipulation writing to ss0 register stop the target fo r communication or wait until the target completes its operation. disable data output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if the setting of the smr0n register is incorrect. manipulate the so0n bit and set an initial output level. enable data output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. (essential) (essential) ( selective ) (selective) (selective) (essential) (essential) clearing error flag (selective) cleared by using sir0n registe r if fef, pef, or ovf flag remains set. starting communication starting target for communication sets transmit data to the siop register (bits 7 to 0 of the sdr0n register) and wait for a clock from the master. starts the target for communication. (essential) (essential) changing setting of sdr0 register change the setting if an incorrect division ratio of the operation clock is set. ( selective ) changing setting of scr0n register change the setting if the setting of the scr0n register is incorrect. (selective) changing setting of soe0 register set the soe0 register and stop data output of the target channel. (selective) changing setting of soe0 register set the soe0 register and enable data output of the target channel. (selective) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 453 (3) processing flow (in single -transmission/reception mode) figure 12-63. timing chart of slave transmission/ reception (in single-tra nsmission/reception mode) ss0n se0n sdr0n sckp pin sip pin shift register 0n intcsip tsf0n receive data 3 receive data 2 receive data 1 transmit data 1 transmit data 2 transmit data 3 receive data 2 receive data 3 write read write read read write sop pin transmit data 3 transmit data 2 transmit data 1 reception & shift operation reception & shift operation reception & shift operation receive data 1 data transmission/reception (8-bit length) data transmission/reception (8-bit length) data transmission/reception (8-bit length) remark n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 454 figure 12-64. flowchart of slave transmission/ reception (in single- tran smission/reception mode) starting csi communication writing 1 to ss0n bit writing transmit data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. smr0n, scr0n: setting communication sdr0n[15:9] : setting transfer rate so0, soe0 : setting output transfer end interrupt generated? transmission/reception completed? no no yes yes setting sau0en bit of per0 register to 1 setting transfer rate by sps0 register port manipulation clearing sau0en bit of per0 register to 0 end of communication reading siop (=sdr0n[7:0]) register starting transmission/reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 455 (4) processing flow (in continu ous transmission/reception mode) figure 12-65. timing chart of sla ve transmission/receptio n (in continuous transmission/reception mode) <4> <5> ss0n se0n sdr0n sckp pin sip pin shift register 0n intcsip tsf0n transmit data 1 transmit data 3 receive data 3 write read read read write sop pin bff0n <1> <2> <3> <2> <3> <4> <2> <7> <8> ( note 1 ) transmit data 2 write <6> <3> ( note 2 ) ( note 2 ) reception & shift operation md0n0 receive data 2 receive data 1 receive data 1 receive data 2 receive data 3 transmit data 3 transmit data 2 transmit data 1 reception & shift operation reception & shift operation data transmission/reception (8-bit length) data transmission/reception (8-bit length) data transmission/reception (8-bit length) notes 1. when transmit data is written to the sdr0n re gister while bff0n = 1, the transmit data is overwritten. 2. the transmit data can be read by reading the sdr0n register during this period. at this time, the transfer operation is not affected. caution the md0n0 bit can be re written even during operation. however, rewrite it before transfer of the last bi t is started, so that it will be rewritten before the transfer end interrupt of the last transmit data. remarks 1. <1> to <8> in the figure correspond to <1> to <8> in figure 12-66 flowchart of slave transmission/reception (in contin uous transmission/reception mode ). 2. n: channel number (n = 0 to 2) p: csi number (p = 00, 01, 10) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 456 figure 12-66. flowchart of slave transmission/recep tion (in continuous transmission/reception mode) starting csi communication writing 1 to ss0n bit reading receive data to siop (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. <1> select the buffer empty interrupt. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0, soe0: setting output y es y es n o n o setting sau0en bit of per0 register to 1 setting transfer rate by sps0 register port manipulation end of communication clearing 0 to md0n0 bit n o transfer end interrupt generated? y es n o communication continued? y es y es clearing sau0en bit of per0 register to 0 communication data exists? w r iting transmit data to siop (=sdr0n[7:0]) tsf0n = 1? reading receive data to siop (=sdr0n[7:0]) writing 1 to md0n0 bit buffer empty interrupt generated? <2> <3> <5> <6> <7> <4> <8> n o caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. remark <1> to <8> in the figure correspond to <1> to <8> in figure 12-65 timing chart of slave transmission/reception (in continuo us transmission/reception mode) . chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 457 12.5.7 calculating transfer clock frequency the transfer clock frequency for 3-wire serial i/o (csi00, csi01, csi10) communicati on can be calculated by the following expressions. (1) master (transfer clock frequency) = {operation clock (mck) frequency of target channel} (sdr0n[15:9] + 1) 2 [hz] (2) slave (transfer clock frequency) = {frequency of serial clock (sck) supplied by master} note [hz] note the permissible maximum frequency is the smaller of f clk /6 [mhz] and f mck /2 [mhz]. remark the value of sdr0n[15:9] is t he value of bits 15 to 9 of the sdr0n register (0000000b to 1111111b) and therefore is 0 to 127. the operation clock (mck) is determined by serial clock select register 0 (sps0) and bit 15 (cks0n) of serial mode register 0n (smr0n). chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 458 table 12-2. selection of operation clock smr0n register sps0 register operation clock (mck) note 1 cks0n prs 013 prs 012 prs 011 prs 010 prs 003 prs 002 prs 001 prs 000 f clk = 20 mhz x x x x 0 0 0 0 f clk 20 mhz x x x x 0 0 0 1 f clk /2 10 mhz x x x x 0 0 1 0 f clk /2 2 5 mhz x x x x 0 0 1 1 f clk /2 3 2.5 mhz x x x x 0 1 0 0 f clk /2 4 1.25 mhz x x x x 0 1 0 1 f clk /2 5 625 khz x x x x 0 1 1 0 f clk /2 6 313 khz x x x x 0 1 1 1 f clk /2 7 156 khz x x x x 1 0 0 0 f clk /2 8 78.1 khz x x x x 1 0 0 1 f clk /2 9 39.1 khz x x x x 1 0 1 0 f clk /2 10 19.5 khz x x x x 1 0 1 1 f clk /2 11 9.77 khz 0 x x x x 1 1 1 1 inttm02 note2 0 0 0 0 x x x x f clk 20 mhz 0 0 0 1 x x x x f clk /2 10 mhz 0 0 1 0 x x x x f clk /2 2 5 mhz 0 0 1 1 x x x x f clk /2 3 2.5 mhz 0 1 0 0 x x x x f clk /2 4 1.25 mhz 0 1 0 1 x x x x f clk /2 5 625 khz 0 1 1 0 x x x x f clk /2 6 313 khz 0 1 1 1 x x x x f clk /2 7 156 khz 1 0 0 0 x x x x f clk /2 8 78.1 khz 1 0 0 1 x x x x f clk /2 9 39.1 khz 1 0 1 0 x x x x f clk /2 10 19.5 khz 1 0 1 1 x x x x f clk /2 11 9.77 khz 1 1 1 1 1 x x x x inttm02 note2 other than above setting prohibited notes 1. when changing the clock selected for f clk (by changing the system clock control register (ckc) value), do so after having stopped (st0 = 000fh) the operation of the serial array unit (sau). when selecting inttm02 for the operation clock, al so stop the timer array unit taus (tt0 = 00ffh). 2. sau can be operated at a fixed division ratio of the subsystem clock, regardless of the f clk frequency (main system clock, subsystem clock), by setting the tis02 bit of the tis0 register of taus to 1, selecting f sub /4 for the input clock, and selecti ng inttm02 using the sps0 register. when changing f clk , however, sau and taus must be stopped as described in note 1 above. remarks 1. x: don?t care 2. n: channel number (n = 0 to 2) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 459 12.6 operation of uart (uart0, uart1) communication this is a start-stop synchronization function using two lines: serial data transmission (txd) and serial data reception (rxd) lines. it transmits or receives data in asyn chronization with the party of communication (by using an internal baud rate). full-duplex uart communication can be realized by using two channels, one dedicated to transmission (even channel) and the other to reception (odd channel). [data transmission/reception] ? data length of 5, 7, or 8 bits ? select the msb/lsb first ? level setting of transmit/recei ve data and select of reverse ? parity bit appending and parity check functions ? stop bit appending [interrupt function] ? transfer end interrupt/buffer empty interrupt ? error interrupt in case of framing error, parity error, or overrun error [error detection flag] ? framing error, parity error, or overrun error the lin-bus is supported in uart0 (0, 1 channels of unit) [lin-bus functions] ? wakeup signal detection ? sync break field (sbf) detection ? sync field measurement, baud rate calculation uart0 uses channels 0 and 1 of sau. uart1 uses channels 2 and 3 of sau. channel used as csi used as uart used as simplified i 2 c 0 csi00 uart0 (supporting lin-bus) ? 1 csi01 ? 2 csi10 uart1 iic10 3 ? ? uart performs the following four types of communication operations. ? uart transmission (see 12.6.1 .) ? uart reception (see 12.6.2 .) ? lin transmission (uart0 only) (see 12.6.3 .) ? lin reception (uart0 only) (see 12.6.4 .) external interrupt (intp0) or timer array unit taus is used. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 460 12.6.1 uart transmission uart transmission is an operation to transmit data from the 78k0r/kx3-l to another device asynchronously (start- stop synchronization). of two channels used for uart, the even channel is used for uart transmission. uart uart0 uart1 target channel channel 0 of sau channel 2 of sau pins used txd0 txd1 intst0 intst1 interrupt transfer end interrupt (in single-transfer mode) or buff er empty interrupt (in continuous transfer mode) can be selected. error detection flag none transfer data length 5, 7, or 8 bits transfer rate max. f mck /6 [bps] (sdr0n [15:9] = 2 or more), min. f clk /(2 2 11 128) [bps] note data phase forward output (default: high level) reverse output (default: low level) parity bit the following selectable ? no parity bit ? appending 0 parity ? appending even parity ? appending odd parity stop bit the following selectable ? appending 1 bit ? appending 2 bits data direction msb or lsb first note use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 28 electrical specifications (target) ). remarks 1. f mck : operation clock (mck) frequency of target channel f clk : system clock frequency 2. n: channel number (n = 0, 2) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 461 (1) register setting figure 12-67. example of contents of registers for uart transmission of uart (uart0, uart1) (1/2) (a) serial output register 0 (so0) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 cko01 cko00 0 0 0 0 1 so02 0/1 note so01 so00 0/1 note (b) serial output enable register 0 (soe0) ? se ts only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 soe01 soe00 0/1 (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 ss00 0/1 (d) serial output level register 0 (sol0) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sol0 0 0 0 0 0 0 0 0 0 0 0 0 0 sol02 0/1 0 sol00 0/1 0: forward (normal) transmission 1: reverse transmission (e) serial mode register 0n (smr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks0n 0/1 ccs0n 0 0 0 0 0 0 sts0n 0 0 sis0n0 0 1 0 0 md0n2 0 md0n1 1 md0n0 0/1 operation mode of channel n 0: transfer end interrupt 1: buffer empty interrupt note before transmission is started, be sure to set to 1 wh en the sol0n bit of the target channel is set to 0, and set to 0 when the sol0n bit of the target channel is set to 1. the value varies depending on the communication data during communication operation. remark n: channel number (n = 0, 2) : setting is fixed in the uart transmission mode, : setting disabled (fixed by hardware) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 462 figure 12-67. example of contents of registers for uart transmission of uart (uart0, uart1) (2/2) (f) serial communication operation setting register 0n (scr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe0n 1 rxe0n 0 dap0n 0 ckp0n 0 0 eoc0n 0 ptc0n1 0/1 ptc0n0 0/1 dir0n 0/1 0 slc0n1 0/1 slc0n0 0/1 0 dls0n2 1 dls0n1 0/1 dls0n0 0/1 setting of stop bit 01b: appending 1 bit 10b: appending 2 bits setting of parity bit 00b: no parity 01b: 0 parity 10b: even parity 11b: odd parity (g) serial data register 0n (sdr0n) (lower 8 bits: txdq) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n baud rate setting 0 transmit data setting remark n: channel number (n = 0, 2), q: uart number (q = 0, 1) : setting is fixed in the uart transmission mode, : setting disabled (set to the initial value) 0/1: set to 0 or 1 depending on the usage of the user txdq chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 463 (2) operation procedure figure 12-68. initial setting procedure for uart transmission caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. starting initial setting setting per0 register setting sps0 register setting smr0n register setting scr0n register setting sdr0n register setting so0 register setting port changing setting of soe0 register writing to ss0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. manipulate the so0n bit and set an initial output level. enable data output of the target channel by setting a port register and a port mode register. set the soe0n bit to 1 and enable data output of the target channel. se0n = 1 when the ss0n bit of the target channel is set to 1. set transmit data to the txdq register (bits 7 to 0 of the sdr0n register) and start communication. changing setting of sol0 register set an output data level. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 464 figure 12-69. procedure for stopping uart transmission remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the so0 register (see figure 12-70 procedure for resuming uart transmission ). starting setting to stop setting st0 register stopping communication write 1 to the st0n bit of the target channel. stop communication in midway. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 465 figure 12-70. procedure for resuming uart transmission port manipulation changing setting of sps0 register changing setting of sdr0 register changing setting of smr0n register changing setting of so0 register port manipulation writing to ss0 register starting communication disable data output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if an incorrect transfer baud rate is set. change the setting if the setting of the smr0n register is incorrect. manipulate the so0n bit and set an initial output level. enable data output of the target channel by setting a port register and a port mode register. se0n = 1 when the ss0n bit of the target channel is set to 1. sets transmit data to the txdq register (bits 7 to 0 of the sdr0n register) and start communication. (essential) (selective) (essential) changing setting of soe0 register set the soe0n bit to 1 and enable output. changing setting of soe0 register clear the soe0n bit to 0 and stop output. (essential) changing setting of scr0n register change the setting if the setting of the scr0n register is incorrect. changing setting of sol0n register change the setting if the setting of the sol0n register is incorrect. starting setting for resumption (essential) (essential) (essential) (essential) (selective) (selective) (selective) (selective) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 466 (3) processing flow (in si ngle-transmission mode) figure 12-71. timing chart of uart tr ansmission (in single-transmission mode) ss0n se0n sdr0n txdq pin shift register 0n intstq tsf0n data transmission (7-bit length) data transmission (7-bit length) data transmission (7-bit length) p transmit data 1 transmit data 2 transmit data 3 transmit data 3 transmit data 2 transmit data 1 shift operation shift operation shift operation sp st st p sp st p sp remark n: channel number (n = 0, 2), q: uart number (q = 0, 1) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 467 figure 12-72. flowchart of uart tran smission (in single-transmission mode) caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. starting uart communication writing 1 to ss0n bit writing transmit data to txdq (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate sol0n: setting output data level so0, soe0: setting output transfer end interrupt g enerated? transmission completed? no no yes yes setting sau0en bit of per0 register to 1 setting transfer rate by sps0 register port manipulation end of communication clearing sau0en bit of per0 register to 0 chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 468 (4) processing flow (in continuous transmission mode) figure 12-73. timing chart of uart transmission (in continuous transmission mode) ss0n se0n sdr0n t x dq pin shift register 0n intstq tsf0n data transmission (7-bit length) data transmission (7-bit length) p transmit data 1 transmit data 2 transmit data 3 transmit data 3 transmit data 2 transmit data 1 shift operation shift operation shift operation sp st st p sp st p sp bff0n <1> <2> <2> <3> ( note ) <2> <3> <5> <3> <4> md0n0 data transmission (7-bit length) note when transmit data is written to the sdr0n register while bff0n = 1, the transmit data is overwritten. caution the md0n0 bit can be re written even during operation. however, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data. remark n: channel number (n = 0, 2), q: uart number (q = 0, 1) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 469 figure 12-74. flowchart of uart transmission (in continuous transmission mode) starting uart communication writing 1 to ss0n bit writing transmit data to txdq (=sdr0n[7:0]) writing 1 to st0n bit perform initial setting when se0n = 0. <1> select the buffer empty interrupt. smr0n, scr0n: setting communication sdr0n[15:9]: setting transfer rate sol0n: setting output data level so0, soe0: setting output n o n o n o y es setting sau0en bit of per0 register to 1 setting transfer rate by sps0 register port manipulation end of communication clearing 0 to md0n0 bit y es tsf0n = 1? transfer end interrupt g enerated? n o y es n o communication continued? y es y es clearing sau0en bit of per0 register to 0 transmitting next data? <2> <3> buffer empty interrupt generated? writing 1 to md0n0 bit <4> <5> caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. remark <1> to <5> in the figure correspond to <1> to <5> in figure 12-73 timing chart of uart transmission (in continuous transmission mode) . chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 470 12.6.2 uart reception uart reception is an operation wherein the 78k0r/kx3-l asynchronously receives data from another device (start-stop synchronization). for uart reception, the odd channel of the two channels used for uart is used. uart uart0 uart1 target channel channel 1 of sau channel 3 of sau pins used rxd0 rxd1 intsr0 intsr1 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error interrupt intsre0 intsre1 error detection flag ? framing error detection flag (fef0n) ? parity error detection flag (pef0n) ? overrun error detection flag (ovf0n) transfer data length 5, 7 or 8 bits transfer rate max. f mck /6 [bps] (sdr0n [15:9] = 2 or more), min. f clk /(2 2 11 128) [bps] note data phase forward output (default: high level) reverse output (default: low level) parity bit the following selectable ? no parity bit (no parity check) ? appending 0 parity (no parity check) ? appending even parity ? appending odd parity stop bit appending 1 bit data direction msb or lsb first note use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 28 electrical specifications (target) ). remarks 1. f mck : operation clock (mck) frequency of target channel f clk : system clock frequency 2. n: channel number (n = 1, 3) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 471 (1) register setting figure 12-75. example of contents of registers for uart reception of uart (uart0, uart1) (1/2) (a) serial output register 0 (so0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 cko01 cko00 0 0 0 0 1 so02 so01 so00 (b) serial output enable register 0 (soe0) ? se ts only the bits of the target channel is 0. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 soe01 0/1 soe00 (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel is 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 0/1 ss02 ss01 0/1 ss00 (d) serial mode register 0n (smr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0n cks0n 0/1 ccs0n 0 0 0 0 0 0 sts0n 1 0 sis0n0 0/1 1 0 0 md0n2 0 md0n1 1 md0n0 0 0: forward (normal) reception 1: reverse reception operation mode of channel n 0: transfer end interrupt (e) serial mode register 0r (smr0r) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr0r cks0r 0/1 ccs0r 0 0 0 0 0 0 sts0r 0 0 sis0r0 0 1 0 0 md0r2 0 md0r1 1 md0r0 0/1 same setting value as cks0n operation mode of channel r 0: transfer end interrupt caution for the uart reception, be sure to set smr0r of channel r that is to be paired with channel n. remark n: channel number (n = 1, 3), r: channel number (r = n ? 1) : setting is fixed in the uart reception mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 472 figure 12-75. example of contents of registers for uart reception of uart (uart0, uart1) (2/2) (f) serial communication operation setting register 0n (scr0n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr0n txe0n 0 rxe0n 1 dap0n 0 ckp0n 0 0 eoc0n 1 ptc0n1 0/1 ptc0n0 0/1 dir0n 0/1 0 slc0n1 0 slc0n0 1 0 dls0n2 1 dls0n1 0/1 dls0n0 0/1 (g) serial data register 0n (sdr0n) (lower 8 bits: rxdq) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr0n baud rate setting 0 receive data register remark n: channel number (n = 1, 3), q: uart number (q = 0, 1) : setting is fixed in the uart reception mode, : setting disabled (set to the initial value) 0/1: set to 0 or 1 depending on the usage of the user rxdq chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 473 (2) operation procedure figure 12-76. initial setting procedure for uart reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. figure 12-77. procedure for stopping uart reception starting initial setting setting per0 register setting sps0 register setting smr0n and smr0r registers setting scr0n register setting sdr0n register writing to ss0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. se0n = 1 when the ss0n bit of the target channel is set to 1. the start bit is detected. starting setting to stop setting st0 register stopping communication write 1 to the st0n bit of the target channel. stop communication in midway. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 474 figure 12-78. procedure for resuming uart reception starting setting for resumption manipulating target for communication changing setting of sps0 register changing setting of sdr0n register writing to ss0 register starting communication stop the target for communication or wait until the target completes its operation. change the setting if an incorrect division ratio of the operation clock is set. change the setting if an incorrect transfer baud rate is set. change the setting if the setting of the smr0n and smr0r registers is incorrect. se0n = 1 when the ss0n bit of the target channel is set to 1. the start bit is detected. (essential) (selective) change the setting if the setting of the scr0n register is incorrect. changing setting of scr0n register cleared by using sir0n register if fef, pef, or ovf flag remains set. clearing error flag clear the soe0 register to 0 and stop data output of the target channel. changing setting of soe0 register changing setting of smr0n and smr0r registers (essential) (essential) (essential) (selective) (selective) (selective) (selective) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 475 (3) processing flow figure 12-79. timing chart of uart reception ss0n se0n sdr0n rxdq pin shift register 0n intsrq tsf0n data reception (7-bit length) data reception (7-bit length) data reception (7-bit length) p receive data 1 receive data 2 receive data 3 receive data 2 receive data 1 shift operation shift operation shift operation sp st st p sp st p sp receive data 3 remark n: channel number (n = 1, 3), q: uart number (q = 0, 1) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 476 figure 12-80. flowchart of uart reception caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. starting uart communication writing 1 to ss0n bit writing 1 to st0n bit end of uart communication perform initial setting when se0n = 0. smr0n, smr0r, scr0n: setting communication sdr0n[15:9]: setting transfer rate so0: set cko0n and so0n bits to 1 transfer end interrupt g enerated? reception completed? no no yes yes starting reception reading rxdq register (sdr0n[7:0]) detecting start bit error interrupt generated? error processing no yes port manipulation clearing sau0en bit of per0 register to 0 setting sau0en bit of per0 register to 1 setting transfer rate by sps0 register chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 477 12.6.3 lin transmission of uart transmission, uart0 supports lin communication. for lin transmission, channel 0 of unit (sau) is used. uart uart0 uart1 support of lin communication supported not supported target channel channel 0 of sau ? pins used txd0 ? intst0 ? interrupt transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. error detection flag none transfer data length 8 bits transfer rate max. f mck /6 [bps] (sdr00 [15:9] = 2 or more), min. f clk /(2 2 11 128) [bps] note data phase forward output (default: high level) reverse output (default: low level) parity bit the following selectable ? no parity bit ? appending 0 parity ? appending even parity ? appending odd parity stop bit the following selectable ? appending 1 bit ? appending 2 bits data direction msb or lsb first note use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 28 electrical specifications (target) ). remark f mck : operation clock (mck) frequency of target channel f clk : system clock frequency lin stands for local interconnect network and is a low-s peed (1 to 20 kbps) serial communication protocol designed to reduce the cost of an automobile network. communication of lin is single-master communicatio n and up to 15 slaves can be connected to one master. the slaves are used to control switches, actuators, and sensors, which are connect ed to the master via lin. usually, the master is connected to a network such as can (controller area network). a lin bus is a single-wire bus to which nodes are connected via transceiver conforming to iso9141. according to the protocol of lin, the master transmits a frame by attach ing baud rate information to it. a slave receives this frame and corrects a baud rate error from t he master. if the baud rate error of a slave is within 15%, communication can be established. figure 12-81 outlines a trans mission operation of lin. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 478 figure 12-81. transmission operation of lin lin bus wakeup signal frame 8 bits note 1 55h transmission data transmission data transmission data transmission data transmission 13-bit sbf transmission note 2 sync break field sync field identification field data field data field checksum field t x d0 (output) intst0 note 3 notes 1. the baud rate is set so as to satisfy the standard of the wakeup signal and data of 00h is transmitted. 2. a sync break field is defined to have a width of 13 bits and output a low level. where the baud rate for main transfer is n [bps], therefore, the baud rate of the sync break field is calculated as follows. (baud rate of sync break field) = 9/13 n by transmitting data of 00h at this baud rate, a sync break field is generated. 3. intst0 is output upon completion of transmission. intst0 is also output when sbf transmission is executed. remark the interval between fields is controlled by software. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 479 figure 12-82. flowchart for lin transmission starting lin communication writing 1 to ss00 transmitting wakeup signal frame transmitting sync break field writing 1 to st00 end of lin communication sync break field identification field data field checksum field sync field transfer end interrupt g enerated? transfer end interrupt g enerated? writing 1 to ss00 transmitting 55h wakeup signal frame setting baud rate setting transfer data 00h setting transfer data 00h setting baud rate receiving data chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 480 12.6.4 lin reception of uart reception, uart0 supports lin communication. for lin reception, channel 1 of unit (sau) is used. uart uart0 uart1 support of lin communication supported not supported target channel channel 1 of sau ? pins used rxd0 ? intsr0 ? interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error interrupt intsre0 ? error detection flag ? framing error detection flag (fef01) ? parity error detection flag (pef01) ? overrun error detection flag (ovf01) transfer data length 8 bits transfer rate max. f mck /6 [bps] (sdr01 [15:9] = 2 or more), min. f clk /(2 2 11 128) [bps] note data phase forward output (default: high level) reverse output (default: low level) parity bit the following selectable ? no parity bit ? appending 0 parity ? appending even parity ? appending odd parity stop bit the following selectable ? appending 1 bit ? appending 2 bits data direction msb or lsb first note use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 28 electrical specifications (target) ). remark f mck : operation clock (mck) frequency of target channel f clk : system clock frequency figure 12-83 outlines a rec eption operation of lin. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 481 figure 12-83. reception operation of lin lin bus 13-bit sbf reception sf reception id reception data reception data reception data reception wakeup signal frame sync break field sync field identification field data filed data filed checksum field r x d0 (input) reception interrupt (intsr0) edge detection (intp0) capture timer disable enable disable enable <1> <2> <3> <4> <5> here is the flow of signal processing. <1> the wakeup signal is detected by detecting an interr upt edge (intp0) on a pin. when the wakeup signal is detected, enable reception of uart0 (r xe01 = 1) and wait for sbf reception. <2> when the start bit of sbf is detect ed, reception is started and serial da ta is sequentially stored in the rxd0 register (= bits 7 to 0 of the serial data register 01 (sdr01)) at the set baud rate. when the stop bit is detected, the reception end interrupt request (intsr0) is generated. when data of low levels of 11 bits or more is detected as sbf, it is judged that sbf receptio n has been correctly completed. if data of low levels of less than 11 bits is detected as sbf, it is judged t hat an sbf reception error has occurred, and the system returns to the sbf reception wait status. <3> when sbf reception has been correctly completed, start channel 7 of the timer array unit taus and measure the bit interval (pulse width) of the sync field (see 6.7.5 operation as input signal high-/low-level width measurement ). <4> calculate a baud rate error from the bit interval of sync field (sf). stop uart0 once and adjust (re-set) the baud rate. <5> the checksum field should be distinguished by software. in addition, processing to initialize uart0 after the checksum field is received and to wait for reception of sbf should also be performed by software. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 482 figure 12-84 shows the configuration of a port that manipulates reception of lin. the wakeup signal transmitted from the master of lin is received by detecting an edge of an external interrupt (intp0). the length of the sync fi eld transmitted from the master can be measured by using the external event capture operation of the timer array unit taus to calculate a baud-rate error. by controlling switch of port input (i sc0/isc1), the input source of port input (rxd0) for reception can be input to the external interrupt pin (intp0) and timer array unit taus. figure 12-84. port configuration for manipulating reception of lin p74/kr4/si00/rxd0 p120/intp0/ exlvi p15/ti07/to07 rxd0 input intp0 input channel 7 input of taus port input switch control (isc0) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 483 the peripheral functions used for the lin communication operation are as follows. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 484 figure 12-85. flowchart of lin reception starting lin communication detecting low-level width detecting low-level width stopping operation detecting high-level width end of lin communication sync break field identification field data field checksum field sync field sbf detected? writing 1 to st01 writing 1 to ss01 wakeup signal frame setting taus in capture mode (to measure low-level width) detecting low-level width receiving data wakeup detected? setting taus in capture mode (to measure low-/high-level width) detecting low-level width setting uart reception mode calculating baud rate detecting high-level width intp0, taus sau for details, see figure 12-80 chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 485 12.6.5 calculating baud rate (1) baud rate calculation expression the baud rate for uart (uart0, uart1) communication can be calculated by the following expressions. (baud rate) = {operation clock (mck) frequency of target channel} (sdr0n[15:9] + 1) 2 [bps] caution setting sdr0n [15:9] = (0000000b, 0000001b) is prohibited. remarks 1. when uart is used, the value of sdr0n[15:9] is the value of bits 15 to 9 of the sdr0n register (0000010b to 1111111b) and therefore is 2 to 127. 2. n: channel number (n = 0 to 3) the operation clock (mck) is determined by serial clock select register 0 (sps0) and bit 15 (cks0n) of serial mode register 0n (smr0n). chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 486 table 12-3. selection of operation clock smr0n register sps0 register operation clock (mck) note1 cks0n prs 013 prs 012 prs 011 prs 010 prs 003 prs 002 prs 001 prs 000 f clk = 20 mhz x x x x 0 0 0 0 f clk 20 mhz x x x x 0 0 0 1 f clk /2 10 mhz x x x x 0 0 1 0 f clk /2 2 5 mhz x x x x 0 0 1 1 f clk /2 3 2.5 mhz x x x x 0 1 0 0 f clk /2 4 1.25 mhz x x x x 0 1 0 1 f clk /2 5 625 khz x x x x 0 1 1 0 f clk /2 6 313 khz x x x x 0 1 1 1 f clk /2 7 156 khz x x x x 1 0 0 0 f clk /2 8 78.1 khz x x x x 1 0 0 1 f clk /2 9 39.1 khz x x x x 1 0 1 0 f clk /2 10 19.5 khz x x x x 1 0 1 1 f clk /2 11 9.77 khz 0 x x x x 1 1 1 1 inttm02 note2 0 0 0 0 x x x x f clk 20 mhz 0 0 0 1 x x x x f clk /2 10 mhz 0 0 1 0 x x x x f clk /2 2 5 mhz 0 0 1 1 x x x x f clk /2 3 2.5 mhz 0 1 0 0 x x x x f clk /2 4 1.25 mhz 0 1 0 1 x x x x f clk /2 5 625 khz 0 1 1 0 x x x x f clk /2 6 313 khz 0 1 1 1 x x x x f clk /2 7 156 khz 1 0 0 0 x x x x f clk /2 8 78.1 khz 1 0 0 1 x x x x f clk /2 9 39.1 khz 1 0 1 0 x x x x f clk /2 10 19.5 khz 1 0 1 1 x x x x f clk /2 11 9.77 khz 1 1 1 1 1 x x x x inttm02 note2 other than above setting prohibited notes 1. when changing the clock selected for f clk (by changing the system clock control register (ckc) value), do so after having stopped (st0 = 000fh) the operation of the serial array unit (sau). when selecting inttm02 for the operation clock, al so stop the timer array unit taus (tt0 = 00ffh). 2. sau can be operated at a fixed division ratio of the subsystem clock, regardless of the f clk frequency (main system clock, subsystem clock), by setting the tis02 bit of the tis0 register of taus to 1, selecting f sub /4 for the input clock, and selecti ng inttm02 using the sps0 register. when changing f clk , however, sau and taus must be stopped as described in note 1 above. remarks 1. x: don?t care 2. n: channel number (n = 0 to 3) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 487 (2) baud rate error during transmission the baud rate error of uart (uart0, uart1) communication during transmission can be calculated by the following expression. make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side. (baud rate error) = (calculated baud rate value) (target baud rate) 100 ? 100 [%] here is an example of setting a uart baud rate at f clk = 20 mhz. f clk = 20 mhz uart baud rate (target baud rate) operation clock (mck) sdr0n[15:9] calculat ed baud rate error from target baud rate 300 bps f clk /2 9 64 300.48 bps +0.16 % 600 bps f clk /2 8 64 600.96 bps +0.16 % 1200 bps f clk /2 7 64 1201.92 bps +0.16 % 2400 bps f clk /2 6 64 2403.85 bps +0.16 % 4800 bps f clk /2 5 64 4807.69 bps +0.16 % 9600 bps f clk /2 4 64 9615.38 bps +0.16 % 19200 bps f clk /2 3 64 19230.8 bps +0.16 % 31250 bps f clk /2 3 39 31250.0 bps 0.0 % 38400 bps f clk /2 2 64 38461.5 bps +0.16 % 76800 bps f clk /2 64 76923.1 bps +0.16 % 153600 bps f clk 64 153846 bps +0.16 % 312500 bps f clk 31 312500 bps 0.0 % remark n: channel number (n = 0, 2) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 488 (3) permissible baud rate range for reception the permissible baud rate range for reception during uart (uart0, uart1) communication can be calculated by the following expression. make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side. 2 k nfr (maximum receivable baud rate) = 2 k nfr ? k + 2 brate 2 k (nfr ? 1) (minimum receivable baud rate) = 2 k nfr ? k ? 2 brate brate: calculated baud rate value at the reception side (see 12.6.5 (1) baud rate calculation expression .) k: sdr0n[15:9] + 1 nfr: 1 data frame length [bits] = (start bit) + (data length) + (parity bit) + (stop bit) remark n: channel number (n = 1, 3) figure 12-86. permissible baud rate range fo r reception (1 data frame length = 11 bits) fl 1 data frame (11 fl) (11 fl) min. (11 fl) max. data frame length of sau start bit bit 0 bit 1 bit 7 parity bit permissible minimum data frame length permissible maximum data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 12-86, the timing of latching receive data is determined by the division ratio set by bits 15 to 9 of the serial data register 0n (sdr0n) after the start bit is detected. if the last data (stop bit) is received before this latch timing, the data can be correctly received. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 489 12.7 operation of simplified i 2 c (iic10) communication this is a clocked communication function to communicate with two or more devices by using two lines: serial clock (scl) and serial data (sda). this communication functi on is designed to execute single communication with devices such as eeprom, flash memory, and a/d converter, and theref ore, can be used only by the master and does not have a wait detection function. make sure by using software, as well as operating the c ontrol registers, that the ac specifications of the start and stop conditions are observed. [data transmission/reception] ? master transmission, master reception (onl y master function with a single master) ? ack output function note and ack detection function ? data length of 8 bits (when an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is used for r/w control.) ? manual generation of start condition and stop condition [interrupt function] ? transfer end interrupt [error detection flag] ? parity error (ack error) * [functions not supported by simplified i 2 c] ? slave transmission, slave reception ? arbitration loss detection function ? wait detection function note when receiving the last data, ack will not be output if 0 is written to the soe02 (soe0 register) bit and serial communication data output is stopped. see the processing flow in 12.7.3 (2) for details. remark to use an i 2 c bus of full function, see chapter 13 serial interface iica . the channel supporting simplified i 2 c (iic10) is channel 2 of sau. channel used as csi used as uart used as simplified i 2 c 0 csi00 ? 1 csi01 uart0 (supporting lin-bus) ? 2 csi10 uart1 iic10 3 ? ? simplified i 2 c (iic10) performs the following four types of communication operations. ? address field transmission (see 12.7.1 .) ? data transmission (see 12.7.2 .) ? data reception (see 12.7.3 .) ? stop condition generation (see 12.7.4 .) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 490 12.7.1 address field transmission address field transmission is a transmission operation that first executes in i 2 c communication to identify the target for transfer (slave). after a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are transmitted in one frame. simplified i 2 c iic10 target channel channel 2 of sau pins used scl10, sda10 intiic10 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error detection flag parity error detection flag (pef02) transfer data length 8 bits (transmitted with specifying the higher 7 bits as address and the least significant bit as r/w control) transfer rate max. f clk /4 mhz f clk : system clock frequency however, the following condition must be satisfied in each mode of i 2 c. ? max. 400 khz (first mode) ? max. 100 khz (standard mode) data level forward output (default: high level) parity bit no parity bit stop bit appending 1 bit (for ack reception timing) data direction msb first chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 491 (1) register setting figure 12-87. example of contents of register s for address field transmission of simplified i 2 c (iic10) (a) serial output register 0 (so0) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 0/1 cko01 cko00 0 0 0 0 1 so02 0/1 so01 so00 start condition is generated by manipulating the so02 bit. (b) serial output enable register 0 (soe0) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 soe01 soe00 soe02 = 0 until the start condition is generated, and soe02 = 1 after generation. (c) serial channel start register 0 (ss0) ? sets only the bits of the target channel is 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 ss00 (d) serial mode register 02 (smr02) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr02 cks02 0/1 ccs02 0 0 0 0 0 0 sts02 0 0 sis020 0 1 0 0 md022 1 md021 0 md020 0 operation mode of channel 2 0: transfer end interrupt (e) serial communication operati on setting register 02 (scr02) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr02 txe02 1 rxe02 0 dap02 0 ckp02 0 0 eoc02 0 ptc021 0 ptc020 0 dir02 0 0 slc021 0 slc020 1 0 dls022 1 dls021 1 dls020 1 setting of parity bit 00b: no parity setting of stop bit 01b: appending 1 bit (ack) (f) serial data register 02 (sdr02) (lower 8 bits: sio10) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr02 baud rate setting 0 transmit data setting (address + r/w) remark : setting is fixed in the iic mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user sio10 chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 492 (2) operation procedure figure 12-88. initial setting proce dure for address field transmission caution after setting the per0 register to 1, be sure to set the sps0 register after 4 or more clocks have elapsed. starting initial setting setting per0 register setting sps0 register setting smr02 register setting scr02 register setting sdr02 register setting so0 register setting port setting so0 register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. manipulate the so02 and cko02 bits and set an initial output level. enable data output, clock output, and n-ch open-drain output (v dd tolerance) mode of the target channel by setting the port register, port mode register, and port output mode register. clear the so02 bit to 0 to generate the start condition. set address and r/w to the sio10 register (bits 7 to 0 of the sdr02 register) and start communication. writing to ss0 register se02 = 1 when the ss02 bit of the target channel is set to 1. setting so0 register clear the cko02 bit to 0 to lower the clock output level. changing setting of soe0 register set the soe02 bit to 1 and enable data output of the target channel. secure a wait time so that the specifications of i 2 c on the slave side are satisfied. wait chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 493 (3) processing flow figure 12-89. timing chart of address field transmission d7 d6 d5 d4 address d3 shift operation d2 d1 d0 r/w d7 d6 address field transmission ss02 se02 soe02 sdr02 scl10 output sda10 output sda10 input shift register 02 intiic10 tsf02 transmit data 1 d5 d4 d3 d2 d1 d0 ack so02 bit manipulation cko02 bit manipulation chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 494 figure 12-90. flowchart of address field transmission starting iic communication writing 0 to so02 bit address field transmission completed perform initial setting when se02 = 0. smr02, scr02: setting communication sps0, sdr02[15:9]: setting transfer rate transfer end interrupt g enerated? no yes writing address and r/w data to sio10 (sdr02[7:0]) writing 1 to ss02 bit parity error (ack error) flag pef02 = 1 ? no yes ack reception error to data transmission flow and data reception flow writing 1 to soe02 bit writing 0 to cko02 bit chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 495 12.7.2 data transmission data transmission is an operation to transmit data to the ta rget for transfer (slave) after transmission of an address field. after all data are transmitted to the slave, a stop condition is generated and the bus is released. simplified i 2 c iic10 target channel channel 2 of sau pins used scl10, sda10 intiic10 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error detection flag parity error detection flag (pef02) transfer data length 8 bits transfer rate max. f clk /4 mhz f clk : system clock frequency however, the following condition must be satisfied in each mode of i 2 c. ? max. 400 khz (first mode) ? max. 100 khz (standard mode) data level forward output (default: high level) parity bit no parity bit stop bit appending 1 bit (for ack reception timing) data direction msb first chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 496 (1) register setting figure 12-91. example of contents of regist ers for data transmission of simplified i 2 c (iic10) (a) serial output register 0 (so0) ? do not manipulate this regi ster during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 0/1 note cko01 cko00 0 0 0 0 1 so02 0/1 note so01 so00 (b) serial output enable register 0 (soe0) ? do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 1 soe01 soe00 (c) serial channel start register 0 (ss0) ? do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 ss00 (d) serial mode register 02 (smr02) ? do not manipulate this re gister during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr02 cks02 0/1 ccs02 0 0 0 0 0 0 sts02 0 0 sis020 0 1 0 0 md022 1 md021 0 md020 0 (e) serial communication operation se tting register 02 (scr02) ? do not manipulate the bits of this register, except the txe02 and rxe02 bits, during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr02 txe02 1 rxe02 0 dap02 0 ckp02 0 0 eoc02 0 ptc021 0 ptc020 0 dir02 0 0 slc021 0 slc020 1 0 dls022 1 dls021 1 dls020 1 (f) serial data register 02 (sdr02) (lower 8 bits: sio10) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr02 baud rate setting 0 transmit data setting note the value varies depending on the communication data during communication operation. remark : setting is fixed in the iic mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user sio10 chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 497 (2) processing flow figure 12-92. timing chart of data transmission d7 d6 d5 d4 d3 shift operation d2 d1 d0 d7 ?l? ?h? ?h? d6 transmit data 1 ss02 se02 soe02 sdr02 scl10 output sda10 output sda10 input shift register 02 intiic10 tsf02 transmit data2 d5 d4 d3 d2 d1 d0 ack figure 12-93. flowchart of data transmission starting data transmission data transmission completed transfer end interrupt g enerated? no yes writing data to sio10 (sdr02[7:0]) no yes ack reception error s top con di t i on generat i on data transfer completed? yes no address field transmission completed parity error (ack error) flag pef02 = 1 ? chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 498 12.7.3 data reception data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field. after all data are received to the slave, a stop condition is generated and the bus is released. simplified i 2 c iic10 target channel channel 2 of sau pins used scl10, sda10 intiic10 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error detection flag none transfer data length 8 bits transfer rate max. f clk /4 mhz f clk : system clock frequency however, the following condition must be satisfied in each mode of i 2 c. ? max. 400 khz (first mode) ? max. 100 khz (standard mode) data level forward output (default: high level) parity bit no parity bit stop bit appending 1 bit (ack transmission) data direction msb first chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 499 (1) register setting figure 12-94. example of contents of regi sters for data reception of simplified i 2 c (iic10) (a) serial output register 0 (so0) ? do not manipulate this regi ster during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 0/1 note cko01 cko00 0 0 0 0 1 so02 0/1 note so01 so00 (b) serial output enable register 0 (soe0) ? do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 1 soe01 soe00 (c) serial channel start register 0 (ss0) ? do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 0/1 ss01 ss00 (d) serial mode register 02 (smr02) ? do not manipulate this re gister during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smr02 cks02 0/1 ccs02 0 0 0 0 0 0 sts02 0 0 sis020 0 1 0 0 md022 1 md021 0 md020 0 (e) serial communication operation se tting register 02 (scr02) ? do not manipulate the bits of this register, except the txe02 and rxe02 bits, during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scr02 txe02 0 rxe02 1 dap02 0 ckp02 0 0 eoc02 0 ptc021 0 ptc020 0 dir02 0 0 slc021 0 slc020 1 0 dls022 1 dls021 1 dls020 1 (f) serial data register 02 (sdr02) (lower 8 bits: sio10) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdr02 baud rate setting 0 dummy transmit data setting (ffh) note the value varies depending on the communication data during communication operation. remark : setting is fixed in the iic mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user sio10 chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 500 (2) processing flow figure 12-95. timing chart of data reception (a) when starting data reception d7 d6 d5 d4 d3 d2 d1 d0 soe02 sdr02 intiic10 tsf02 ack txe02 = 0 / rxe02 = 1 txe02, rxe02 txe02 = 1 / rxe02 = 0 shift operation ?h? dummy data (ffh) scl10 output sda10 output sda10 input shift register 02 receive data ss02 se02 st02 (b) when receiving last data d7 d6 d5 d4 d3 d2 d1 d0 d2 d1 d0 st02 se02 soe02 sdr02 scl10 output sda10 output sda10 input shift register 02 intiic10 tsf02 nack ack txe0 2 = 0 / rxe0 2 = 1 txe02, rxe02 iic operation stop so02 bit manipulation cko02 bit manipulation so02 bit manipulation shift operation shift operation dummy data (ffh) dummy data (ffh) receive data output enable by serial communication operation receive data output stop by serial communication operation last byte reception stop condition remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), r: iic number (r = 10, 20) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 501 figure 12-96. flowchart of data reception caution ack is not output when the last data is received (nack). communication is then completed by setting ?1? to the st02 bit to st op operation and generating a stop condition. starting data reception data reception completed no yes writing dummy data (ffh) to sio10 (sdr02[7:0]) stop condition g eneration yes no reading sio10 (sdr02[7:0]) address field tran smission completed writing 1 to st02 bit writing 0 to txe02 bit, and 1 to rxe02 bit writing 1 to ss02 bit last byte received? yes writing 0 to soe02 bit (output stop by serial communication operation) data transfer completed? no transfer end interrupt generated? chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 502 12.7.4 stop condition generation after all data are transmitted to or received from the ta rget slave, a stop condition is generated and the bus is released. (1) processing flow figure 12-97. timing chart of stop condition generation stop condition st02 se02 soe02 scl10 output sda10 output operation stop so02 bit manipulation cko02 bit manipulation so02 bit manipulation note note during a receive operation, the soe02 bit is cl eared to 0 before receiving the last data. figure 12-98. flowchart of stop condition generation starting generation of stop condition. end of iic communication writing 1 to st02 bit to clear (se02 is cleared to 0) writing 0 to soe02 bit writing 1 to so02 bit writing 1 to cko02 bit writing 0 to so02 bit completion of data transmission/data reception wait secure a wait time so that the specifications of i 2 c on the slave side are satisfied. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 503 12.7.5 calculating transfer rate the transfer rate for simplified i 2 c (iic10) communication can be calculated by the following expressions. (transfer rate) = {operation clock (mck) frequency of target channel} (sdr02[15:9] + 1) 2 remark the value of sdr02[15:9] is the value of bits 15 to 9 of the sdr02 register (0000000b to 1111111b) and therefore is 0 to 127. the operation clock (mck) is determined by serial clock select register 0 (sps0) and bit 15 (cks02) of serial mode register 02 (smr02). chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 504 table 12-4. selection of operation clock smr02 register sps0 register operation clock (mck) note 1 cks02 prs 013 prs 012 prs 011 prs 010 prs 003 prs 002 prs 001 prs 000 f clk = 20 mhz x x x x 0 0 0 0 f clk 20 mhz x x x x 0 0 0 1 f clk /2 10 mhz x x x x 0 0 1 0 f clk /2 2 5 mhz x x x x 0 0 1 1 f clk /2 3 2.5 mhz x x x x 0 1 0 0 f clk /2 4 1.25 mhz x x x x 0 1 0 1 f clk /2 5 625 khz x x x x 0 1 1 0 f clk /2 6 313 khz x x x x 0 1 1 1 f clk /2 7 156 khz x x x x 1 0 0 0 f clk /2 8 78.1 khz x x x x 1 0 0 1 f clk /2 9 39.1 khz x x x x 1 0 1 0 f clk /2 10 19.5 khz x x x x 1 0 1 1 f clk /2 11 9.77 khz 0 x x x x 1 1 1 1 inttm02 note 2 0 0 0 0 x x x x f clk 20 mhz 0 0 0 1 x x x x f clk /2 10 mhz 0 0 1 0 x x x x f clk /2 2 5 mhz 0 0 1 1 x x x x f clk /2 3 2.5 mhz 0 1 0 0 x x x x f clk /2 4 1.25 mhz 0 1 0 1 x x x x f clk /2 5 625 khz 0 1 1 0 x x x x f clk /2 6 313 khz 0 1 1 1 x x x x f clk /2 7 156 khz 1 0 0 0 x x x x f clk /2 8 78.1 khz 1 0 0 1 x x x x f clk /2 9 39.1 khz 1 0 1 0 x x x x f clk /2 10 19.5 khz 1 0 1 1 x x x x f clk /2 11 9.77 khz 1 1 1 1 1 x x x x inttm02 note 2 other than above setting prohibited notes 1. when changing the clock selected for f clk (by changing the system clock control register (ckc) value), do so after having stopped (st0 = 000fh) the operation of the serial array unit (sau). when selecting inttm02 for the operation clock, al so stop the timer array unit taus (tt0 = 00ffh). 2. sau can be operated at a fixed division ratio of the subsystem clock, regardless of the f clk frequency (main system clock, subsystem clock), by setting the tis02 bit of the tis0 register of taus to 1, selecting f sub /4 for the input clock, and selecting inttm02 using the sps0 register. when changing f clk , however, sau and taus must be stopped as described in note 1 above. remark x: don?t care chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 505 here is an example of setting an iic transfer rate where mck = f clk = 20 mhz. f clk = 20 mhz iic transfer mode (desired transfer rate) operation clock (mck) sdr02[15:9] calculated transfer rate error from desired transfer rate 100 khz f clk 99 100 khz 0.0% 400 khz f clk 24 400 khz 0.0% 12.8 processing procedure in case of error the processing procedure to be followed if an error of each type occurs is described in figures 12-99 to 12-101. figure 12-99. processing procedure in case of parity error or overrun error software manipulation hardware status remark reads sdr0n register. bff = 0, and channel n is enabled to receive data. this is to prevent an overrun error if the next reception is completed during error processing. reads ssr0n register. error type is identified and the read value is used to clear error flag. writes sir0n register. error flag is cl eared. error can be cleared only during reading, by writing the value read from the ssr0n register to the sir0n register without modification. figure 12-100. processing procedure in case of framing error software manipulation hardware status remark reads sdr0n register. bff = 0, and channel n is enabled to receive data. this is to prevent an overrun error if the next reception is completed during error processing. reads ssr0n register. error type is identified and the read value is used to clear error flag. writes sir0n register. error flag is cl eared. error can be cleared only during reading, by writing the value read from the ssr0n register to the sir0n register without modification. sets st0n bit to 1. se0n = 0, and channel n stops operation. synchronization with other party of communication synchronization with the other party of communication is re-established and communication is resumed because it is considered that a framing error has occurred because the start bit has been shifted. sets ss0n bit to 1. se0n = 1, and channel n is enabled to operate. remark n: channel number (n = 0 to 3) chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 506 figure 12-101. processing procedure in case of parity error (ack error) in simplified i 2 c mode software manipulation hardware status remark reads sdr02 register. bff = 0, and channel 2 is enabled to receive data. this is to prevent an overrun error if the next reception is completed during error processing. reads ssr02 register. error type is identified and the read value is used to clear error flag. writes sir02 register. error flag is cl eared. error can be cleared only during reading, by writing the value read from the ssr02 register to the sir02 register without modification. sets st02 bit to 1. se02 = 0, and channel 2 stops operation. creates stop condition. creates start condition. slave is not ready for reception because ack is not returned. therefore, a stop condition is created, the bus is released, and communication is started again from the start condition. or, a restart condition is generated and transmission can be redone from address transmission. sets ss02 bit to 1. se02 = 1, and channel 2 is enabled to operate. chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 507 12.9 relationship between re gister settings and pins tables 12-5 to 12-8 show the relationship between register settings and pins for each channel of the serial array unit. table 12-5. relationship between register settings and pins (channel 0: csi00, uart0 transmission) pin function se 00 note 1 md 002 md0 01 soe 00 so0 0 cko 00 txe 00 rxe 00 pm 75 p75 pm 74 note 2 p74 note 2 pm 73 p73 operation mode sck00/ kr5/p75 si00/ rxd0/kr4/ p74 note 2 so00/ txd0/kr3/ p73 0 0 kr4/p74 0 0 1 0 1 1 0 0 note 3 note 3 note 3 note 3 note 3 note 3 operation stop mode kr5/p75 kr4/p74/ rxd0 kr3/p73 0 1 1 0 1 1 1 note 3 note 3 slave csi00 reception sck00 (input) si00 kr3/p73 1 0/1 note 4 1 1 0 1 note 3 note 3 0 1 slave csi00 transmission sck00 (input) kr4/p74 so00 1 0/1 note 4 1 1 1 1 1 0 1 slave csi00 transmission /reception sck00 (input) si00 so00 0 1 0/1 note 4 0 1 0 1 1 note 3 note 3 master csi00 reception sck00 (output) si00 kr3/p73 1 0/1 note 4 0/1 note 4 1 0 0 1 note 3 note 3 0 1 master csi00 transmission sck00 (output) kr4/p74 so00 0 0 1 0/1 note 4 0/1 note 4 1 1 0 1 1 0 1 master csi00 transmission /reception sck00 (output) si00 so00 1 0 1 1 0/1 note 4 1 1 0 note 3 note 3 note 3 note 3 0 1 uart0 transmission note 5 kr5/p75 kr4/p74/ rxd0 txd0 notes 1. the se0 register is a read-only status register which is set using the ss0 and st0 registers. 2. when channel 1 is set to uart0 reception, this pin becomes an rxd0 function pin (refer to table 12-6 ). in this case, operation stop mode or uart0 transmission must be selected for channel 0. 3. this pin can be set as a port function pin. 4. this is 0 or 1, depending on the communicat ion operation. for details, refer to 12.3 (12) serial output register 0 (so0) . 5. when using uart0 transmission and reception in a pair, set channel 1 to uart0 reception (refer to table 12-6 ). remark x: don?t care chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 508 table 12-6. relationship between register settings and pins (channel 1: csi01, uart0 reception) pin function se 01 note 1 md 012 md0 11 soe 01 so 01 cko 01 txe 01 rxe 01 pm 72 p72 pm 71 p71 pm 70 p70 pm 74 note 2 p74 note 2 operation mode sck01 / kr2/ intp6/ p72 si01/ kr1/ intp5/ p71 so01/ kr0/ intp4/ p70 si00/rxd0/ kr4/p74 note 2 0 0 0 0 1 0 1 1 0 0 note 3 note 3 note 3 note 3 note 3 note 3 note 3 note 3 operation stop mode kr2/ intp6/ p72 kr1/ intp5/ p71 kr0/ intp4/ p70 kr4/p74 0 1 1 0 1 1 1 note 3 note 3 note 3 note 3 slave csi01 reception sck01 (input) si01 kr0/ intp4/ p70 si00/kr4/ p74 1 0/1 note 4 1 1 0 1 note 3 note 3 0 1 note 3 note 3 slave csi01 transmission sck01 (input) kr1/ intp5/ p71 so01 si00/kr4/ p74 1 0/1 note 4 1 1 1 1 1 0 1 note 3 note 3 slave csi01 transmission /reception sck01 (input) si01 so01 si00/kr4/ p74 0 1 0/1 note 4 0 1 0 1 1 note 3 note 3 note 3 note 3 master csi01 reception sck01 (output) si01 kr0/ intp4/ p70 si00/kr4/ p74 1 0/1 note 4 0/1 note 4 1 0 0 1 note 3 note 3 0 1 note 3 note 3 master csi01 transmission sck01 (output) kr1/ intp5/ p71 so01 si00/kr4/ p74 0 0 1 0/1 note 4 0/1 note 4 1 1 0 1 1 0 1 note 3 note 3 master csi01 transmission /reception sck01 (output) si01 so01 si00/kr4/ p74 1 0 1 0 1 1 0 1 note 3 note 3 note 3 note 3 note 3 note 3 1 uart0 reception notes 5, 6 kr2/ intp6/ p72 kr1/ intp5/ p71 kr0/ intp4/ p70 rxd0 notes 1. the se0 register is a read-only status register which is set using the ss0 and st0 registers. 2. when channel 1 is set to uart0 reception, this pin becomes an rxd0 function pin. in this case, set channel 0 to operation stop mode or uart0 transmission (refer to table 12-5 ). when channel 0 is set to csi00, this pin cannot be used as an rxd0 function pin. in this case, set channel 1 to operation stop mode or csi01. 3. this pin can be set as a port function pin. 4. this is 0 or 1, depending on the communication operation. for details, refer to 12.3 (12) serial output register 0 (so0) . 5. when using uart0 transmission and reception in a pair, set channel 0 to uart0 transmission (refer to table 12-5 ). 6. the smr00 register of channel 0 must also be se t during uart0 reception. for details, refer to 12.5.2 (1) register setting . remark x: don?t care chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 509 table 12-7. relationship between register settings a nd pins (channel 2: csi10, uart1 transmission, iic10) pin function se 02 note 1 md 022 md 021 soe 02 so 02 cko 02 txe 02 rxe 02 pm3 2 p32 pm 31 note 2 p31 note 2 pm 30 p30 operation mode sck10/ scl10/ intp2/p32 si10/sda10/ rxd1/intp1/ p31 note 2 so10/ txd1/p30 0 0 intp1/p31 0 1 rxd1/intp1/ p31 0 1 0 0 1 1 0 0 not e 3 note 3 note 3 note 3 note 3 note 3 operation stop mode intp2/p32 intp1/p31 p30 0 1 1 0 1 1 1 note 3 note 3 slave csi10 reception sck10 (input) si10 p30 1 0/1 note 4 1 1 0 1 note 3 note 3 0 1 slave csi10 transmission sck10 (input) intp1/p31 so10 1 0/1 note 4 1 1 1 1 1 0 1 slave csi10 transmission /reception sck10 (input) si10 so10 0 1 0/1 note 4 0 1 0 1 1 note 3 note 3 master csi10 reception sck10 (output) si10 p30 1 0/1 note 4 0/1 note 4 1 0 0 1 note 3 note 3 0 1 master csi10 transmission sck10 (output) intp1/p31 so10 0 0 1 0/1 note 4 0/1 note 4 1 1 0 1 1 0 1 master csi10 transmission /reception sck10 (output) si10 so10 1 0 1 1 0/1 note 4 1 1 0 not e 3 note 3 note 3 note 3 0 1 uart1 transmission note5 intp2/p32 rxd1/intp1/ p31 txd1 0 0 1 0 0 0 0/1 note 6 0/1 note 6 0 1 0 1 0 1 note 3 note 3 iic10 start condition scl10 sda10 p30 1 0/1 note 4 0/1 note 4 1 0 0 1 0 1 note 3 note 3 iic10 address field transmission scl10 sda10 p30 1 0/1 note 4 0/1 note 4 1 0 0 1 0 1 note 3 note 3 iic10 data transmission scl10 sda10 p30 1 1 0/1 note 4 0/1 note 4 0 1 0 1 0 1 note 3 note 3 iic10 data reception scl10 sda10 p30 0 0 1 0 0 1 0 0 0/1 note 7 0/1 note 7 0 1 0 1 0 1 note 3 note 3 iic10 stop condition scl10 sda10 p30 notes 1. the se0 register is a read-only status register which is set using the ss0 and st0 registers. 2. when channel 3 is set to uart1 reception, this pin becomes an rxd1 function pin (refer to table 12-8 ). in this case, operation stop mode or uart1 transmission must be selected for channel 2. 3. this pin can be set as a port function pin. 4. this is 0 or 1, depending on the communicat ion operation. for details, refer to 12.3 (12) serial output register 0 (so0) . 5. when using uart1 transmission and reception in a pair, set channel 3 to uart1 reception (refer to table 12-8 ). 6. set the cko02 bit to 1 before a start condition is genera ted. clear the so02 bit from 1 to 0 when the start condition is generated. 7. set the cko02 bit to 1 before a stop condition is gener ated. clear the so02 bit from 0 to 1 when the stop condition is generated. remark x: don?t care chapter 12 serial array unit preliminary user?s manual u19291ej1v0ud 510 table 12-8. relationship between register se ttings and pins (channel 3: uart1 reception) pin function se03 note 1 md032 md031 txe03 rxe03 pm31 note 2 p31 note 2 operation mode si10/sda10/rxd1/intp1/p31 note 2 0 0 1 0 0 note 3 note 3 operation stop mode si10/sda10/intp1/p31 note 2 1 0 1 0 1 1 uart1 reception notes 4, 5 rxd1 notes 1. the se0 register is a read-only status register which is set using the ss0 and st0 registers. 2. when channel 3 is set to uart1 reception, this pin becomes an rxd1 function pin. in this case, set channel 2 to operation stop mode or uart1 transmission (refer to table 12-7 ). when channel 2 is set to csi10 or iic10, this pin cannot be used as an rxd1 function pin. in this case, set channel 3 to operation stop mode. 3. this pin can be set as a port function pin. 4. when using uart1 transmission and reception in a pair, set channel 2 to uart1 transmission (refer to table 12-7 ). 5. the smr02 register of channel 2 must also be set during uart1 reception. for details, refer to 12.5.2 (1) register setting . remark x: don?t care preliminary user?s manual u19291ej1v0ud 511 chapter 13 serial interface iica remark 44-pin products of the 78k0r/kc3-l are not provided with serial interface iica. 13.1 functions of serial interface iica serial interface iica has the following three modes. (1) operation stop mode this mode is used when serial transfers are not performed. it can therefore be used to reduce power consumption. (2) i 2 c bus mode (multimaster supported) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock (scl0) line and a serial data bus (sda0) line. this mode complies with the i 2 c bus format and the master device can generated ?start condition?, ?address?, ?transfer direction specification?, ?dat a?, and ?stop condition? data to the slave device, via the serial data bus. the slave device automatically detects these received status and data by har dware. this function can simplify the part of application prog ram that controls the i 2 c bus. since the scl0 and sda0 pins are used for open drain out puts, iica requires pull-up resistors for the serial clock line and the serial data bus line. (3) wakeup mode the stop mode can be released by generating an interr upt request signal (intiica) when an extension code from the master device or a local address has been received while in stop mode. this can be set by using the wup bit of iica contro l register 1 (iicctl1). figure 13-1 shows a block diagram of serial interface iica. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 512 figure 13-1. block diagram of serial interface iica iice dq dfc sda0/ p61 scl0/ p60 intiica iicctl0.stt, spt iics.msts, exc, coi iics.msts, exc, coi f clk lrel wrel spie wtim acke stt spt msts ald exc coi trc ackd std spd stcf iicbsy stcen iicrsv wup cld dad dfc smc pm60 internal bus iica status register (iics) iica control register 0 (iicctl0) slave address register (sva) noise eliminator match signal match signal iica shift register (iica) so latch set clear iicwl trc dfc data hold time correction circuit start condition generator stop condition generator ack generator wakeup controller n-ch open- drain output pm61 noise eliminator bus status detector ack detector stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller start condition detector internal bus iica flag register (iicf) iica control register 1 (iicctl1) n-ch open- drain output output latch (p60) output latch (p61) wup sub-circuit for standby filter filter output control iica shift register (iica) counter iica low-level width setting register (iicwl) iica high-level width setting register (iicwh) chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 513 figure 13-2 shows a serial bus configuration example. figure 13-2. serial bus c onfiguration example using i 2 c bus master cpu1 slave cpu1 address 0 sda0 scl0 serial data bus serial clock + v dd + v dd sda0 scl0 sda0 scl0 sda0 scl0 sda0 scl0 master cpu2 slave cpu2 address 1 slave cpu3 address 2 slave ic address 3 slave ic address n chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 514 13.2 configuration of serial interface iica serial interface iica includes the following hardware. table 13-1. configuration of serial interface iica item configuration registers iica shift register (iica) slave address register (sva) control registers peripheral enable register 0 (per0) iica control register 0 (iicctl0) iica status register (iics) iica flag register (iicf) iica control register 1 (iicctl1) iica low-level width setting register (iicwl) iica high-level width setting register (iicwh) port mode register 6 (pm6) port register 6 (p6) (1) iica shift register (iica) iica is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial clock. iica can be used for both transmission and reception. the actual transmit and receive operations can be contro lled by writing and reading operations to iica. cancel the wait state and start data transfer by writing data to iica during the wait period. iica can be set by an 8-bit memory manipulation instruction. reset signal generation clears iica to 00h. figure 13-3. format of iica shift register (iica) symbol iica address: fff50h after reset: 00h r/w 76543210 cautions 1. do not write data to iica during data transfer. 2. write or read iica only during the wait period. accessing iica in a communication state other than during the wait period is prohibit ed. when the device serves as the master, however, iica can be written only once after the communication trigger bit (stt) is set to 1. (2) slave address register (sva) this register stores seven bits of local addresse s {a6, a5, a4, a3, a2, a1, a0} when in slave mode. sva can be set by an 8-bit memory manipulation instruction. however, rewriting to this register is prohibited wh ile std = 1 (while the start condition is detected). reset signal generation clears sva to 00h. figure 13-4. format of slave address register (sva) symbol sva address: f0234h after reset: 00h r/w 76543210 0 note a0 a1 a2 a3 a4 a5 a6 note bit 0 is fixed to 0. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 515 (3) so latch the so latch is used to retain the sda0 pin?s output level. (4) wakeup controller this circuit generates an interrupt request (intiica) w hen the address received by this register matches the address value set to the slave address register (sva) or when an extension code is received. (5) serial clock counter this counter counts the serial clocks that are output or input during transmi t/receive operations and is used to verify that 8-bit data was transmitted or received. (6) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiica). an i 2 c interrupt request is generated by the following two triggers. ? falling edge of eighth or ninth clock of the serial clock (set by wtim bit) ? interrupt request generated when a stop co ndition is detected (set by spie bit) remark wtim bit: bit 3 of iica control register 0 (iicctl0) spie bit: bit 4 of iica control register 0 (iicctl0) (7) serial clock controller in master mode, this circuit generates the clock output via the scl0 pin from a sampling clock. (8) serial clock wait controller this circuit controls the wait timing. (9) ack generator, stop condition detector, start condition detector, and ack detector these circuits generate and detect each status. (10) data hold time correction circuit this circuit generates the hold time for data corre sponding to the falling edge of the serial clock. (11) start condition generator this circuit generates a start condition when the stt bit is set to 1. however, in the communication reservation disabled stat us (iicrsv bit = 1), when the bus is not released (iicbsy bit = 1), start condition requests are ignored and the stcf bit is set to 1. (12) stop condition generator this circuit generates a stop condition when the spt bit is set to 1. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 516 (13) bus status detector this circuit detects whether or not the bus is releas ed by detecting start conditions and stop conditions. however, as the bus status cannot be detected immediately following operation, the initial status is set by the stcen bit. remark stt bit: bit 1 of iica cont rol register 0 (iicctl0) spt bit: bit 0 of iica control register 0 (iicctl0) iicrsv bit: bit 0 of iica flag register (iicf) iicbsy bit: bit 6 of iica flag register (iicf) stcf bit: bit 7 of iica flag register (iicf) stcen bit: bit 1 of iica flag register (iicf) chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 517 13.3 registers controlling serial interface iica serial interface iica is controlled by the following eight registers. ? peripheral enable register 0 (per0) ? iica control register 0 (iicctl0) ? iica flag register (iicf) ? iica status register (iics) ? iica control register 1 (iicctl1) ? iica low-level width setting register (iicwl) ? iica high-level width setting register (iicwh) ? port mode register 6 (pm6) ? port register 6 (p6) (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripheral hardware macro. clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. when serial interface iica is used, be sure to set bit 4 (iicaen) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 13-5. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> 6 <5> <4> 3 <2> 1 0 per0 rtcen 0 adcen iicaen 0 sau0en 0 0 iicaen control of serial interface iica input clock supply 0 stops supply of input clock. ? sfr used by serial interface iica cannot be written. ? serial interface iica is in the reset status. 1 supplies input clock. ? sfr used by serial interface iica can be read/written. cautions 1. when setting serial interf ace iica, be sure to set iicaen to 1 first. if iicaen = 0, writing to a control register of serial interface iica is ignore d, and, even if the register is read, only the default value is read. 2. be sure to clear bits 0, 1, 3, and 6 of the per0 register to 0. (2) iica control register 0 (iicctl0) this register is used to enable/stop i 2 c operations, set wait timing, and set other i 2 c operations. iicctl0 can be set by a 1-bit or 8-bit memory manipula tion instruction. however, set the spie, wtim, and acke bits while iice bit = 0 or during the wait period. these bits can be set at the same time when the iice bit is set from ?0? to ?1?. reset signal generation clea rs this register to 00h. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 518 figure 13-6. format of iica cont rol register 0 (iicctl0) (1/4) address: f0230h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> iicctl0 iice lrel wrel spie wtim acke stt spt iice i 2 c operation enable 0 stop operation. reset the iica status register (iics) note 1 . stop internal operation. 1 enable operation. be sure to set this bit (1) while the scl0 and sda0 lines are at high level. condition for clearing (iice = 0) condition for setting (iice = 1) ? cleared by instruction ? reset ? set by instruction lrel note 2 exit from communications 0 normal operation 1 this exits from the current communications and sets standby mode. this setting is automatically cleared to 0 after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl0 and sda0 lines are set to high impedance. the following flags of iica control register 0 (iicctl0) and iica status register (iics) are cleared to 0. ? stt ? spt ? msts ? exc ? coi ? trc ? ackd ? std the standby mode following exit from communications rema ins in effect until the following communications entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code rece ption occurs after the start condition. condition for clearing (lrel = 0) condition for setting (lrel = 1) ? automatically cleared after execution ? reset ? set by instruction wrel note 2 wait cancellation 0 do not cancel wait 1 cancel wait. this setting is automatic ally cleared after wait is canceled. when wrel is set (wait canceled) during the wait period at the ninth clock pulse in t he transmission status (trc = 1), the sda0 line goes into the high impedance state (trc = 0). condition for clearing (wrel = 0) condition for setting (wrel = 1) ? automatically cleared after execution ? reset ? set by instruction notes 1. the iics register, the stcf and iicbsy bits of the iicf register, and the cld and dad bits of the iicctl1 register are reset. 2. the signal of this bit is invalid while iice0 is 0. caution the start condition is detected immediately after i 2 c is enabled to operate (iice = 1) while the scl0 line is at high level and the sda0 line is at low level. immediately after enabling i 2 c to operate (iice = 1), set lrel (1) by using a 1-bit memory manipulation instruction. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 519 figure 13-6. format of iica cont rol register 0 (iicctl0) (2/4) spie note 1 enable/disable generation of interrupt request when stop condition is detected 0 disable 1 enable condition for clearing (spie = 0) condition for setting (spie = 1) ? cleared by instruction ? reset ? set by instruction wtim note 1 control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, cloc k output is set to low level and wait is set. slave mode: after input of eight clo cks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and wait is set. slave mode: after input of nine clo cks, the clock is set to low level and wait is set for master device. an interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit. the setting of this bit is valid when the address tr ansfer is completed. when in master mode, a wait is inserted at the falling edge of the ninth clock during address tr ansfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ack) is issued. however, when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtim = 0) condition for setting (wtim = 1) ? cleared by instruction ? reset ? set by instruction acke notes 1, 2 acknowledgment control 0 disable acknowledgment. 1 enable acknowledgment. during t he ninth clock period, the sda0 line is set to low level. condition for clearing (acke = 0) condition for setting (acke = 1) ? cleared by instruction ? reset ? set by instruction notes 1. the signal of this bit is invalid while iice0 is 0. set this bit during that period. 2. the set value is invalid during address transfer and if the code is not an extension code. when the device serves as a slave and the addresses match, an acknowledgment is generated regardless of the set value. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 520 figure 13-6. format of iica cont rol register 0 (iicctl0) (3/4) stt note start condition trigger 0 do not generate a start condition. 1 when bus is released (in stop mode): generate a start condition (for starting as master). when the scl0 line is high level, the sda0 line is changed from high level to low level and then the st art condition is generated. next, after the rated amount of time has elapsed, scl0 is changed to low level (wait state). when a third party is communicating: ? when communication reservation function is enabled (iicrsv = 0) functions as the start condition reservation flag. when set to 1, automatically generates a start condition after the bus is released. ? when communication reservation function is disabled (iicrsv = 1) stcf is set to 1 and information that is set (1) to stt is cleared. no start condition is generated. in the wait state (when master device): generates a restart condition after releasing the wait. cautions concerning set timing ? for master reception: cannot be set to 1 during transfer. can be set to 1 only in the waiting period when acke has been cleared to 0 and slave ha s been notified of final reception. ? for master transmission: a start condition cannot be generated normally during the acknowledge period. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as spt. ? setting stt to 1 and then setting it again before it is cleared to 0 is prohibited. condition for clearing (stt = 0) condition for setting (stt = 1) ? cleared by setting stt to 1 while communication reservation is prohibited. ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? cleared by lrel = 1 (exit from communications) ? when iice = 0 (operation stop) ? reset ? set by instruction note the signal of this bit is invalid while iice0 is 0. remarks 1. bit 1 (stt) becomes 0 when it is read after data setting. 2. iicrsv: bit 0 of iic flag register (iicf) stcf: bit 7 of iic flag register (iicf) chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 521 figure 13-6. format of iica cont rol register 0 (iicctl0) (4/4) spt stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (terminati on of master device?s transfer). after the sda0 line goes to low level, either set the scl0 line to high level or wait until it goes to high level. next, after the rated amount of time has elap sed, the sda0 line changes from low level to high level and a stop condition is generated. cautions concerning set timing ? for master reception: cannot be set to 1 during transfer. can be set to 1 only in the waiting period when acke has been cleared to 0 and slave has been notified of final reception. ? for master transmission: a st op condition cannot be generated normally during the acknowledge period. therefore, set it during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as stt. ? spt can be set to 1 only when in master mode note . ? when wtim has been cleared to 0, if spt is set to 1 duri ng the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level peri od of the ninth clock. wtim should be changed from 0 to 1 during the wait period following the output of eight clocks, and spt should be set to 1 during the wait period that follows the output of the ninth clock. ? setting spt to 1 and then setting it again before it is cleared to 0 is prohibited. condition for clearing (spt = 0) condition for setting (spt = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? cleared by lrel = 1 (exit from communications) ? when iice = 0 (operation stop) ? reset ? set by instruction note set spt to 1 only in master mode. however, spt must be set to 1 and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. caution when bit 3 (trc) of the iica status register (iics) is set to 1, wrel is set to 1 during the ninth clock and wait is canceled, after which trc is cleared and the sda0 line is set to high impedance. remark bit 0 (spt) becomes 0 when it is read after data setting. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 522 (3) iica status register (iics) this register indicates the status of i 2 c. iics is read by a 1-bit or 8-bit memory manipulation in struction only when stt = 1 and during the wait period. reset signal generation clea rs this register to 00h. caution reading the iica status register (iics) while wup of iica control register 1 (iicctl1) is set to 1 is prohibited. when wup is changed from 0 to 1, regardless of the intiica interrupt request, the change in status is not reflected until the next start cond ition or stop condition is detected. to use the wakeup mode, therefore, enable (spie = 1) the interrupt generated by detecting a stop condition and read the iics re gister after the interr upt has been detected. figure 13-7. format of iica status register (iics) (1/3) address: fff51h after reset: 00h r symbol <7> <6> <5> <4> <3> <2> <1> <0> iics msts ald exc coi trc ackd std spd msts master status check flag 0 slave device status or communication standby status 1 master device communication status condition for clearing (msts = 0) condition for setting (msts = 1) ? when a stop condition is detected ? when ald = 1 (arbitration loss) ? cleared by lrel = 1 (exit from communications) ? when iice changes from 1 to 0 (operation stop) ? reset ? when a start condition is generated ald detection of arbitration loss 0 this status means either that there was no arbitr ation or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. msts is cleared. condition for clearing (ald = 0) condition for setting (ald = 1) ? automatically cleared after iics is read note ? when iice changes from 1 to 0 (operation stop) ? reset ? when the arbitration result is a ?loss?. exc detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (exc = 0) condition for setting (exc = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel = 1 (exit from communications) ? when iice changes from 1 to 0 (operation stop) ? reset ? when the higher four bits of the received address data is either ?0000? or ?1111? (set at the rising edge of the eighth clock). note this register is also cleared when a 1-bit memo ry manipulation instruction is executed for bits other than iics. therefore, when using the ald bi t, read the data of this bit before the data of the other bits. remark lrel: bit 6 of iica control register 0 (iicctl0) iice: bit 7 of iica control register 0 (iicctl0) chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 523 figure 13-7. format of iica status register (iics) (2/3) coi detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coi = 0) condition for setting (coi = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel = 1 (exit from communications) ? when iice changes from 1 to 0 (operation stop) ? reset ? when the received address matches the local address (slave address register (sva)) (set at the rising edge of the eighth clock). trc detection of transmit/receive status 0 receive status (other than transmit status). the sda0 line is set for high impedance. 1 transmit status. the value in the so0 latch is enabled for output to the sda0 line (valid starting at the falling edge of the first byte?s ninth clock). condition for clearing (trc = 0) condition for setting (trc = 1) chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 524 figure 13-7. format of iica status register (iics) (3/3) ackd detection of acknowledge (ack) 0 acknowledge was not detected. 1 acknowledge was detected. condition for clearing (ackd = 0) condition for setting (ackd = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by lrel = 1 (exit from communications) ? when iice changes from 1 to 0 (operation stop) ? reset ? after the sda0 line is set to low level at the rising edge of scl0?s ninth clock std detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect. condition for clearing (std = 0) condition for setting (std = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by lrel = 1 (exit from communications) ? when iice changes from 1 to 0 (operation stop) ? reset ? when a start condition is detected spd detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device ?s communication is terminated and the bus is released. condition for clearing (spd = 0) condition for setting (spd = 1) ? at the rising edge of the address transfer byte?s first clock following setting of th is bit and detection of a start condition ? when iice changes from 1 to 0 (operation stop) ? reset ? when a stop condition is detected remark lrel: bit 6 of iica control register 0 (iicctl0) iice: bit 7 of iica control register 0 (iicctl0) (4) iica flag register (iicf) this register sets the operation mode of i 2 c and indicates the status of the i 2 c bus. iicf can be set by a 1-bit or 8-bit memory manipulati on instruction. however, the stcf and iicbsy bits are read-only. the iicrsv bit can be used to enable/disabl e the communication reservation function. stcen can be used to set the initial value of the iicbsy bit. iicrsv and stcen can be written only when the operation of i 2 c is disabled (bit 7 (iice) of iica control register 0 (iicctl0) = 0). when operation is enabled, the iicf register can be read. reset signal generation clea rs this register to 00h. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 525 figure 13-8. format of iica flag register (iicf) <7> stcf condition for clearing (stcf = 0) ? cleared by stt = 1 ? when iice = 0 (operation stop) ? reset condition for setting (stcf = 1) ? generating start condition unsuccessful and stt cleared to 0 when communication reservation is disabled (iicrsv = 1). stcf 0 1 generate start condition start condition generation unsuccessful: clear stt flag stt clear flag iicf symbol <6> iicbsy 5 0 4 0 3 0 2 0 <1> stcen <0> iicrsv address: fff52h after reset: 00h r/w note condition for clearing (iicbsy = 0) ? detection of stop condition ? when iice = 0 (operation stop) ? reset condition for setting (iicbsy = 1) ? detection of start condition ? setting of iice when stcen = 0 iicbsy 0 1 bus release status (communication initial status when stcen = 1) bus communication status (communication initial status when stcen = 0) i 2 c bus status flag condition for clearing (stcen = 0) ? cleared by instruction ? detection of start condition ? reset condition for setting (stcen = 1) ? set by instruction stcen 0 1 after operation is enabled (iice = 1), enable generation of a start condition upon detection of a stop condition. after operation is enabled (iice = 1), enable generation of a start condition without detecting a stop condition. initial start enable trigger condition for clearing (iicrsv = 0) ? cleared by instruction ? reset condition for setting (iicrsv = 1) ? set by instruction iicrsv 0 1 enable communication reservation disable communication reservation communication reservation function disable bit note bits 6 and 7 are read-only. cautions 1. write to stcen only when the operation is stopped (iice = 0). 2. as the bus release status (iicbsy = 0) is recognized regardless of the actual bus status when stcen = 1, when generating the first start condition (stt = 1), it is necessary to verify that no third party comm unications are in progress in order to prevent such communications from being destroyed. 3. write to iicrsv only when the operation is stopped (iice = 0). remark stt: bit 1 of iica cont rol register 0 (iicctl0) iice: bit 7 of iica control register 0 (iicctl0) chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 526 (5) iica control register 1 (iicctl1) this register is used to set the operation mode of i 2 c and detect the statuses of the scl0 and sda0 pins. iicctl1 can be set by a 1-bit or 8-bit memory manipulat ion instruction. however, the cld and dad bits are read-only. set iicctl1, except the wup bit, while bit 7 (iice) of iica control register 0 (iicctl0) is 0. reset signal generation clea rs this register to 00h. figure 13-9. format of iica cont rol register 1 (iicctl1) (1/2) address: f0231h after reset: 00h r/w note symbol 7 6 <5> <4> <3> <2> 1 0 iicctl1 wup 0 cld dad smc dfc 0 0 wup control of address match wakeup 0 stops operation of address match wakeup function in stop mode. 1 enables operation of address match wakeup function in stop mode. clear (0) wup after the address has matched or an extension code has been received. the subsequent communication can be entered by cleari ng (0) wup. (the wait must be released and transmit data must be written after wup has been cleared (0).) the interrupt timing when the address has matched or when an extension code has been received, while wup = 1, is identical to the interrupt timing when wup = 0. (a delay of the difference of sampling by the clock will occur.) furthermore, when wup = 1, a stop condition interr upt is not generated even if the spie bit is set to 1. when wup = 0 is set by a source other than an interrupt from serial interface iica, operation as the master device cannot be performed until the subsequent start co ndition or stop condition is detected. do not output a start condition by setting (1) the stt bit, without waiti ng for the detection of the subsequent start condition or stop condition. condition for clearing (w up = 0) condition for setting (wup = 1) ? cleared by instruction (after address match or extension code reception) ? set by instruction (when msts, exc, and coi are ?0?, and std also ?0? (communication not entered)) note note the status of iics must be checked and wup must be set during the period shown below. scl0 <1> <2> sda0 a6 a5 a4 a3 a2 a1 a0 the maximum time from reading iics to setting wup is the period from <1> to <2>. check the iics operation status and set wup during this period. r/w chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 527 figure 13-9. format of iica cont rol register 1 (iicctl1) (2/2) cld detection of scl0 pin level (valid only when iice = 1) 0 the scl0 pin was detected at low level. 1 the scl0 pin was detected at high level. condition for clearing (cld = 0) condition for setting (cld = 1) ? when the scl0 pin is at low level ? when iice = 0 (operation stop) ? reset ? when the scl0 pin is at high level dad detection of sda0 pin level (valid only when iice = 1) 0 the sda0 pin was detected at low level. 1 the sda0 pin was detected at high level. condition for clearing (dad = 0) condition for setting (dad = 1) ? when the sda0 pin is at low level ? when iice = 0 (operation stop) ? reset ? when the sda0 pin is at high level smc operation mode switching 0 operates in standard mode. 1 operates in fast mode. dfc digital filter operation control 0 digital filter off. 1 digital filter on. digital filter can be used only in fast mode. in fast mode, the transfer clock does not vary, rega rdless of the dfc bit being set (1) or cleared (0). the digital filter is used for noise elimination in fast mode. note bits 4 and 5 are read-only. remark iice: bit 7 of iica control register 0 (iicctl0) chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 528 (6) iica low-level width setting register (iicwl) this register is used to set the low- level width of the scl0 pin signal th at is output by serial interface iica being in master mode. iicwl can be set by an 8-bit memory manipulation instruction. set iicwl when bit 7 (iice) of iica control register 0 (iicctl0) is 0. reset signal generation sets this register to ffh. figure 13-10. format of iica low-level width setting register (iicwl) address: f0232h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 iicwl (7) iica high-level width setting register (iicwh) this register is used to set the high-level width of t he scl0 pin signal that is output by serial interface iica being in master mode. iicwh can be set by an 8-bit memory manipulation instruction. set iicwh when bit 7 (iice) of iica control register 0 (iicctl0) is 0. reset signal generation sets this register to ffh. figure 13-11. format of iica high-level width setting register (iicwh) address: f0233h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 iicwh chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 529 (8) port mode register 6 (pm6) this register sets the input/output of port 6 in 1-bit units. when using the p60/scl0 pin as clock i/o and the p61/ sda0 pin as serial data i/o, clear pm60 and pm61, and the output latches of p60 and p61 to 0. set iice (bit 7 of iica control register 0 (iicctl0)) to 1 before setting the output mo de because the p60/scl0 and p61/sda0 pins output a low level (fixed) when iice is 0. pm6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation se ts this register to ffh. figure 13-12. format of port mode register 6 (pm6) pm60 pm61 1 1 1 1 1 1 p6n pin i/o mode selection (n = 0, 1) output mode (output buffer on) input mode (output buffer off) pm6n 0 1 0 1 2 3 4 5 6 7 pm6 address: fff26h after reset: ffh r/w symbol chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 530 13.4 i 2 c bus mode functions 13.4.1 pin configuration the serial clock pin (scl0) and serial data bus pin (sda0) are configured as follows. (1) scl0....... this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. (2) sda0 ...... this pin is used fo r serial data input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are n-ch open-drai n outputs, an external pull-up resistor is required. figure 13-13. pin configuration diagram master device clock output (clock input) data output data input v ss v ss scl0 sda0 v dd v dd (clock output) clock input data output data input v ss v ss slave device scl0 sda0 chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 531 13.5 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. figure 13-14 shows the transfer timing for the ?start conditi on?, ?address?, ?data?, and ?st op condition? output via the i 2 c bus?s serial data bus. figure 13-14. i 2 c bus serial data transfer timing scl0 sda0 start condition address r/w ack data 1-7 8 9 1-8 ack data ack stop condition 9 1-8 9 the master device generates the start c ondition, slave address, and stop condition. the acknowledge (ack) can be generated by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scl0) is continuously output by the master device. howeve r, in the slave device, the scl0?s low level period can be extended and a wait can be inserted. 13.5.1 start conditions a start condition is met when the scl0 pin is at high level and the sda0 pin changes from high level to low level. the start conditions for the scl0 pin and sda0 pin are signal s that the master device gener ates to the slave device when starting a serial transfer. when the device is us ed as a slave, start conditions can be detected. figure 13-15. start conditions scl0 sda0 h a start condition is output when bit 1 (stt) of iica control register 0 (iicctl0) is set (1) after a stop condition has been detected (spd: bit 0 of the iica status register (iics) = 1). when a start condition is detected, bit 1 (std) of iics is set (1). chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 532 13.5.2 addresses the address is defined by the 7 bits of data that follow the start condition. an address is a 7-bit data segment that is output in order to select one of t he slave devices that are connected to the master device via the bus lines. therefore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware t hat detects the start condition and c hecks whether or not the 7-bit address data matches the data values stored in the slave address register (sva). if the address data matches the sva values, the slave device is selected and comm unicates with the master device until t he master device generates a start condition or stop condition. figure 13-16. address scl0 sda0 intiica 123456789 a6 a5 a4 a3 a2 a1 a0 r/w address note note intiica is not issued if data other than a local addre ss or extension code is received during slave device operation. addresses are output when a total of 8 bits consisting of the slave address and the tr ansfer direction described in 13.5.3 transfer di rection specification are written to the iica shift register (iica). the received addresses are written to iica. the slave address is assigned to the higher 7 bits of iica. 13.5.3 transfer di rection specification in addition to the 7-bit address data, the master device s ends 1 bit that specifies t he transfer direction. when this transfer direction specificati on bit has a value of ?0?, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of ?1?, it indicates that the master device is receiving data from a slave device. figure 13-17. transfer direction specification scl0 sda0 intiica 123456789 a6 a5 a4 a3 a2 a1 a0 r/w transfer direction specification note note intiica is not issued if data other than a local addre ss or extension code is received during slave device operation. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 533 13.5.4 acknowledge (ack) ack is used to check the status of serial data at the transmission and reception sides. the reception side returns ack each time it has received 8-bit data. the transmission side usually receives ack after transmitting 8-bit data. when ack is returned from the reception side, it is assumed that reception has been correctly performed and processi ng is continued. whether ack has been detected can be checked by using bit 2 (ack d) of the iica status register (iics). when the master receives the last dat a item, it does not return ack and instead generates a stop condition. if a slave does not return ack after receiving data, the ma ster outputs a stop condition or restart condition and stops transmission. if ack is not returned, the possible causes are as follows. <1> reception was not performed normally. <2> the final data item was received. <3> the reception side specified by the address does not exist. to generate ack, the reception side makes the sda0 line low at the ninth clock (indicating normal reception). automatic generation of ack is enabled by setting bit 2 (ac ke) of iica control register 0 (iicctl0) to 1. bit 3 (trc) of the iics register is set by t he data of the eighth bit that follows 7-bit address information. usually, set acke to 1 for reception (trc = 0). if a slave can receive no more data during reception (trc = 0) or does not require the next data item, then the slave must inform the master, by clearing acke to 0, that it will not receive any more data. when the master does not require the nex t data item during receptio n (trc = 0), it must clear acke to 0 so that ack is not generated. in this way, the master informs a slave at the transmission side that it does not require any more data (transmission will be stopped). figure 13-18. ack scl0 sda0 123456789 a6 a5 a4 a3 a2 a1 a0 r/w ack when the local address is received, ac k is automatically generated, regard less of the value of acke. when an address other than that of t he local address is received, ack is not generated (nack). when an extension code is received, ack is generated if acke is set to 1 in advance. how ack is generated when data is received differs as follows depending on the setting of the wait timing. ? when 8-clock wait state is selected (b it 3 (wtim) of iicctl0 register = 0): by setting acke to 1 before releasing the wait state, ack is generated at the falling e dge of the eighth clock of the scl0 pin. ? when 9-clock wait state is selected (b it 3 (wtim) of iicctl0 register = 1): ack is generated by setting acke to 1 in advance. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 534 13.5.5 stop condition when the scl0 pin is at high level, changing the sda0 pin from low level to high level generates a stop condition. a stop condition is a signal that the master device generates to the slave device when serial transfer has been completed. when the device is used as a slave, stop conditions can be detected. figure 13-19. stop condition scl0 sda0 h a stop condition is generated when bit 0 (spt) of iica contro l register 0 (iicctl0) is set to 1. when the stop condition is detected, bit 0 (spd) of t he iica status register (iics) is set to 1 and intiica is generated when bit 4 (spie) of iicctl0 is set to 1. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 535 13.5.6 wait the wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0 pin to low level notifi es the communication partner of the wait state. when wait state has been canceled for both the master and slave devices, the next data transfer can begin. figure 13-20. wait (1/2) (1) when master device has a nine-clock wait and slave device has an eight-clock wait (master transmits, slave receives, and acke = 1) master iica scl0 slave iica scl0 acke transfer lines scl0 sda0 6789 123 master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock iica data write (cancel wait) wait after output of eighth clock wait from slave wait from master ffh is written to iica or wrel is set to 1 678 9 123 d2 d1 d0 d7 d6 d5 ack h chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 536 figure 13-20. wait (2/2) (2) when master and slave devices both have a nine-clock wait (master transmits, slave receives, and acke = 1) master iica scl0 slave iica scl0 acke transfer lines scl0 sda0 h 6789 1 23 master and slave both wait after output of ninth clock wait from master and slave wait from slave iica data write (cancel wait) ffh is written to iica or wrel is set to 1 6789 123 d2 d1 d0 ack d7 d6 d5 generate according to previously set acke value remark acke: bit 2 of iica control register 0 (iicctl0) wrel: bit 5 of iica control register 0 (iicctl0) a wait may be automatically generat ed depending on the setting of bit 3 (wtim) of iica control register 0 (iicctl0). normally, the receiving side cancels the wait state when bit 5 (wrel) of iicctl0 is set to 1 or when ffh is written to the iica shift register (iica), and the transmitting side cancels the wait state when data is written to iica. the master device can also cancel the wait state via either of the following methods. ? by setting bit 1 (stt) of iicctl0 to 1 ? by setting bit 0 (spt) of iicctl0 to 1 chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 537 13.5.7 canceling wait the i 2 c usually cancels a wait stat e by the following processing. ? writing data to iica shift register (iica) ? setting bit 5 (wrel) of iica control register 0 (iicctl0) (canceling wait) ? setting bit 1 (stt) of iicctl0 regi ster (generating start condition) note ? setting bit 0 (spt) of iicctl0 regi ster (generating stop condition) note note master only when the above wait canceling pr ocessing is executed, the i 2 c cancels the wait state and communication is resumed. to cancel a wait state and transmit data (incl uding addresses), write the data to iica. to receive data after canceling a wait state, or to co mplete data transmission, set bit 5 (wrel) of iica control register 0 (iicctl0) to 1. to generate a restart condition after canceling a wait state, set bit 1 (stt) of iicctl0 to 1. to generate a stop condition after canceling a wa it state, set bit 0 ( spt) of iicctl0 to 1. execute the canceling processing only once for one wait state. if, for example, data is written to iica after canceling a wa it state by setting wrel to 1, an incorrect value may be output to sda0 because the timing for changing the sd a0 line conflicts with the timing for writing iica. in addition to the above, communication is stopped if iice is cleared to 0 when communication has been aborted, so that the wait st ate can be canceled. if the i 2 c bus has deadlocked due to noise, processing is sav ed from communication by setting bit 6 (lrel) of iicctl0, so that the wait state can be canceled. caution if a processing to cancel a wait state is ex ecuted when wup = 1, the wait state will not be canceled. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 538 13.5.8 interrupt request (intiica) generation timing and wait control the setting of bit 3 (wtim) of iica control register 0 (ii cctl0) determines the timing by which intiica is generated and the corresponding wait c ontrol, as shown in table 13-2. table 13-2. intiica generation timing and wait control during slave device operation during master device operation wtim address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiica signal and wait period occu rs at the falling edge of the ninth clock only when there is a match with the address set to the slave address register (sva). at this point, ack is generated regardless of the va lue set to iicctl0?s bit 2 (acke). for a slave device that has received an extension code, intiica occu rs at the falling edge of the eighth clock. however, if the address does not match after restar t, intiica is generated at the falling edge of the 9th clock, but wait does not occur. 2. if the received address does not match the contents of the slave address regi ster (sva) and extension code is not received, neither intiica nor a wait occurs. remark the numbers in the table indicate the number of t he serial clock?s clock signals. interrupt requests and wait control are both synchronized with t he falling edge of these clock signals. (1) during address transmission/reception ? slave device operation: interrupt and wait timi ng are determined depending on the conditions described in notes 1 and 2 above, regardless of the wtim bit. ? master device operation: interrupt and wait timing oc cur at the falling edge of the ninth clock regardless of the wtim bit. (2) during data reception ? master/slave device operation: interrupt and wait timing are determined according to the wtim bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing are determined according to the wtim bit. (4) wait cancellation method the four wait cancellation methods are as follows. ? writing data to iica shift register (iica) ? setting bit 5 (wrel) of iica control register 0 (iicctl0) (canceling wait) ? setting bit 1 (stt) of iicctl0 regi ster (generating start condition) note ? setting bit 0 (spt) of iicctl0 regi ster (generating stop condition) note note master only. when an 8-clock wait has been selected (wtim = 0) , the presence/absence of ack generation must be determined prior to wait cancellation. (5) stop condition detection intiica is generated when a stop condit ion is detected (only when spie = 1). chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 539 13.5.9 address match detection method in i 2 c bus mode, the master device can se lect a particular slave device by transmitting the corresponding slave address. address match can be detected automatical ly by hardware. an interrupt r equest (intiica) occurs when a local address has been set to the slave address register (sva) and when the address set to sva matches the slave address sent by the master device, or when an extension code has been received. 13.5.10 error detection in i 2 c bus mode, the status of the serial data bus (sda0) during data transmission is captured by the iica shift register (iica) of the transmitting device, so the iica data prior to trans mission can be compared with the transmitted iica data to enable detection of transmission errors. a transmission error is judged as having occurred when the compared data values do not match. 13.5.11 extension code (1) when the higher 4 bits of the receive address are ei ther ?0000? or ?1111?, the extension code reception flag (exc) is set to 1 for extension code reception and an inte rrupt request (intiica) is issued at the falling edge of the eighth clock. the local address stored in t he slave address register (sva) is not affected. (2) if ?11110 0? is set to sva by a 10-bit address transfer and ?11110 0? is transferred from the master device, the results are as follows. note that intiica occurs at the falling edge of the eighth clock. ? higher four bits of data match: exc = 1 ? seven bits of data match: coi = 1 remark exc: bit 5 of iica status register (iics) coi: bit 4 of iica status register (iics) (3) since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. if the extension code is received while a slave device is operating, then the slave device is participating in communication even if its address does not match. for example, after the extension code is received, if you do not wish to operate the target device as a slave device, set bit 6 (lrel) of the iica control register 0 (iicctl0) to 1 to set the standby mode for the next communication operation. table 13-3. bit definition s of major extension codes slave address r/w bit description 0 0 0 0 0 0 0 0 general call address 1 1 1 1 0 x x 0 10-bit slave addre ss specification (during address authentication) 1 1 1 1 0 x x 1 10-bit slave address specification (after address match, when read command is issued) remark see the i 2 c bus specifications issued by nxp semiconducto rs for details of extension codes other than those described above. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 540 13.5.12 arbitration when several master devices simultaneously generate a star t condition (when stt is set to 1 before std is set to 1), communication among the master devic es is performed as the number of clo cks are adjusted until the data differs. this kind of operation is called arbitration. when one of the master devices loses in arbitration, an arbitration loss flag (ald ) in the iica status register (iics) is set (1) via the timing by which the arbitration loss oc curred, and the scl0 and sda0 lines are both set to high impedance, which releases the bus. the arbitration loss is detected based on the timing of the next interrupt reques t (the eighth or ninth clock, when a stop condition is detected, et c.) and the ald = 1 setting that has been made by software. for details of interrupt request timing, see 13.5.8 interrupt request (intii ca) generation timing and wait control . remark std: bit 1 of iica status register (iics) stt: bit 1 of iica control register 0 (iicctl0) figure 13-21. arbitration timing example scl0 sda0 scl0 sda0 scl0 sda0 hi-z hi-z master 1 loses arbitration master 1 master 2 transfer lines chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 541 table 13-4. status during arbitrati on and interrupt request generation timing status during arbitration interrupt request generation timing during address transmission read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack transfer period after data transmission when restart condition is detected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected during data transf er when stop condition is generated (when spie = 1) note 2 when data is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to generate a restart condition when stop condition is generated (when spie = 1) note 2 when data is at low level while attempting to generate a stop condition when scl0 is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when wtim (bit 3 of iica control register 0 (iicct l0)) = 1, an interrupt request occurs at the falling edge of the ninth clock. when wtim = 0 and the extension code?s slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. when there is a chance that ar bitration will occur, set spie = 1 for master device operation. remark spie: bit 4 of iica c ontrol register 0 (iicctl0) chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 542 13.5.13 wakeup function the i 2 c bus slave function is a function that generates an interrupt request si gnal (intiica) when a local address and extension code have been received. this function makes processing more efficient by prev enting unnecessary intiica signal from occurring when addresses do not match. when a start condition is detected, wake up standby mode is set. this wakeup standby mode is in effect while addresses are transmitted due to the possibility that an ar bitration loss may change the master device (which has generated a start condition) to a slave device. however, when a stop condition is detected, bit 4 (spie) of iica control register 0 (iicctl0) is set regardless of the wakeup function, and this determines whether interrupt requests are enabled or disabled. to use the wakeup function in the stop mode, set wup to 1. addresses can be received regardless of the operation clock. an interrupt request signal (intiica) is also generated when a local address and extension code have been received. operation returns to normal operation by using an instruction to clear (0) the wup bit after this interrupt has been generated. the flows of when setting the wup bit and clearing (0) the wup bit upon an address match are shown below. figure 13-22. flow when setting wup = 1 waits for 3 clocks. yes no start wup = 1 wait stop instruction execution msts = std = exc = coi =0? chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 543 figure 13-23. flow when setting wup = 0 upon ad dress match (including extension code reception) waits for 5 clocks. a wait of 5 clocks is required from release of stop mode to setting wup = 0. executes processing corresponding to the operation to be executed after checking the operation state of serial interface iica. stop mode state no yes wup = 0 wait reading iics intiica = 1? use the following flows to perform the processing to re lease the stop mode other than by an interrupt request (intiica) generated from serial interface iica. ? master device operation: flow shown in figure 13-24 ? slave device operation: flow shown in figure 13-23 or figure 13-25 when operating the 78k0r/kx3-l as a slav e device, basically, use the flow show n in figure 13-23. in this flow, however, extra time to keep communication waiting is requi red, because setting wup to 0 takes processing time. to shorten the time for which communication is kept wait ing, use the flow shown in figure 13-25 to operate the 78k0r/kx3-l. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 544 figure 13-24. when operating as master device after releasing stop mode other than by intiica executes processing corresponding to the operation to be executed after checking the operation state of serial interface iica. no yes releases stop mode by an interrupt other than intiica. generates a stop condition or selects as a slave device. start wup = 1 spie = 1 releasing stop mode stop instruction wup = 0 reading iics intiica = 1? stop mode state figure 13-25. when operating as sla ve device after releasing stop mode other than by intiica (when not required to operate as master device) executes processing corresponding to the operation to be executed after checking the operation state of serial interface iica. no yes releases stop mode by an interrupt other than intiica. start wup = 1 spie = 1 releasing stop mode reading iics intiica = 1? stop instruction stop mode state selects as a slave device. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 545 13.5.14 communication reservation (1) when communication reservation func tion is enabled (bit 0 (iicrsv) of iica flag register (iicf) = 0) to start master device communications when not curr ently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. there are two modes under which the bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released by setting bit 6 (lrel) of iica control r egister 0 (iicctl0) to 1 and saving communication). if bit 1 (stt) of iicctl0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition is automatically generated and wait state is set. if an address is written to the iica shift register (iica) after bit 4 (spie) of iicctl0 was set to 1, and it was detected by generation of an interrupt request signal (intiica) that t he bus was released (detection of the stop condition), then the device automatically starts communic ation as the master. data written to iica before the stop condition is det ected is invalid. when stt has been set to 1, the operation mode (as star t condition or as communication reservation) is determined according to the bus status. ? if the bus has been released .........................................a start c ondition is generated ? if the bus has not been released (stand by mode) .........communica tion reservation check whether the communication reservat ion operates or not by using msts (bit 7 of the iica status register (iics)) after stt is set to 1 and the wait time elapses. use software to secure the wait time calculated by the following expression. wait time from setting stt = 1 to checking the msts flag: (iicwl setting value + iicwh setting value + 4 (clocks)) f clk + t f 2 remark iicwl: iica low-level width setting register iicwh: iica high-level width setting register t f : sda0 and scl0 signal falling times (see chapter 28 electrical specifications (target) ) f clk : cpu/peripheral hardware clock frequency chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 546 figure 13-26 shows the communication reservation timing. figure 13-26. communication reservation timing 2 13456 2 1 3456 789 scl0 sda0 program processing hardware processing write to iica set spd and intiica stt = 1 communi- cation reservation set std generate by master device with bus mastership remark iica: iica shift register stt: bit 1 of iica control register 0 (iicctl0) std: bit 1 of iica status register (iics) spd: bit 0 of iica status register (iics) communication reservations are accepted via the timing shown in figure 13-27. after bit 1 (std) of the iica status register (iics) is set to 1, a communicatio n reservation can be made by setting bit 1 (stt) of iica control register 0 (iicctl0) to 1 before a stop condition is detected. figure 13-27. timing for accepting communication reservations scl0 sda0 std spd standby mode (communication can be reserved by setting stt to 1 during this period.) figure 13-28 shows the communication reservation protocol. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 547 figure 13-28. communication reservation protocol di set1 stt define communication reservation wait msts = 0? (communication reservation) note 2 yes no (generate start condition) cancel communication reservation mov iica, # h ei sets stt flag (communication reservation) defines that communication reservation is in effect (defines and sets user flag to any part of ram) secures wait time note 1 by software. confirmation of communication reservation clear user flag iica write operation notes 1. the wait time is calculated as follows. (iicwl setting value + iicwh setting value + 4 (clocks)) f clk + t f 2 2. the communication reservation oper ation executes a write to the iica shift register (iica) when a stop condition interrupt request occurs. remark stt: bit 1 of iica control register 0 (iicctl0) msts: bit 7 of iica status register (iics) iica: iica shift register iicwl: iica low-level width setting register iicwh: iica high-level width setting register t f : sda0 and scl0 signal falling times (see chapter 28 electrical specifications (target) ) f clk : cpu/peripheral hardware clock frequency chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 548 (2) when communication reservation function is disabled (bit 0 (iicrsv) of iica flag register (iicf) = 1) when bit 1 (stt) of iica control regist er 0 (iicctl0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. the following two statuses are included in the st atus where bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released by setting bit 6 (lrel) of iicctl0 to 1 and saving communication) to confirm whether the start condition was generated or r equest was rejected, check stcf (bit 7 of iicf). it takes up to 5 clocks until stcf is set to 1 after setting stt = 1. therefore, secure the time by software. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 549 13.5.15 cautions (1) when stcen (bit 1 of iica flag register (iicf)) = 0 immediately after i 2 c operation is enabled (iice = 1), the bus communication status (iicbsy (bit 6 of iicf) = 1) is recognized regardless of the act ual bus status. when changing from a mode in which no stop condition has been detected to a master device communication mode, fi rst generate a stop condition to release the bus, then perform master device communication. when using multiple masters, it is not possible to per form master device communication when the bus has not been released (when a stop condition has not been detected). use the following sequence for generating a stop condition. <1> set iica control register 1 (iicctl1). <2> set bit 7 (iice) of iica control register 0 (iicctl0) to 1. <3> set bit 0 (spt) of iicctl0 to 1. (2) when stcen = 1 immediately after i 2 c operation is enabled (iice = 1), the bus released status (iicbsy = 0) is recognized regardless of the actual bus status. to generate the first start condition (s tt (bit 1 of iica control register 0 (iicctl0)) = 1), it is necessary to confirm that t he bus has been released, so as to not disturb other communications. (3) if other i 2 c communications are already in progress if i 2 c operation is enabled and the device participates in communication already in progress when the sda0 pin is low and the scl0 pin is high, the macro of i 2 c recognizes that the sda0 pin has gone low (detects a start condition). if the value on the bus at this time ca n be recognized as an extension code, ack is returned, but this interferes with other i 2 c communications. to avoid this, start i 2 c in the following sequence. <1> clear bit 4 (spie) of iicctl0 to 0 to disable gener ation of an interrupt request signal (intiica) when the stop condition is detected. <2> set bit 7 (iice) of iicctl0 to 1 to enable the operation of i 2 c. <3> wait for detection of the start condition. <4> set bit 6 (lrel) of iicctl0 to 1 before ack is retu rned (4 to 80 clocks after setting iice to 1), to forcibly disable detection. (4) setting stt and spt (bits 1 and 0 of iicctl0) again afte r they are set and before they are cleared to 0 is prohibited. (5) when transmission is reserved, set spie (bit 4 of iictl0) to 1 so that an interrupt request is generated when the stop condition is detected. transfer is started when communication data is written to iica after the interrupt request is generated. unless the interrupt is generat ed when the stop condition is detected, the device stops in the wait state because the interrupt request is not generated when communicati on is started. however, it is not necessary to set spie to 1 when msts (bit 7 of iics) is detected by software. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 550 13.5.16 communication operations the following shows three operatio n procedures with the flowchart. (1) master operation in single master system the flowchart when using the 78k0r/kx3-l as the mast er in a single master system is shown below. this flowchart is broadly divided into the initial setti ngs and communication processing. execute the initial settings at startup. if communication with the slave is required, prepare the communication and then execute communication processing. (2) master operation in multimaster system in the i 2 c bus multimaster system, whethe r the bus is released or us ed cannot be ju dged by the i 2 c bus specifications when the bus takes part in a communication. here, when data and clock are at a high level for a certain period (1 frame), the 78k0r/kx3-l takes par t in a communication with bus released state. this flowchart is broadly divided into the initial setti ngs, communication waiting, and communication processing. the processing when the 78k0r/kx3-l lo oses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. execute the initial settings at startup to take part in a communication. then, wait for the communication request as the master or wait fo r the specification as the slave. the actual communication is performed in the communication processing, and it supports the transmission/reception with the slave and the arbitration with other masters. (3) slave operation an example of when the 78k0r/kx3-l is used as the i 2 c bus slave is shown below. when used as the slave, operation is st arted by an interrupt. execute the in itial settings at startup, then wait for the intiica interrupt occurrence (communication waiting). when an intiica interrupt occurs, the communication status is judged and its result is passed as a flag over to the main processing. by checking the flags, necessary communication processing is performed. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 551 (1) master operation in single-master system figure 13-29. master operation in single-master system spt = 1 spt = 1 wrel = 1 start end acke = 0 wtim = wrel = 1 no no yes no no no yes yes yes yes stcen = 1? acke = 1 wtim = 0 trc = 1? ackd = 1? ackd = 1? no yes no yes yes no yes no yes no yes no yes no stt = 1 iicwl, iicwh xxh iicf 0xh setting stcen, iicrsv = 0 iicctl0 1xx111xxb iice = 1 iicctl0 0xx111xxb acke = wtim = spie = 1 setting port initializing i 2 c bus note sva xxh writing iica writing iica reading iica intiica interrupt occurs? end of transfer? end of transfer? restart? setting of the port used alternatively as the pin to be used. first, set the port to input mode and the output latch to 0 (see 13.3 (8) port mode register 6 (pm6) ). setting port set the port from input mode to output mode and enable the output of the i 2 c bus (see 13.3 (8) port mode register 6 (pm6) ). sets a transfer clock. sets a local address. sets a start condition. prepares for starting communication (generates a start condition). starts communication (specifies an address and transfer direction). waits for detection of acknowledge. waits for data transmission. starts transmission. communication processing initial setting starts reception. waits for data reception. intiica interrupt occurs? waits for detection of acknowledge. prepares for starting communication (generates a stop condition). waits for detection of the stop condition. intiica interrupt occurs? intiica interrupt occurs? intiica interrupt occurs? note release (scl0 and sda0 pins = high level) the i 2 c bus in conformance with t he specifications of the product that is communicating. if eeprom is outputting a low level to the sda0 pin, for example, set the scl0 pin in the output port mode, and output a clock pulse from the output port until the sda0 pin is constantly at high level. remark conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 552 (2) master operation in multi-master system figure 13-30. master operation in multi-master system (1/3) iicwl, iicwh xxh iicf 0xh setting stcen and iicrsv setting port spt = 1 sva xxh spie = 1 start slave operation slave operation releases the bus for a specific period. bus status is being checked. yes checking bus status note master operation starts? enables reserving communication. disables reserving communication. spd = 1? stcen = 1? iicrsv = 0? a selects a transfer clock. sets a local address. sets a start condition. (communication start request) (no communication start request) ? waiting to be specified as a slave by other master ? waiting for a communication start request (depends on user program) prepares for starting communication (generates a stop condition). waits for detection of the stop condition. no yes yes no intiica interrupt occurs? intiica interrupt occurs? yes no yes no spd = 1? yes no slave operation no intiica interrupt occurs? yes no 1 b spie = 0 yes no waits for a communication request. waits for a communication initial setting iicctl0 1xx111xxb iice = 1 iicctl0 0xx111xxb acke = wtim = spie = 1 setting of the port used alternatively as the pin to be used. first, set the port to input mode and the output latch to 0 (see 13.3 (8) port mode register 6 (pm6) ). setting port set the port from input mode to output mode and enable the output of the i 2 c bus (see 13.3 (8) port mode register 6 (pm6) ). note confirm that the bus is released (cld bit = 1, dad bit = 1) for a specific period (for example, for a period of one frame). if the sda0 pin is constantly at low level, decide whether to release the i 2 c bus (scl0 and sda0 pins = high level) in conformance with the s pecifications of the produc t that is communicating. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 553 figure 13-30. master operation in multi-master system (2/3) stt = 1 wait slave operation yes msts = 1? exc = 1 or coi =1? prepares for starting communication (generates a start condition). secure wait time note by software. waits for bus release (communication being reserved). wait state after stop condition was detected and start condition was generated by the communication reservation function. no intiica interrupt occurs? yes yes no no a c stt = 1 wait note slave operation yes iicbsy = 0? exc = 1 or coi =1? prepares for starting communication (generates a start condition). disables reserving communication. enables reserving communication. waits for bus release detects a stop condition. no no intiica interrupt occurs? yes yes no yes stcf = 0? no b d c d communication processing communication processing note the wait time is calculated as follows. (iicwl setting value + iicwh setting value + 4 (clocks)) f clk + t f 2 remark iicwl: iica low-level width setting register iicwh: iica high-level width setting register t f : sda0 and scl0 signal falling times (see chapter 28 electrical specifications (target) ) f clk : cpu/peripheral hardware clock frequency chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 554 figure 13-30. master operation in multi-master system (3/3) writing iica wtim = 1 wrel = 1 reading iica acke = 1 wtim = 0 wtim = wrel = 1 acke = 0 writing iica yes trc = 1? restart? msts = 1? starts communication (specifies an address and transfer direction). starts transmission. no yes waits for data reception. starts reception. yes no intiica i nterrupt occurs? yes no transfer end? waits for detection of ack. yes no intiica i nterrupt occurs? waits for data transmission. does not participate in communication. yes no intiica i nterrupt occurs? no yes ackd = 1? no yes no c 2 yes msts = 1? no yes transfer end? no yes ackd = 1? no 2 yes msts = 1? no 2 waits for detection of ack. yes no intiica i nterrupt occurs? yes msts = 1? no c 2 yes exc = 1 or coi = 1? no 1 2 spt = 1 stt = 1 slave operation end communication processing communication processing remarks 1. conform to the specifications of the product that is communicatin g, with respect to the transmission and reception formats. 2. to use the device as a master in a multi-ma ster system, read the msts bit each time interrupt intiica has occurred to check the arbitration result. 3. to use the device as a slave in a multi-master system, check the status by using the iics and iicf registers each time interrupt in tiica has occurred, and determine the processing to be performed next. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 555 (3) slave operation the processing procedure of the slave operation is as follows. basically, the slave operation is event-driven. therefor e, processing by the intiica interrupt (processing that must substantially change the operation status such as de tection of a stop condition during communication) is necessary. in the following explanation, it is assumed that the extension code is not supported for data communication. it is also assumed that the intiica interrupt servicing only performs status transition processing, and that actual data communication is performed by the main processing. iica interrupt servicing main processing intiica flag setting data setting therefore, data communication processing is perfo rmed by preparing the following three flags and passing them to the main processing instead of intiica. <1> communication mode flag this flag indicates the following two communication statuses. ? clear mode: status in which data communication is not performed ? communication mode: status in which data comm unication is performed (from valid address detection to stop condition detection, no detec tion of ack from master, address mismatch) <2> ready flag this flag indicates that data communication is enabled. its function is the same as the intiica interrupt for ordinary data communication. this flag is set by interrupt servicing and cleared by the main processing. clear this flag by interrupt servicing when communication is started. however, the ready flag is not set by interrupt servicing when the first data is transmitted. therefore, the first data is transmitted without the flag being cleared (an address match is interpreted as a request for the next data). <3> communication direction flag this flag indicates the direction of communication. its value is the same as trc. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 556 the main processing of the slave operation is explained next. start serial interface iica and wait until communication is enabled. when communication is enabled, execute communication by using the communication mode flag an d ready flag (processing of the stop condition and start condition is performed by an interrupt. here, check the status by using the flags). the transmission operation is repeated until the master no longer returns ack. if ack is not returned from the master, communication is completed. for reception, the necessary amount of data is received. when communication is completed, ack is not returned as the next data. after tha t, the master generates a stop condition or restart condition. exit from the communication status occurs in this way. figure 13-31. slave operation flowchart (1) yes yes yes yes yes yes yes no no no no no no wrel = 1 ackd = 1? no yes no yes no start communication mode flag = 1? communication mode flag = 1? communication direction flag = 1? ready flag = 1? communication direction flag = 1? reading iica clearing ready flag clearing ready flag communication direction flag = 1? clearing communication mode flag wrel = 1 writing iica sva xxh sets a local address. iicwl, iicwh xxh selects a transfer clock. iicf 0xh setting iicrsv sets a start condition. starts transmission. starts reception. communication mode flag = 1? ready flag = 1? setting port setting port communication processing initial setting setting of the port used alternatively as the pin to be used. first, set the port to input mode and the output latch to 0 (see 13.3 (8) port mode register 6 (pm6) ). set the port from input mode to output mode and enable the output of the i 2 c bus (see 13.3 (8) port mode register 6 (pm6) ). iicctl0 0xx011xxb acke = wtim = 1, spie = 0 iicctl0 1xx011xxb iice = 1 remark conform to the specifications of the product that is in communication, regarding the transmission and reception formats. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 557 an example of the processing procedur e of the slave with the intiica interrupt is explained below (processing is performed assuming that no extension code is used). the intiica interrupt checks the status, and the following operations are performed. <1> communication is stopped if the stop condition is issued. <2> if the start condition is issued, the address is c hecked and communication is completed if the address does not match. if the address matches, the communi cation mode is set, wait is cancelled, and processing returns from the interrupt (the ready flag is cleared). <3> for data transmit/receive, only the ready flag is set. processing returns from the interrupt with the i 2 c bus remaining in the wait state. remark <1> to <3> above correspond to <1> to <3> in figure 13-32 slave operation flowchart (2). figure 13-32. slave operation flowchart (2) yes yes yes no no no intiica generated set ready flag interrupt servicing completed spd = 1? std = 1? coi = 1? communication direction flag trc set communication mode flag clear ready flag clear c ommunication direction flag, ready flag, and communication mode flag <1> <2> <3> chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 558 13.5.17 timing of i 2 c interrupt request (intiica) occurrence the timing of transmitting or receiving data and generation of interrupt request signal intiica, and the value of the iics register when the intiica signal is generated are shown below. remark st: start condition ad6 to ad0: address r/w: transfer direction specification ack: acknowledge d7 to d0: data sp: stop condition chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 559 (1) master device operation (a) start ~ address ~ data ~ data ~ stop (transmission/reception) (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt = 1 3 4 5 2 1 1: iics = 1000110b 2: iics = 1000000b 3: iics = 1000000b (sets wtim to 1) note 4: iics = 100000b (sets spt to 1) note 5: iics = 00000001b note to generate a stop condition, set wtim to 1 and ch ange the timing for generating the intiica interrupt request signal. remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt = 1 3 4 2 1 1: iics = 1000110b 2: iics = 1000100b 3: iics = 100000b (sets spt to 1) 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 560 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack stt = 1 spt = 1 3 4 7 2 1 5 6 1: iics = 1000110b 2: iics = 1000000b (sets wtim to 1) note 1 3: iics = 100000b (clears wtim to 0 note 2 , sets stt to 1) 4: iics = 1000110b 5: iics = 1000000b (sets wtim to 1) note 3 6: iics = 100000b (sets spt to 1) 7: iics = 00000001b notes 1. to generate a start condition, set wtim to 1 and change the timing for generating the intiica interrupt request signal. 2. clear wtim to 0 to restore the original setting. 3. to generate a stop condition, set wtim to 1 and change the timing for generating the intiica interrupt request signal. remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack stt = 1 spt = 1 3 4 5 2 1 1: iics = 1000110b 2: iics = 100000b (sets stt to 1) 3: iics = 1000110b 4: iics = 100000b (sets spt to 1) 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 561 (c) start ~ code ~ data ~ data ~ stop (extension code transmission) (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt = 1 3 4 5 2 1 1: iics = 1010110b 2: iics = 1010000b 3: iics = 1010000b (sets wtim to 1) note 4: iics = 101000b (sets spt to 1) 5: iics = 00000001b note to generate a stop condition, set wtim to 1 and ch ange the timing for generating the intiica interrupt request signal. remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt = 1 3 4 2 1 1: iics = 1010110b 2: iics = 1010100b 3: iics = 101000b (sets spt to 1) 4: iics = 00001001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 562 (2) slave device operation (slave address data reception) (a) start ~ address ~ data ~ data ~ stop (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics = 0001110b 2: iics = 0001000b 3: iics = 0001000b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics = 0001110b 2: iics = 0001100b 3: iics = 000100b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 563 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim = 0 (after restart, matches with sva) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics = 0001110b 2: iics = 0001000b 3: iics = 0001110b 4: iics = 0001000b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 (after restart, matches with sva) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics = 0001110b 2: iics = 000100b 3: iics = 0001110b 4: iics = 000100b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 564 (c) start ~ address ~ data ~ start ~ code ~ data ~ stop (i) when wtim = 0 (after restart, do es not match address (= extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics = 0001110b 2: iics = 0001000b 3: iics = 0010010b 4: iics = 0010000b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 (after restart, do es not match address (= extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 5 6 2 1 4 1: iics = 0001110b 2: iics = 000100b 3: iics = 0010010b 4: iics = 0010110b 5: iics = 001000b 6: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 565 (d) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim = 0 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 2 1 1: iics = 0001110b 2: iics = 0001000b 3: iics = 00000110b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 2 1 1: iics = 0001110b 2: iics = 000100b 3: iics = 00000110b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 566 (3) slave device operation (w hen receiving extension code) the device is always participating in communication when it receives an extension code. (a) start ~ code ~ data ~ data ~ stop (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics = 0010010b 2: iics = 0010000b 3: iics = 0010000b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 5 2 1 1: iics = 0010010b 2: iics = 0010110b 3: iics = 0010100b 4: iics = 001000b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 567 (b) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim = 0 (after restart, matches sva) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics = 0010010b 2: iics = 0010000b 3: iics = 0001110b 4: iics = 0001000b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 (after restart, matches sva) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 6 2 1 5 1: iics = 0010010b 2: iics = 0010110b 3: iics = 001000b 4: iics = 0001110b 5: iics = 000100b 6: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 568 (c) start ~ code ~ data ~ start ~ code ~ data ~ stop (i) when wtim = 0 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics = 0010010b 2: iics = 0010000b 3: iics = 0010010b 4: iics = 0010000b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 7 2 1 5 6 1: iics = 0010010b 2: iics = 0010110b 3: iics = 001000b 4: iics = 0010010b 5: iics = 0010110b 6: iics = 001000b 7: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 569 (d) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim = 0 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 2 1 1: iics = 00100010b 2: iics = 00100000b 3: iics = 00000110b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics = 00100010b 2: iics = 00100110b 3: iics = 0010000b 4: iics = 00000110b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 570 (4) operation without communication (a) start ~ code ~ data ~ data ~ stop st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 1 1: iics = 00000001b remark : generated only when spie = 1 (5) arbitration loss operation (opera tion as slave after arbitration loss) when the device is used as a master in a multi-master system, read the msts bit each time interrupt request signal intiica has occurred to check the arbitration result. (a) when arbitration loss occurs durin g transmission of slave address data (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics = 0101110b 2: iics = 0001000b 3: iics = 0001000b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 571 (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics = 0101110b 2: iics = 0001100b 3: iics = 000100b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (b) when arbitration loss occurs dur ing transmission of extension code (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics = 0110010b 2: iics = 0010000b 3: iics = 0010000b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 572 (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 5 2 1 1: iics = 0110010b 2: iics = 0010110b 3: iics = 0010100b 4: iics = 001000b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (6) operation when arbitration loss occurs (no communication after arbitration loss) when the device is used as a master in a multi-master system, read the msts bit each time interrupt request signal intiica has occurred to check the arbitration result. (a) when arbitration loss occu rs during transmission of slave address data (when wtim = 1) st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 2 1 1: iics = 01000110b 2: iics = 00000001b remark : always generated : generated only when spie = 1 chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 573 (b) when arbitration loss occurs dur ing transmission of extension code st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 2 1 1: iics = 0110010b sets lrel = 1 by software 2: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (c) when arbitration loss occu rs during transmission of data (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 2 1 1: iics = 10001110b 2: iics = 01000000b 3: iics = 00000001b remark : always generated : generated only when spie = 1 chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 574 (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 2 1 1: iics = 10001110b 2: iics = 01000100b 3: iics = 00000001b remark : always generated : generated only when spie = 1 (d) when loss occurs due to rest art condition during data transfer (i) not extension code (example: unmatches with sva) st ad6 to ad0 r/w ack d7 to dn ad6 to ad0 ack sp st r/w d7 to d0 ack 3 2 1 1: iics = 1000110b 2: iics = 01000110b 3: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care n = 6 to 0 chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 575 (ii) extension code st ad6 to ad0 r/w ack d7 to dn ad6 to ad0 ack sp st r/w d7 to d0 ack 3 2 1 1: iics = 1000110b 2: iics = 01100010b sets lrel = 1 by software 3: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care n = 6 to 0 (e) when loss occurs due to st op condition during data transfer st ad6 to ad0 r/w ack d7 to dn sp 2 1 1: iics = 10000110b 2: iics = 01000001b remark : always generated : generated only when spie = 1 : don?t care n = 6 to 0 chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 576 (f) when arbitration loss occurs due to low-level da ta when attempting to generate a restart condition (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack stt = 1 3 4 5 2 1 1: iics = 1000110b 2: iics = 1000000b (sets wtim to 1) 3: iics = 1000100b (clears wtim to 0) 4: iics = 01000000b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack stt = 1 3 4 2 1 1: iics = 1000110b 2: iics = 1000100b (sets stt to 1) 3: iics = 01000100b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 577 (g) when arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 ack sp stt = 1 3 4 2 1 1: iics = 1000110b 2: iics = 1000000b (sets wtim to 1) 3: iics = 100000b (sets stt to 1) 4: iics = 01000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp stt = 1 2 3 1 1: iics = 1000110b 2: iics = 100000b (sets stt to 1) 3: iics = 01000001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 578 (h) when arbitration loss occurs due to low-level data when attemp ting to generate a stop condition (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack spt = 1 3 4 5 2 1 1: iics = 1000110b 2: iics = 1000000b (sets wtim to 1) 3: iics = 1000100b (clears wtim to 0) 4: iics = 01000100b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack spt = 1 3 4 2 1 1: iics = 1000110b 2: iics = 1000100b (sets spt to 1) 3: iics = 01000100b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 579 13.6 timing charts when using the i 2 c bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the mast er device transmits the trc bit (bit 3 of the iica status register (iics)), which specifies the data transfer di rection, and then starts serial communication with the slave device. figures 13-33 and 13-34 show timing charts of the data communication. the iica shift register (iica)?s shift operation is synchroni zed with the falling edge of the serial clock (scl0). the transmit data is transferred to the so latch an d is output (msb first) via the sda0 pin. data input via the sda0 pin is captured into iica at the rising edge of scl0. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 580 figure 13-33. example of master to slave communication (when 9-clock wait is selected fo r both master and slave) (1/3) (1) start condition ~ address h h l l l l h h l l 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iica ackd std spd wtim acke msts stt spt wrel intiica trc iica ackd std spd wtim acke msts stt spt wrel intiica trc scl0 sda0 processing by master device transfer lines processing by slave device iica address iica data transmit start condition receive note 1 iica ffh note 2 note 2 notes 1. write data to iica, not setting wrel, in order to cancel a wait state during master transmission. 2. to cancel slave wait, write ?ffh? to iica or set wrel. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 581 figure 13-33. example of master to slave communication (when 9-clock wait is selected fo r both master and slave) (2/3) (2) data h h l l l l l l h h h h l l l l l 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 ack ack iica ackd std spd wtim acke msts stt spt wrel intiica trc iica ackd std spd wtim acke msts stt spt wrel intiica trc scl0 sda0 processing by master device transfer lines processing by slave device iica data iica ffh iica ffh iica data transmit receive note 2 note 2 note 2 note 2 note 1 note 1 notes 1. write data to iica, not setting wrel, in order to cancel a wait state during master transmission. 2. to cancel slave wait, write ?ffh? to iica or set wrel. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 582 figure 13-33. example of master to slave communication (when 9-clock wait is selected fo r both master and slave) (3/3) (3) stop condition h h l l l l h h l 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 ack iica ackd std spd wtim acke msts stt spt wrel intiica trc iica ackd std spd wtim acke msts stt spt wrel intiica trc scl0 sda0 processing by master device transfer lines processing by slave device iica address iica ffh note 2 stop condition start condition transmit note 2 (when spie = 1) receive (when spie = 1) iica data note 1 iica ffh note 2 note 2 notes 1. write data to iica, not setting wrel, in order to cancel a wait state during master transmission. 2. to cancel slave wait, write ?ffh? to iica or set wrel. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 583 figure 13-34. example of slave to master communication (when 8-clock wait is selected for master, 9-clock wait is selected for slave) (1/3) (1) start condition ~ address h h l l l h l l l 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 d4 d3 d2 d5 d6 d7 ack r iica ackd std spd wtim acke msts stt spt wrel intiica trc iica ackd std spd wtim acke msts stt spt wrel intiica trc scl0 sda0 processing by master device transfer lines processing by slave device iica address iica ffh note 1 note 1 iica data transmit receive transmit receive note 2 notes 1. to cancel master wait, write ?ffh? to iica or set wrel. 2. write data to iica, not setting wrel, in order to cancel a wait state during slave transmission. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 584 figure 13-34. example of slave to master communication (when 8-clock wait is selected for master, 9-clock wait is selected for slave) (2/3) (2) data h h h l l l l l l l h h l l l l l 1 89 2345678 9 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 iica ackd std spd wtim acke msts stt spt wrel intiica trc iica ackd std spd wtim acke msts stt spt wrel intiica trc scl0 sda0 processing by master device transfer lines processing by slave device note 2 note 2 receive transmit iica data iica data iica ffh note 1 iica ffh note 1 note 1 note 1 notes 1. to cancel master wait, write ?ffh? to iica or set wrel. 2. write data to iica, not setting wrel, in order to cancel a wait state during slave transmission. chapter 13 serial interface iica preliminary user?s manual u19291ej1v0ud 585 figure 13-34. example of slave to master communication (when 8-clock and 9-clock wait is selected for m aster, 9-clock wait is selected for slave) (3/3) (3) stop condition h h l l l 12345678 9 1 d7 d6 d5 d4 d3 d2 d1 d0 ad6 nack iica ackd std spd wtim acke msts stt spt wrel intiica trc iica ackd std spd wtim acke msts stt spt wrel intiica trc scl0 sda0 processing by master device transfer lines processing by slave device iica address iica ffh note 1 note 2 iica data stop condition start condition (when spie = 1) (when spie = 1) transmit receive iica ffh note 1 note 1 receive notes 1, 3 note 3 notes 1. to cancel wait, write ?ffh? to iica or set wrel. 2. write data to iica, not setting wrel, in order to cancel a wait state during slave transmission. 3. if a wait state during slave transmission is canceled by setting wrel, trc will be cleared. preliminary user?s manual u19291ej1v0ud 586 chapter 14 multiplier/divider 14.1 functions of multiplier/divider the multiplier/divider has the following functions. ? 16 bits 16 bits = 32 bits (multiplication) ? 32 bits 32 bits = 32 bits, 32-bit remainder (division) 14.2 configuration of multiplier/divider the multiplier/divider consis ts of the following hardware. table 14-1. configuration of multiplier/divider item configuration registers multiplication/division data register a (l) (mdal) multiplication/division data register a (h) (mdah) multiplication/division data register b (l) (mdbl) multiplication/division data register b (h) (mdbh) multiplication/division dat a register c (l) (mdcl) multiplication/division data register c (h) (mdch) control register multiplication/division control register (mduc) figure 14-1 shows a block diagram of the multiplier/divider. chapter 14 multiplier/divider preliminary user?s manual u19291ej1v0ud 587 figure 14-1. block diagram of multiplier/divider internal bus f prs multiplication result (product) division result (remainder) division result (quotient) multiplier dividend divisor multiplicand multiplication/division data register c mdch mdcl counter data flow during division data flow during multiplication divmode multiplication/division control register (mduc) controller controller controller divst intmd clear start multiplication/division data register a mdah mdal multiplication/division data register b mdbh mdbl multiplication/division block chapter 14 multiplier/divider preliminary user?s manual u19291ej1v0ud 588 (1) multiplication/division da ta register a (mdah, mdal) the mdah and mdal registers set the values that are used for a multipli cation or division operation and store the operation result. they set the multiplier and mu ltiplicand data in the multiplication mode, and set the dividend data in the division mode. furthermore, the operation result (quotient) is stored in the mdah and mdal registers in the division mode. mdah and mdal can be set by a 16-bit manipulation instruction. reset signal generation clears these registers to 0000h. figure 14-2. format of multiplication/ division data register a (mdah, mdal) ffff3h ffff2h mdah mdah 15 mdah 14 mdah 13 mdah 12 mdah 11 mdah 10 mdah 9 mdah 8 mdah 7 mdah 6 mdah 5 mdah 4 mdah 3 mdah 2 mdah 1 mdah 0 ffff1h ffff0h mdal mdal 15 mdal 14 mdal 13 mdal 12 mdal 11 mdal 10 mdal 9 mdal 8 mdal 7 mdal 6 mdal 5 mdal 4 mdal 3 mdal 2 mdal 1 mdal 0 address: ffff0h, ffff1h, ffff2h, ffff3h after reset: 0000h, 0000h r/w symbol symbol cautions 1. do not rewrite the mdah and mdal values during division ope ration processing (while the multiplication/division control register (mduc) is 81h). the operation will be executed in this case, but the operation resu lt will be an undefined value. 2. the mdah and mdal values read during division operation processing (while mduc is 81h) will not be guaranteed. the following table shows the functions of md ah and mdal during operation execution. table 14-2. functions of mdah and mdal during operation execution divmode operation mode setting operation result 0 multiplication mode mdah: multiplier mdal: multiplicand ? 1 division mode mdah: divisor (higher 16 bits) mdal: dividend (lower 16 bits) mdah: division result (quotient) higher 16 bits mdal: division result (quotient) lower 16 bits remark divmode: bit 7 of the multiplica tion/division control register (mduc) chapter 14 multiplier/divider preliminary user?s manual u19291ej1v0ud 589 (2) multiplication/division da ta register b (mdbl, mdbh) the mdbh and mdbl registers set the values that are used for multiplica tion or division operation and store the operation result. they store t he operation result (product) in the multiplication mode and set the divisor data in the division mode. mdbh and mdbl can be set by a 16-bit manipulation instruction. reset signal generation clears these registers to 0000h. figure 14-3. format of multiplication/ division data register b (mdbh, mdbl) address: ffff4h, ffff5h, ffff6h, ffff7h after reset: 0000h, 0000h r/w symbol ffff7h ffff6h mdbh mdbh 15 mdbh 14 mdbh 13 mdbh 12 mdbh 11 mdbh 10 mdbh 9 mdbh 8 mdbh 7 mdbh 6 mdbh 5 mdbh 4 mdbh 3 mdbh 2 mdbh 1 mdbh 0 symbol ffff5h ffff4h mdbl mdbl 15 mdbl 14 mdbl 13 mdbl 12 mdbl 11 mdbl 10 mdbl 9 mdbl 8 mdbl 7 mdbl 6 mdbl 5 mdbl 4 mdbhl 3 mdbl 2 mdbl 1 mdbl 0 cautions 1. do not rewrite the mdbh and mdbl values during division ope ration processing (while the multiplication/division contro l register (mduc) is 81h). the operation result will be an undefined value. 2. do not set mdbh and mdbl to 0000h in the di vision mode. if they are set, the operation result will be an undefined value. the following table shows the functions of md bh and mdbl during operation execution. table 14-3. functions of mdbh a nd mdbl during operation execution divmode operation mode setting operation result 0 multiplication mode ? mdbh: multiplication result (product) higher 16 bits mdbl: multiplication result (product) lower 16 bits 1 division mode mdbh: divisor (higher 16 bits) mdbl: dividend (lower 16 bits) ? remark divmode: bit 7 of the multiplica tion/division control register (mduc) chapter 14 multiplier/divider preliminary user?s manual u19291ej1v0ud 590 (3) multiplication/division da ta register c (mdcl, mdch) the mdch and mdcl registers store rema inder value of the operation result in the division mode. they are not used in the multiplication mode. mdch and mdcl can be read by a 16-bit manipulation instruction. reset signal generation clears these registers to 0000h. figure 14-4. format of multiplication/ division data register c (mdch, mdcl) address: f00e0h, f00e1h, f00e2h, f00e3h after reset: 0000h, 0000h r/w f00e3h f00e2h mdch mdch 15 mdch 14 mdch 13 mdch 12 mdch 11 mdch 10 mdch 9 mdch 8 mdch 7 mdch 6 mdch 5 mdch 4 mdch 3 mdch 2 mdch 1 mdch 0 f00e1h f00e0h mdcl mdcl 15 mdcl 14 mdcl 13 mdcl 12 mdcl 11 mdcl 10 mdcl 9 mdcl 8 mdcl 7 mdcl 6 mdcl 5 mdcl 4 mdcl 3 mdcl 2 mdcl 1 mdcl 0 symbol symbol caution the mdch and mdcl values read durin g division operation processing (while the multiplication/division control register (mduc) is 81h) will not be guaranteed. table 14-4. functions of mdch a nd mdcl during operation execution divmode operation mode setting operation result 0 multiplication mode ? ? 1 division mode ? mdch: remainder (higher 16 bits) mdcl: remainder (lower 16 bits) remark divmode: bit 7 of the multiplica tion/division control register (mduc) the register configuration differs bet ween when multiplication is executed and when division is executed, as follows. ? register configuration during multiplication chapter 14 multiplier/divider preliminary user?s manual u19291ej1v0ud 591 14.3 register controlling multiplier/divider the multiplier/divider is controlled by using t he multiplication/division control register (mduc). (1) multiplication/division control register (mduc) mduc is an 8-bit register that controls the operation of the multiplier/divider. mduc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 14-5. format of multiplicatio n/division control register (mduc) address: f00e8h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 <0> mduc divmode 0 0 0 0 0 0 divst divmode operation mode (multi plication/division) selection 0 multiplication mode 1 division mode divst note division operation start/stop 0 division operation processing complete 1 starts division operation/divisi on operation processing in progress note divst can only be set (1) in the division mode. in the division mode, division operation is started by setting (1) divst. divst is automatically cleared (0 ) when the operation ends. in the multiplication mode, operation is automatically started by setting the multiplier and multiplicand to mdah and mdal, respectively. cautions 1. do not rewrite divmode during operation pr ocessing (while divst is 1). if it is rewritten, the operation result will be an undefined value. 2. divst cannot be cleared (0) by using software during division operation processing (while divst is 1). chapter 14 multiplier/divider preliminary user?s manual u19291ej1v0ud 592 14.4 operations of multiplier/divider 14.4.1 multiplication operation ? initial setting <1> set bit 7 (divmode) of the multiplicati on/division control register (mduc) to 0. <2> set the multiplicand to the multiplicat ion/division data register a (l) (mdal). <3> set the multiplier to the multiplicat ion/division data register a (h) (mdah). (there is no preference in the or der of executing steps <2> and <3>. multiplication operation is automatically started when the mu ltiplier and multiplicand are set to mdah and mdal, respectively.) ? during operation processing <4> wait for at least one clock. the operation will end when one clock has been issued. ? operation end <5> read the product (lower 16 bits) from the mu ltiplication/division data register b (l) (mdbl). <6> read the product (higher 16 bits) from the mult iplication/division data register b (h) (mdbh). (there is no preference in the order of executing steps <5> and <6>.) ? next operation <7> to execute multiplication operation next, start from the ?initial setting? for multiplication operation. <8> to execute division operation next, start from the ?initial setting? in 14.4.2 division operation . remark steps <1> to <7> correspond to <1> to <7> in figure 14-6. figure 14-6. timing diagram of multiplication operation (0003h 0002h) mdah 0003h 0002h 0006h ffffh ffffh fffe000h 1fffeh initial value = 0 initial value = 0 initial value = 0 mdal mdbh divmode operation clock "0" <1> <2> <4> <3> <7> <5>, <6> chapter 14 multiplier/divider preliminary user?s manual u19291ej1v0ud 593 14.4.2 division operation ? initial setting <1> set bit 7 (divmode) of the multiplicati on/division control register (mduc) to 1. <2> set the dividend (higher 16 bits) to the mu ltiplication/division data register a (h) (mdah). <3> set the dividend (lower 16 bits) to the mu ltiplication/division data register a (l) (mdal). <4> set the divisor (higher 16 bits) to the mult iplication/division data register b (h) (mdbh). <5> set the divisor (lower 16 bits) to the multip lication/division data register b (l) (mdbl). <6> set bit 0 (divst) of mduc to 1. (there is no preference in the order of executing steps <2> to <5>.) ? during operation processing <7> the operation will end when one of the following processing is completed. ? a wait of at least 16 clocks (the operat ion will end when 16 clocks have been issued.) ? a check whether divst has been cleared ? generation of a division completion interrupt (intmd) (the read values of mdbl, mdbh, mdch, and mdcl during operation processing are not guaranteed.) ? operation end <8> divst is cleared (0) and an interrupt request si gnal (intmd) is generated (end of operation). <9> read the quotient (lower 16 bits) from mdal. <10> read the quotient (higher 16 bits) from mdah. <11> read the remainder (lower 16 bits) from mu ltiplication/division data register c (l) (mdcl). <12> read the remainder (higher 16 bits) from the multiplication/division data register c (h) (mdch). (there is no preference in the order of executing steps <9> to <12>.) ? next operation <13> to execute multiplication operation ne xt, start from the ?initial setting? in 14.4.1 multiplication operation . <14> to execute division operation next, start from the ?initial setting? for division operation. remark steps <1> to <12> correspond to <1> to <12> in figure 14-7. chapter 14 multiplier/divider preliminary user?s manual u19291ej1v0ud 594 figure 14-7. timing diagram of division operation (example: 35 6 = 5, remainder 5) mdah, mdal 0000 008c 0000 0000 0000 0000 0000 0000 0000 0006 xxxx xxxx 0000 0230 0000 08c0 0000 2300 0000 8c00 0002 3000 0008 c000 0023 0000 008c 0000 0230 0000 08c0 0000 2300 0000 8c00 0000 3000 0000 c000 0001 0000 0002 0000 0002 0000 0005 0000 0005 divmode operation clock divst counter undefined intmd mdbh, mdbl xxxx xxxx mdch, mdcl xxxx xxxx 123456 <1> <2> <3> 789 a b c de f 0 0 0000 0023 <4> <5> <6> <7> <9>, <10> <11>, <12> <8> <8> preliminary user?s manual u19291ej1v0ud 595 chapter 15 dma controller the 78k0r/kx3-l has an internal dma (direct memory access) controller. data can be automatically transferred between the peri pheral hardware supporting dma, sfrs, and internal ram without via cpu. as a result, the normal internal operation of the cpu and data transfer can be execut ed in parallel with transfer between the sfr and internal ram, and therefore, a large c apacity of data can be processed. in addition, real-time control using communication, timer, and a/d can also be realized. 15.1 functions of dma controller { number of dma channels: 2 { transfer unit: 8 or 16 bits { maximum transfer unit: 1024 times { transfer type: 2-cycle transfer (one transfer is proc essed in 2 clocks and the cpu stops during that processing.) { transfer mode: single-transfer mode { transfer request: selectable from the following peripheral hardware interrupts ? a/d converter ? serial interface (csi00, csi01, csi10, uart0, uart1, or iic10) ? timer (channel 0, 1, 4, or 5) { transfer target: between sfr and internal ram here are examples of functions using dma. ? successive transfer of serial interface ? batch transfer of analog data ? capturing a/d conversion result at fixed interval ? capturing port value at fixed interval chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 596 15.2 configuration of dma controller the dma controller includes the following hardware. table 15-1. configuration of dma controller item configuration address registers ? dma sfr address registers 0, 1 (dsa0, dsa1) ? dma ram address regist ers 0, 1 (dra0, dra1) count register ? dma byte count registers 0, 1 (dbc0, dbc1) control registers ? dma mode control registers 0, 1 (dmc0, dmc1) ? dma operation control register 0, 1 (drc0, drc1) (1) dma sfr address register n (dsan) this is an 8-bit register that is us ed to set an sfr address that is the tr ansfer source or destination of dma channel n. set the lower 8 bits of the sfr addresses fff00h to fffffh. this register is not automatically incr emented but fixed to a specific value. in the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address. dsan can be read or written in 8-bit units. however, it cannot be written during dma transfer. reset signal generation clears this register to 00h. figure 15-1. format of dma sfr address register n (dsan) address: fffb0h (dsa0), fffb1h (dsa1) after reset: 00h r/w 7 6 5 4 3 2 1 0 dsan remark n: dma channel number (n = 0, 1) chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 597 (2) dma ram address register n (dran) this is a 16-bit register that is used to set a ram address that is the transfer source or destination of dma channel n. addresses of the internal ram area other than the general-purpose registers (ff900h to ffedfh in the case of the pd78f1001, 78f1004, and 78f1007) can be set to this register. set the lower 16 bits of the ram address. this register is automatically in cremented when dma transfer has been start ed. it is incremented by +1 in the 8-bit transfer mode and by +2 in the 16-bit transfer mo de. dma transfer is started from the address set to this dran register. when the data of the last address has been transferred, dran st ops with the value of the last address +1 in the 8-bit transfer mode, and t he last address +2 in the 16-bit transfer mode. in the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address. dran can be read or written in 8-bit or 16-bit units. however, it cannot be written during dma transfer. reset signal generation clears this register to 0000h. figure 15-2. format of dma ram address register n (dran) address: fffb2h, fffb3h (dra0), fffb4h, fffb5h (dra1) after reset: 0000h r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dran (n = 0, 1) remark n: dma channel number (n = 0, 1) dra0h: fffb3h dra1h: fffb5h dra0l: fffb2h dra1l: fffb4h chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 598 (3) dma byte count register n (dbcn) this is a 10-bit register that is us ed to set the number of times dma channel n executes transfer. be sure to set the number of times of transfer to this dbcn regi ster before executing dma transfer (up to 1024 times). each time dma transfer has been executed, this regist er is automatically decremented. by reading this dbcn register during dma transfer, the remain ing number of times of transfer can be learned. dbcn can be read or written in 8-bit or 16-bit units. however, it cannot be written during dma transfer. reset signal generation clears this register to 0000h. figure 15-3. format of dma byte count register n (dbcn) address: fffb6h, fffb7h (dbc0), fffb8h, fffb9h (dbc1) after reset: 0000h r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dbcn 0 0 0 0 0 0 (n = 0, 1) dbcn[9:0] number of times of transfer (when dbcn is written) remaining number of times of transfer (when dbcn is read) 000h 1024 completion of transfer or waiting for 1024 times of dma transfer 001h 1 waiting for remaining one time of dma transfer 002h 2 waiting for remaining two times of dma transfer 003h 3 waiting for remaining three times of dma transfer ? ? ? ? ? ? ? ? ? 3feh 1022 waiting for remaining 1022 times of dma transfer 3ffh 1023 waiting for remaining 1023 times of dma transfer cautions 1. be sure to cl ear bits 15 to 10 to ?0?. 2. if the general-purpose register is specifie d or the internal ram sp ace is exceeded as a result of continuous transfer , the general-purpose register or sfr space are written or read, resulting in loss of data in these spaces. be sure to set the number of times of transfer that is within the internal ram space. remark n: dma channel number (n = 0, 1) dbc0h: fffb7h dbc1h: fffb9h dbc0l: fffb6h dbc1l: fffb8h chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 599 15.3 registers controlling dma controller dma controller is controlle d by the following registers. ? dma mode control register n (dmcn) ? dma operation control register n (drcn) remark n: dma channel number (n = 0, 1) (1) dma mode control register n (dmcn) dmcn is a register that is used to set a transfer mode of dma channel n. it is used to select a transfer direction, data size, setting of pending, and start source. bit 7 (stgn) is a software trigger that starts dma. rewriting bits 6, 5, and 3 to 0 of dmcn is prohibited during operation (when dstn = 1). dmcn can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 15-4. format of dma mode control register n (dmcn) (1/2) address: fffbah (dmc0), fffbbh (dmc1) after reset: 00h r/w symbol <7> <6> <5> <4> 3 2 1 0 dmcn stgn drsn dsn dwaitn ifcn3 ifcn2 ifcn1 ifcn0 stgn note dma transfer start software trigger 0 no trigger operation 1 dma transfer is started when dma operation is enabled (denn = 1). dma transfer is started by writing 1 to stgn when dma operation is enabled (denn = 1). when this bit is read, 0 is always read. drsn selection of dma transfer direction 0 sfr to internal ram 1 internal ram to sfr dsn specification of transfer data size for dma transfer 0 8 bits 1 16 bits dwaitn pending of dma transfer 0 executes dma transfer upon dma start request (not held pending). 1 holds dma start request pending if any. dma transfer that has been held pending can be star ted by clearing the value of dwaitn to 0. it takes 2 clocks to actually hold dma transfer pending when the value of dwaitn is set to 1. note the software trigger (stgn) can be used r egardless of the ifcn0 to ifcn3 values. remark n: dma channel number (n = 0, 1) chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 600 figure 15-4. format of dma mode control register n (dmcn) (2/2) address: fffbah (dmc0), fffbbh (dmc1) after reset: 00h r/w symbol <7> <6> <5> <4> 3 2 1 0 dmcn stgn drsn dsn dwaitn ifcn3 ifcn2 ifcn1 ifcn0 selection of dma start source note ifcn 3 ifcn 2 ifcn 1 ifcn 0 trigger signal trigger contents 0 0 0 0 ? disables dma transfer by interrupt. (only software trigger is enabled.) 0 0 1 0 inttm00 timer channel 0 interrupt 0 0 1 1 inttm01 timer channel 1 interrupt 0 1 0 0 inttm04 timer channel 4 interrupt 0 1 0 1 inttm05 timer channel 5 interrupt 0 1 1 0 intst0/intcsi00 uart0 transmission end interrupt/csi00 transfer end interrupt 0 1 1 1 intsr0/intcsi01 uart0 reception end interrupt/csi01 transfer end interrupt 1 0 0 0 intst1/intcsi10/intiic10 uart1 transmission end interrupt/ csi10 transfer end interrupt/ iic10 transfer end interrupt 1 0 0 1 intsr1 uart1 reception end interrupt 1 1 0 0 intad a/d conversion end interrupt other than above setting prohibited note the software trigger (stgn) can be used r egardless of the ifcn0 to ifcn3 values. remark n: dma channel number (n = 0, 1) chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 601 (2) dma operation control register n (drcn) drcn is a register that is used to enable or disable transfer of dma channel n. rewriting bit 7 (denn) of this register is prohibited during operation (when dstn = 1). drcn can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 15-5. format of dma oper ation control register n (drcn) address: fffbch (drc0), fffbdh (drc1) after reset: 00h r/w symbol <7> 6 5 4 3 2 1 <0> drcn denn 0 0 0 0 0 0 dstn denn dma operation enable flag 0 disables operation of dma channel n (stops operating cock of dma). 1 enables operation of dma channel n. dmac waits for a dma trigger when dstn = 1 after dma operation is enabled (denn = 1). dstn dma transfer mode flag 0 dma transfer of dma channel n is completed. 1 dma transfer of dma channel n is not completed (still under execution). dmac waits for a dma trigger when dstn = 1 after dma operation is enabled (denn = 1). when a software trigger (stgn) or the start source trigger set by ifcn3 to ifcn0 is input, dma transfer is started. when dma transfer is completed after that, this bit is automatic ally cleared to 0. write 0 to this bit to forcibly te rminate dma transfer under execution. cautions 1. the dstn flag is au tomatically cleared to 0 when a dma transfer is completed. writing the denn flag is enabled only wh en dstn = 0. when a dma transfer is terminated without waiting for ge neration of the interrupt (intdman) of dman, therefore, set dstn to 0 and then denn to 0 (for details , refer to 15.5.5 forced termination by software). 2. when the fsel bit of the osmc register has been set to 1, do not enable (denn = 1) dma operation for at least th ree clocks after the setting. remark n: dma channel number (n = 0, 1) chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 602 no no dstn = 1 dstn = 0 intdman = 1 dma trigger = 1? dbcn = 0000h ? yes yes denn = 1 setting dsan, dran, dbcn, and dmcn transmitting dma request receiving dma acknowledge dma transfer dran = dran + 1 (or + 2) dbcn = dbcn ? 1 denn = 0 set by software program operation by dma controller (hardware) set by software program 15.4 operation of dma controller 15.4.1 operation procedure <1> the dma controller is enabled to operate when denn = 1. before writing the other registers, be sure to set denn to 1. use 80h to write wit h an 8-bit manipulation instruction. <2> set an sfr address, a ram address, the number of times of transfer, and a transfer mode of dma transfer to the dsan, dran, cbcn, and dmcn registers. <3> the dma controller waits for a dma trigger when dstn = 1. use 81h to write with an 8-bit manipulation instruction. <4> when a software trigger (stgn) or a start source tri gger specified by ifcn3 to ifcn0 is input, a dma transfer is started. <5> transfer is completed when the number of times of trans fer set by the dbcn register reaches 0, and transfer is automatically terminated by occu rrence of an interrupt (intdman). <6> stop the operation of the dma c ontroller by clearing denn to 0 w hen the dma controller is not used. figure 15-6. operation procedure remark n: dma channel number (n = 0, 1) chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 603 15.4.2 transfer mode the following four modes can be selected for dma transfe r by using bits 6 and 5 (drsn and dsn) of the dmcn register. drsn dsn dma transfer mode 0 0 transfer from sfr of 1-byte data (fixed add ress) to ram (address is incremented by +1) 0 1 transfer from sfr of 2-byte data (fixed add ress) to ram (address is incremented by +2) 1 0 transfer from ram of 1-byte data (address is incremented by +1) to sfr (fixed address) 1 1 transfer from ram of 2-byte data (address is incremented by +2) to sfr (fixed address) by using these transfer modes, up to 1024 bytes of data can be consecutively transferred by using the serial interface, data resulting from a/d c onversion can be consecutively transferred, and port data can be scanned at fixed time intervals by using a timer. 15.4.3 termination of dma transfer when dbcn = 00h and dma transfer is completed, the dstn bit is automatically cleared to 0. an interrupt request (intdman) is generated and transfer is terminated. when the dstn bit is cleared to 0 to forcibly terminate dm a transfer, the dbcn and dra n registers hold the value when transfer is terminated. the interrupt request (intdman) is not ge nerated if transfer is forcibly terminated. remark n: dma channel number (n = 0, 1) chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 604 15.5 example of setting of dma controller 15.5.1 csi consecutive transmission a flowchart showing an example of setting for csi consecutive transmission is shown below. ? consecutive transmission of csi10 ? dma channel 0 is used for dma transfer. ? dma start source: intcsi10 (software trigger (stg0) only for the first start source) ? interrupt of csi10 is specified by ifc03 to if c00 (bits 3 to 0 of the dmc0 register) = 1000b. ? transfers ffb00h to ffbffh (256 bytes) of ram to fff10h of the transmit buffer (sio10) of csi. chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 605 figure 15-7. example of setting for csi consecuti ve transmission note the dst0 flag is automatically cleared to 0 when a dma transfer is completed. writing the den0 flag is enabled only when dst0 = 0. to terminate a dma transfer without waiting for occurrence of the interrupt of dma0 (intdma0), set dst0 to 0 and then den0 to 0 (for details, refer to 15.5.5 forced termination by software ). the fist trigger for consecutive transmi ssion is not started by the interrupt of csi. start it by a software trigger. csi transmission of the second time and onward is automatically executed. the dma interrupt (intdma0) is generated as soon as the last data has been writte n to the transmit buffer. at this point, the last data of csi is being transmitted. to start dma transfer again, therefore, wait until transfer of csi is completed. setting for csi transfer den0 = 1 dsa0 = 10h dra0 = fb00h dbc0 = 0100h dmc0 = 48h den0 = 0 dst0 = 1 stg0 = 1 start dma is started. intcsi10 occurs. reti end user program processing occurrence of intdma0 dst0 = 0 note dma0 transfer csi transmission hardware operation chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 606 15.5.2 consecutive capturing of a/d conversion results a flowchart of an example of setting for consecutivel y capturing a/d conversion results is shown below. ? consecutive capturing of a/d conversion results. ? dma channel 1 is used for dma transfer. ? dma start source: intad ? interrupt of a/d is specified by ifc13 to if c10 (bits 3 to 0 of the dmc1 register) = 1100b. ? transfers fff1eh and fff1fh (2 bytes) of the 10-bit a/d conversion result register to 512 bytes of ffce0h to ffedfh of ram. chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 607 figure 15-8. example of setting of cons ecutively capturing a/d conversion results note the dst1 flag is automatically cleared to 0 when a dma transfer is completed. writing the den1 flag is enabled only when dst1 = 0. to terminate a dma transfer without waiting for occurrence of the interrupt of dma1 (intdma1), set dst1 to 0 and then den1 to 0 (for details, refer to 15.5.5 forced termination by software ). hardware operation den1 = 1 dsa1 = 1eh dra1 = fce0h dbc1 = 0100h dmc1 = 2ch dst1 = 1 starting a/d conversion den1 = 0 reti end intdma1 occurs. dst1 = 0 note intad occurs. dma1 transfer start user program processing chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 608 15.5.3 uart consecutive r eception + ack transmission a flowchart illustrating an example of setting for uart consecutive reception + ack transmission is shown below. ? consecutively receives data fr om uart0 and outputs ack to p10 on completion of reception. ? dma channel 0 is used for dma transfer. ? dma start source: software trigger (dma transfer on occurrence of an interrupt is disabled.) ? transfers fff12h of uart receive data register 0 (rxd0) to 64 bytes of ffe00h to ffe3fh of ram. chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 609 den0 = 1 dsa0 = 12h dra0 = fe00h dbc0 = 0040h dmc0 = 00h den0 = 0 note setting for uart reception dst0 = 1 user program processing stg0 = 1 p10 = 1 p10 = 0 intsr0 occurs. intdma0 occurs. dst0 = 0 dma0 transfer reti hardware operation start end reti intsr0 interrupt routine figure 15-9. example of setting for uar t consecutive reception + ack transmission note the dst0 flag is automatically cleared to 0 when a dma transfer is completed. writing the den0 flag is enabled only when dst0 = 0. to terminate a dma transfer without waiting for occurrence of the interrupt of dma0 (intdma0), set dst0 to 0 and then den0 to 0 (for details, refer to 15.5.5 forced termination by software ). remark this is an example where a software trigger is used as a dma start source. if ack is not transmitted and if only data is consec utively received from uart, the uart reception end interrupt (intsr0) can be used to start dma for data reception. chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 610 starting dma transfer dwaitn = 0 dwaitn = 1 wait for 2 clocks p10 = 1 wait for 9 clocks p10 = 0 main program 15.5.4 holding dma transfer pending by dwaitn when dma transfer is started, transfer is performed while an in struction is executed. at this time, the operation of the cpu is stopped and delayed for the duration of 2 clo cks. if this poses a problem to the operation of the set system, a dma transfer can be held pen ding by setting dwaitn to 1. to output a pulse with a width of 10 cl ocks of the operating frequency from t he p10 pin, for example, the clock width increases to 12 if a dma transfer is started midway. in this case, the dma transfer can be held pending by setting dwaitn to 1. after setting dwaitn to 1, it takes two cl ocks until a dma transfer is held pending. figure 15-10. example of setting for ho lding dma transfer pending by dwaitn remarks 1. n: dma channel number (n = 0, 1) 2. 1 clock: 1/f clk (f clk : cpu clock) chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 611 dstn = 0 denn = 0 dstn = 0 ? no 2 clock wait yes dstn = 0 denn = 0 15.5.5 forced termination by software after dstn is set to 0 by software, it takes up to 2 clocks until a dma transfe r is actually stopped and dstn is set to 0. to forcibly terminate a dma transfer by software wit hout waiting for occurrence of the interrupt (intdman) of dman, therefore, perform either of the following processes. ? set dstn to 0 (use drcn = 80h to write with an 8-bit manipulation instruction) by software, confirm by polling that dstn has actually been cleared to 0, and then set denn to 0 (use drcn = 00h to write with an 8-bit manipulation instruction). ? set dstn to 0 (use drcn = 80h to write with an 8-bit manipulation instruction) by software and then set denn to 0 (use drcn = 00h to write with an 8-bit manipu lation instruction) two or more clocks after. figure 15-11. forced termination of dma transfer example 1 example 2 remarks 1. n: dma channel number (n = 0, 1) 2. 1 clock: 1/f clk (f clk : cpu clock) chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 612 15.6 cautions on using dma controller (1) priority of dma during dma transfer, a request from the other dma channel is held pend ing even if generated. the pending dma transfer is started after the ongoing dma transfer is completed. when the requests from either of the dma channels are successively generated in a short period note , they are successively transferred, and on completion of that, the requests from the other dm a channel are executed. in this case, one or tow instructions are executed between the fi rst dma transfer and next dma transfer. if two dma requests are generated at the same time, however, dma channel 0 takes priority over dma channel 1. if a dma request and an interrupt request are gener ated at the same time, the dma transfer takes precedence, and then interrupt servicing is executed. note the short period refers to a period of eight or fewe r cpu clocks. the relationship between the lengths of clock period and dma operations is as follows. 1 clock period: setting disabled dma request cannot be accepted. 2 to 4 clock period: dma transfer of the channel where requests are successively generated is executed. 5 to 8 clock period: whether dma transfer of the c hannel where requests are successively generated is executed or dma requests from the ot her channel are executed depends on the number of times cpu instructions are executed. (2) dma response time the response time of dma transfer is as follows. table 15-2. response time of dma transfer minimum time maximum time response time 4 clocks 10 clocks remark 1 clock: 1/f clk (f clk : cpu clock) in the following cases, however, dma transfer may be delayed further. the number of clocks by which dma transfer is delayed differs depending on the condition. ? instruction execution by ram ? execution of dma pending instruction chapter 15 dma controller preliminary user?s manual u19291ej1v0ud 613 (3) operation in standby mode the dma controller operates as follows in the standby mode. table 15-3. dma operation in standby mode status dma operation halt mode normal operation stop mode stops operation. if dma transfer and stop instruction execution contend, dma transfer may be damaged. therefore, stop dma before executing the stop instruction. (4) dma pending instruction even if a dma request is generated, dm a transfer is held pending immediately after the following instructions. ? call !addr16 ? call &!addr16 ? call !!addr20 ? call rp ? callt [addr5] ? brk ? bit manipulation instructions for registers if0l, if0h, if1l, if1h, if2l, if2h, mk0l, mk0h, mk1l, mk1h, mk2l, mk2h, pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12l, pr12h and psw each, and 8-bit manipulation instru ctions with operands including es registers (5) operation if address in general- purpose register area or other than those of internal ram area is specified the address indicated by dra0n is incremented during dma transfer. if the address is incremented to an address in the general-purpose register area or exceed s the area of the internal ram, the following operation is performed. z in mode of transfer from sfr to ram the data of that address is lost. z in mode of transfer from ram to sfr undefined data is transferred to sfr. in either case, malfunctioning may occur or damage may be done to the system. therefore, make sure that the address is within the internal ram area ot her than the general-purpose register area. internal ram general-purpose registers dma transfer enabled area fff00h ffeffh ffee0h ffedfh preliminary user?s manual u19291ej1v0ud 614 chapter 16 interrupt functions the number of interrupt sources differs, depending on the product. 78k0r/kc3-l (44-pin) 78k0r/kc3-l (48-pin) 78k0r/kd3-l 78k0r/ke3-l internal 9 9 9 9 maskable interrupts external 24 25 25 25 16.1 interrupt function types the following two types of inte rrupt functions are used. (1) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into four priority groups by setting the priority specification flag registers (pr00l, pr 00h, pr01l, pr01h, pr02l, pr10l, pr10h, pr11l, pr11h, pr12l). multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. if two or more interrupt requests, each having the same priority, are simultaneously generated, then they are processed according to the priority of vectored in terrupt servicing. for the priority order, see table 16-1 . a standby release signal is generated a nd stop and halt modes are released. external interrupt requests and internal interrupt requests are provided as maskable interrupts. (2) software interrupt this is a vectored interrupt generated by executing the brk instruction. it is acknowledged even when interrupts are disabled. the software interrupt does not undergo interrupt priority control. 16.2 interrupt sources and configuration interrupt sources include maskable interrupts and software inte rrupts. in addition, they also have up to five reset sources (see table 16-1 ). chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 615 table 16-1. interrupt source list (1/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 0 intwdti watchdog timer interval note 3 (75% of overflow time) 0004h 1 intlvi low-voltage detection note 4 internal 0006h (a) 2 intp0 0008h 3 intp1 000ah 4 intp2 000ch 5 intp3 000eh 6 intp4 0010h 7 intp5 pin input edge detection external 0012h (b) 8 intcmp0 cmp0 detection 0016h 9 intcmp1 cmp1 detection 0018h 10 intdma0 end of dma0 transfer 001ah 11 intdma1 end of dma1 transfer 001ch 12 intst0/ intcsi00 end of uart0 transmission/ end of csi00 communication 001eh 13 intsr0/ intcsi01 end of uart0 reception/ end of csi01 communication 0020h 14 intsre0 uart0 communication error occurrence 0022h 15 intst1 /intcsi10 /intiic10 end of uart1 transmission/ end of csi10 communication/ end of iic10 communication 0024h 16 intsr1 end of uart1 reception 0026h 17 intsre1 uart1 communication error occurrence 0028h 18 intiica note 5 end of iica communication 002ah 19 inttm00 end of timer channel 0 count or capture 002ch 20 inttm01 end of timer channel 1 count or capture 002eh 21 inttm02 end of timer channel 2 count or capture 0030h 22 inttm03 end of timer channel 3 count or capture 0032h maskable 23 intad end of a/d conversion internal 0034h (a) notes 1. the default priority determines t he sequence of interrupts if two or more maskable interrupts occur simultaneously. zero indicates the highest priority and 33 indicates the lowest priority. 2. basic configuration types (a) to (c) co rrespond to (a) to (c) in figure 16-1. 3. when bit 7 (wdtint) of the option byte (000c0h) is set to 1. 4. when bit 1 (lvimd) of the low-voltage det ection register (lvim) is cleared to 0. 5. 44-pin products of 78k0r/kc3-l is not provided. chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 616 table 16-1. interrupt source list (2/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 24 intrtc fixed-cycle sign al of real-time counter/alarm match detection 0036h 25 intrtci interval signal dete ction of real-time counter internal 0038h (a) 26 intkr key return signal detection external 003ah (b) 27 intmd end of division operation 0040h 28 inttm04 end of timer channel 4 count or capture 0042h 29 inttm05 end of timer channel 5 count or capture 0044h 30 inttm06 end of timer channel 6 count or capture 0046h 31 inttm07 end of timer channel 7 count or capture internal 0048h (a) 32 intp6 004ah maskable 33 intp7 pin input edge detection external 004ch (b) software ? brk execution of brk instruction ? 007eh (c) reset reset pin input poc power-on-clear lvi low-voltage detection note 3 wdt overflow of watchdog timer reset ? trap execution of illegal instruction note 4 ? 0000h ? notes 1. the default priority determines t he sequence of interrupts if two or more maskable interrupts occur simultaneously. zero indicates the highest priority and 33 indicates the lowest priority. 2. basic configuration types (a) to (c) co rrespond to (a) to (c) in figure 16-1. 3. when bit 1 (lvimd) of the low-voltage detection register (lvim) is set to 1. 4. when the instruction code in ffh is executed. reset by the illegal instruction ex ecution not issued by emul ation with the in-circuit emulator or on-chip debug emulator. chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 617 figure 16-1. basic configuration of interrupt function (a) internal maskable interrupt if mk ie pr1 isp1 pr0 isp0 internal bus interrupt request priority controller vector table address generator standby release signal (b) external maskable interrupt if mk ie pr1 isp1 pr0 isp0 internal bus external interrupt edge enable register (egp, egn) interrupt request edge detector priority controller vector table address generator standby release signal (c) software interrupt vector table address generator internal bus interrupt request if: interrupt request flag ie: interrupt enable flag isp0: in-service priority flag 0 isp1: in-service priority flag 1 mk: interrupt mask flag pr0: priority specification flag 0 pr1: priority specification flag 1 chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 618 16.3 registers controlling interrupt functions the following 6 types of registers are used to control the interrupt functions. ? interrupt request flag registers (if0l, if0h, if1l, if1h, if2l) ? interrupt mask flag registers (mk0l, mk0h, mk1l, mk1h, mk2l) ? priority specification flag registers (pr00l, pr 00h, pr01l, pr01h, pr02l, pr10l, pr10h, pr11l, pr11h, pr12l) ? external interrupt rising edge enable register (egp0) ? external interrupt falling edge enable register (egn0) ? program status word (psw) table 16-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 619 table 16-2. flags corresponding to interrupt request sources (1/2) interrupt request flag interrupt mask flag priority specification flag interrupt source register register register intwdti wdtiif wdtimk wdtipr0, wdtipr1 intlvi lviif lvimk lvipr0, lvipr1 intp0 pif0 pmk0 ppr00, ppr10 intp1 pif1 pmk1 ppr01, ppr11 intp2 pif2 pmk2 ppr02, ppr12 intp3 pif3 pmk3 ppr03, ppr13 intp4 pif4 pmk4 ppr04, ppr14 intp5 pif5 if0l pmk5 mk0l ppr05, ppr15 pr00l, pr10l intcmp0 cmpif0 cmpmk0 cmppr00, cmppr10 intcmp1 cmpif1 cmpmk1 cmppr01, cmppr11 intdma0 dmaif0 dmamk0 dmapr00, dmapr10 intdma1 dmaif1 dmamk1 dmapr01, dmapr11 intst0 note 1 stif0 note 1 stmk0 note 1 stpr00, stpr10 note 1 intcsi00 note 1 csiif00 note 1 csimk00 note 1 csipr000, csipr100 note 1 intsr0 note 2 srif0 note 2 srmk0 note 2 srpr00, srpr10 note 2 intcsi01 note 2 csiif01 note 2 csimk01 note 2 csipr001, csipr101 note 2 intsre0 sreif0 if0h sremk0 mk0h srepr00, srepr10 pr00h, pr10h notes 1. do not use uart0 and csi00 at t he same time because they share flags for the interrupt request sources. if one of the interrupt sources inst0 and intcsi 00 is generated, bit 5 of if0h is set to 1. bit 5 of mk0h, pr00h, and pr10h supports these two interrupt sources. 2. do not use uart0 and csi01 at t he same time because they share flags for the interrupt request sources. if one of the interrupt sources insr0 and intc si01 is generated, bit 6 of if0h is set to 1. bit 6 of mk0h, pr00h, and pr10h supports these two interrupt sources. chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 620 table 16-2. flags corresponding to interrupt request sources (2/2) interrupt request flag interrupt mask flag priority specification flag interrupt source register register register intst1 note 1 stif1 note 1 stmk1 note 1 stpr01, stpr11 note 1 intcsi10 note 1 csiif10 note 1 csimk10 note 1 csipr010, csipr110 note 1 intiic10 note 1 iicif10 note 1 iicmk10 note 1 iicpr010, iicpr110 note 1 intsr1 srif1 srmk1 srpr01, srpr11 intsre1 sreif1 sremk1 srepr01, srepr11 intiica note 2 iicaif note 2 iicamk note 2 iicapr0, iicapr1 note 2 inttm00 tmif00 tmmk00 tmpr000, tmpr100 inttm01 tmif01 tmmk01 tmpr001, tmpr101 inttm02 tmif02 tmmk02 tmpr002, tmpr102 inttm03 tmif03 if1l tmmk03 mk1l tmpr003, tmpr103 pr01l, pr11l intad adif admk adpr0, adpr1 intrtc rtcif rtcmk rtcpr0, rtcpr1 intrtci rtciif rtcimk rtcipr0, rtcipr1 intkr krif krmk krpr0, krpr1 intmd mdif mdmk mdpr0, mdpr1 inttm04 tmif04 if1h tmmk04 mk1h tmpr004, tmpr104 pr01h, pr11h inttm05 tmif05 tmmk05 tmpr005, tmpr105 inttm06 tmif06 tmmk06 tmpr006, tmpr106 inttm07 tmif07 tmmk07 tmpr007, tmpr107 intp6 pif6 pmk6 ppr06, ppr16 intp7 pif7 if2l pmk7 mk2l ppr07, ppr17 pr02l, pr12l notes 1. do not use uart1, csi10, and iic10 at the same time because they share flags for the interrupt request sources. if one of the interrupt sources intst1, in tcsi10, and intiic10 is generated, bit 0 of if1l is set to 1. bit 0 of mk1l, pr01l, and pr1 1l supports these three interrupt sources. 2. 44-pin products of 78k0r/kc3-l is not provided. chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 621 (1) interrupt request flag register s (if0l, if0h, if1l, if1h, if2l) the interrupt request flags are set to 1 when the correspo nding interrupt request is g enerated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknow ledgment of an interrupt request or upon reset signal generation. when an interrupt is acknowledged, the interrupt req uest flag is automatically cleared and then the interrupt routine is entered. if0l, if0h, if1l, if1h, and if 2l can be set by a 1-bit or 8-bit memory manipulation instruction. when if0l and if0h, and if1l and if1h are combined to form 16-bit regist ers if0 and if1, they can be set by a 16-bit memory manipulation instruction. using if2l as if2 can be set al so by using a 16-bit memory manipulation instruction. reset signal generation clears these registers to 00h. remark if an instruction that writes data to this register is execut ed, the number of instru ction execution clocks increases by 2 clocks. figure 16-2. format of interrupt request flag registers (if0l, if0h, if1l, if1h, if2l) (1/2) address: fffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l pif5 pif4 pif3 pif2 pif1 pif0 lviif wdtiif address: fffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> 0 if0h sreif0 srif0 csiif01 stif0 csiif00 dmaif1 dmaif0 cmpif1 cmpif0 0 address: fffe2h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if1l tmif03 tmif02 tmif01 tmif00 iicaif note sreif1 srif1 stif1 csiif10 iicif10 address: fffe3h after reset: 00h r/w symbol <7> <6> 5 4 <3> <2> <1> <0> if1h tmif04 mdif 0 0 krif rtciif rtcif adif address: fffd0h after reset: 00h r/w symbol 7 6 5 <4> <3> <2> <1> <0> if2l 0 0 0 pif7 pif6 tmif07 tmif06 tmif05 note 44-pin products of 78k0r/kc3-l is not provided. chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 622 figure 16-2. format of interrupt request flag registers (if0l, if0h, if1l, if1h, if2l) (2/2) xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status cautions 1. be sure to clear bit 0 of if0h, bits 4 and 5 of if1h, and bits 5 to 7 of if2l to 0. 2. when operating a timer, seri al interface, or a/d c onverter after standby release, operate it once after clearing the interrupt request flag. an interrupt request flag may be set by noise. 3. when manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (clr1) . when describing in c langua ge, use a bit manipulation instruction such as ?if0l.0 = 0;? or ?_asm(?clr1 if0l, 0?);? because the comp iled assembler must be a 1-bit memory manipulation instruction (clr1). if a program is described in c language us ing an 8-bit memory manipulation instruction such as ?if0l &= 0xfe;? and compiled, it b ecomes the assembler of three instructions. mov a, if0l and a, #0feh mov if0l, a in this case, even if th e request flag of another bit of the same interrupt request flag register (if0l) is set to 1 at the timi ng between ?mov a, if0l? and ?mov if0l, a?, the flag is cleared to 0 at ?mov if0l, a?. therefore, care mu st be exercised when using an 8-bit memory manipulation instruction in c language. chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 623 (2) interrupt mask flag register s (mk0l, mk0h, mk1l, mk1h, mk2l) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. mk0l, mk0h, mk1l, mk1h, and mk2l can be set by a 1-bi t or 8-bit memory manipulation instruction. when mk0l and mk0h, and mk1l and mk1h are combined to form 16- bit registers mk0 and mk1, they can be set by a 16-bit memory manipulation instruction. using mk 2l as mk2 can be set also by using a 16-bit memory manipulation instruction. reset signal generation sets these registers to ffh. remark if an instruction that writes data to this register is execut ed, the number of instru ction execution clocks increases by 2 clocks. figure 16-3. format of interrupt mask flag registers (mk0l, mk0h, mk1l, mk1h, mk2l) address: fffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk wdtimk address: fffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> 0 mk0h sremk0 srmk0 csimk01 stmk0 csimk00 dmamk1 dmamk0 cmpmk1 cmpmk0 1 address: fffe6h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk1l tmmk03 tmmk02 tmmk01 tmmk00 iicamk note sremk1 srmk1 stmk1 csimk10 iicmk10 address: fffe7h after reset: ffh r/w symbol <7> <6> 5 4 <3> <2> <1> <0> mk1h tmmk04 mdmk 1 1 krmk rtcimk rtcmk admk address: fffd4h after reset: ffh r/w symbol 7 6 5 <4> <3> <2> <1> <0> mk2l 1 1 1 pmk7 pmk6 tmmk07 tmmk06 tmmk05 xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled note 44-pin products of 78k0r/kc3-l is not provided. caution be sure to set bit 0 of mk0h, bits 4 an d 5 of mk1h, and bits 5 to 7 of mk2l to 1. chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 624 (3) priority specification flag registers (pr00l, pr 00h, pr01l, pr01h, pr02l, pr10l, pr10h, pr11l, pr11h, pr12l) the priority specification flag regist ers are used to set the corresponding maskable interrupt priority level. a priority level is set by using the pr0xy and pr1xy registers in combination (xy = 0l, 0h, 1l, 1h, or 2l). pr00l, pr00h, pr01l, pr01h, pr02l, pr10l, pr10h, pr 11l, pr11h, and pr12l can be set by a 1-bit or 8- bit memory manipulation instruction. if pr00l and pr00h, pr01l and pr01h, pr10l and pr10h, and pr11l and pr11h are combined to form 16-bit registers pr00, pr01, pr10, and pr11, they can be set by a 16-bit memory manipulation instruction. using pr02l as pr 02 and pr12l as pr12 can be set also by using a 16-bit memory manipulation instruction. reset signal generation sets these registers to ffh. remark if an instruction that writes data to this register is execut ed, the number of instru ction execution clocks increases by 2 clocks. figure 16-4. format of priority specification flag registers (pr00l, pr00h, pr01l, pr01h, pr02l, pr 10l, pr10h, pr11l, pr11h, pr12l) (1/2) address: fffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr00l ppr05 ppr04 ppr03 ppr02 ppr01 ppr00 lvipr0 wdtipr0 address: fffech after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr10l ppr15 ppr14 ppr13 ppr12 ppr11 ppr10 lvipr1 wdtipr1 address: fffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> 0 pr00h srepr00 srpr00 csipr001 stpr00 csipr000 dmapr01 dmapr00 cmppr01 cmppr00 1 address: fffedh after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> 0 pr10h srepr10 srpr10 csipr101 stpr10 csipr100 dmapr11 dmapr10 cmppr11 cmppr10 1 chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 625 figure 16-4. format of priority specification flag registers (pr00l, pr00h, pr01l, pr01h, pr02l, pr 10l, pr10h, pr11l, pr11h, pr12l) (2/2) address: fffeah after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr01l tmpr003 tmpr002 tmpr001 tmpr000 iicapr0 note srepr01 srpr01 stpr01 csipr010 iicpr010 address: fffeeh after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr11l tmpr103 tmpr102 tmpr101 tmpr100 iicapr1 note srepr11 srpr11 stpr11 csipr110 iicpr110 address: fffebh after reset: ffh r/w symbol <7> <6> 5 4 <3> <2> <1> <0> pr01h tmpr004 mdpr0 1 1 krpr0 rtcipr0 rtcpr0 adpr0 address: fffefh after reset: ffh r/w symbol <7> <6> 5 4 <3> <2> <1> <0> pr11h tmpr104 mdpr1 1 1 krpr1 rtcipr1 rtcpr1 adpr1 address: fffd8h after reset: ffh r/w symbol 7 6 5 <4> <3> <2> <1> <0> pr02l 1 1 1 ppr07 ppr06 tmpr007 tmpr006 tmpr005 address: fffdch after reset: ffh r/w symbol 7 6 5 <4> <3> <2> <1> <0> pr12l 1 1 1 ppr17 ppr16 tmpr107 tmpr106 tmpr105 xxpr1x xxpr0x priority level selection 0 0 specify level 0 (high priority level) 0 1 specify level 1 1 0 specify level 2 1 1 specify level 3 (low priority level) note 44-pin products of 78k0r/kc3-l is not provided. caution be sure to set bit 0 of pr00h and pr10h, bits 4 and 5 of pr 01h and pr11h, and bits 5 to 7 of pr02l and pr12l to 1. chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 626 (4) external interrupt rising edge en able register (egp0), external inte rrupt falling edge enable register (egn0) these registers specify the valid edge for intp0 to intp7. egp0 and egn0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 16-5. format of external interrupt rising edge enable register (egp0) and external interrupt falling edge enable register (egn0) address: fff38h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp0 egp7 egp6 egp5 egp4 egp3 egp2 egp1 egp0 address: fff39h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn0 egn7 egn6 egn5 egn4 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 7) 0 0 edge detection disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges table 16-3 shows the ports corresponding to egpn and egnn. table 16-3. ports correspo nding to egpn and egnn detection enable register edge detection port interrupt request signal egp0 egn0 p120 intp0 egp1 egn1 p31 intp1 egp2 egn2 p32 intp2 egp3 egn3 p80 intp3 egp4 egn4 p70 intp4 egp5 egn5 p71 intp5 egp6 egn6 p72 intp6 egp7 egn7 p82 intp7 caution select the port mode by clearing eg pn and egnn to 0 because an edge may be detected when the external interrupt func tion is switched to the port function. remark n = 0 to 7 chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 627 (5) program status word (psw) the program status word is a register used to hold the instruction exec ution result and the current status for an interrupt request. the ie flag that sets maskable in terrupt enable/disable and the isp0 and isp1 flags that controls multiple interrupt servicing are mapped to the psw. besides 8-bit read/write, this register can carry out op erations using bit manipulation instructions and dedicated instructions (ei and di). when a vect ored interrupt request is acknowledged, if the brk instruction is executed, the contents of the psw are aut omatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of t he acknowledged interrupt are transferred to the isp0 and isp1 flags. the psw content s are also saved into the stack with the push psw instruction. they are restored from the stack with the reti, re tb, and pop psw instructions. reset signal generation sets psw to 06h. figure 16-6. configuration of program status word <7> ie <6> z <5> rbs1 <4> ac <3> rbs0 <2> isp1 <1> isp0 0 cy psw after reset 06h isp1 0 0 1 1 enables interrupt of level 0 (while interrupt of level 1 or 0 is being serviced). enables interrupt of level 0 and 1 (while interrupt of level 2 is being serviced). enables interrupt of level 0 to 2 (while interrupt of level 3 is being serviced). enables all interrupts (waits for acknowledgment of an interrupt). ie 0 1 disabled enabled priority of interrupt currently being serviced interrupt request acknowledgment enable/disable used when normal instruction is executed isp0 0 1 0 1 chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 628 16.4 interrupt servicing operations 16.4.1 maskable interrupt request acknowledgment a maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cleared to 0. a vectored interrupt request is acknowledged if interrupts are in the interrupt enabled stat e (when the ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request. the times from generation of a maskable interrupt request until vectored interr upt servicing is performed are listed in table 16-4 below. for the interrupt request acknowledgment timing, see figures 16-8 and 16-9 . table 16-4. time from generation of maskable inte rrupt until servicing minimum time maximum time note servicing time 9 clocks 14 clocks note if an interrupt request is generated just before the ret instruction, the wait time becomes longer. remark 1 clock: 1/f clk (f clk : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledge d first. if two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. an interrupt request that is held pending is a cknowledged when it becomes acknowledgeable. figure 16-7 shows the interrupt request acknowledgment algorithm. if a maskable interrupt request is acknowledged, the content s are saved into the stacks in the order of psw, then pc, the ie flag is reset (0), and the contents of the pr iority specification flag corresponding to the acknowledged interrupt are transferred to the isp1 and isp0 flags. the ve ctor table data determined for each interrupt request is the loaded into the pc and branched. restoring from an interrupt is possible by using the reti instruction. chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 629 figure 16-7. interrupt request acknowledgment processing algorithm yes no yes no yes no no yes no ie = 1? vectored interrupt servicing start if = 1? mk = 0? ( pr 1, pr 0) (isp1, isp0) yes (interrupt request generation) no (low priority) interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending higher priority than other interrupt requests simultaneously generated? higher default priority note than other interrupt requests simultaneously generated? if: interrupt request flag mk: interrupt mask flag pr0: priority specification flag 0 pr1: priority specification flag 1 ie: flag that controls acknowledgment of mask able interrupt request (1 = enable, 0 = disable) isp0, isp1: flag that indicates the priority leve l of the interrupt currently being serviced (see figure 16-6 ) note for the default priority, refer to table 16-1 interrupt source list . chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 630 figure 16-8. interrupt request ac knowledgment timing (minimum time) 9 clocks instruction instruction cpu processing if 6 clocks psw and pc saved, jump to interrupt servicing interrupt servicing program remark 1 clock: 1/f clk (f clk : cpu clock) figure 16-9. interrupt request ac knowledgment timing (maximum time) 14 clocks instruction ret instruction cpu processing if 6 clocks 6 clocks psw and pc saved, jump to interrupt servicing interrupt servicing program remark 1 clock: 1/f clk (f clk : cpu clock) chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 631 16.4.2 software interrupt request acknowledgment a software interrupt request is acknowledged by brk instructi on execution. software interrupts cannot be disabled. if a software interrupt request is ackno wledged, the cont ents are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (0), and the contents of the vect or table (0007eh, 0007fh) are loaded into the pc and branched. restoring from a software interrupt is possi ble by using the retb instruction. caution do not use the reti instruction fo r restoring from the software interrupt. 16.4.3 multiple interrupt servicing multiple interrupt servicing occurs when another interrupt re quest is acknowledged during execution of an interrupt. multiple interrupt servicing does not occur unless the inte rrupt request acknowledgment enabled state is selected (ie = 1). when an interrupt request is acknowledged, inte rrupt request acknowledgment becomes disabled (ie = 0). therefore, to enable multiple interrupt servicing, it is necessary to set (1) the ie flag with the ei instruction during interrupt servicing to enable interrupt acknowledgment. moreover, even if interrupts are enabled, multiple interr upt servicing may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for multiple interrupt servicing. in the interrupt enabled state, if an in terrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for mu ltiple interrupt servicing. if an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. inte rrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower prio rity are held pending. when servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. table 16-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and figure 16-10 shows multiple interrupt servicing examples. chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 632 table 16-5. relationship between interrupt requests enabled for multiple interrupt servicing during interrupt servicing maskable interrupt request priority level 0 (pr = 00) priority level 1 (pr = 01) priority level 2 (pr = 10) priority level 3 (pr = 11) multiple interrupt request interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 ie = 1 ie = 0 ie = 1 ie = 0 software interrupt request isp1 = 0 isp0 = 0 { { isp1 = 0 isp0 = 1 { { { isp1 = 1 isp0 = 0 { { { { maskable interrupt isp1 = 1 isp0 = 1 { { { { { software interrupt { { { { { remarks 1. { : multiple interrupt servicing enabled 2. : multiple interrupt servicing disabled 3. isp0, isp1, and ie are flags contained in the psw. isp1 = 0, isp0 = 0: an interrupt of level 1 or level 0 is being serviced. isp1 = 0, isp0 = 1: an interrupt of level 2 is being serviced. isp1 = 1, isp0 = 0: an interrupt of level 3 is being serviced. isp1 = 1, isp0 = 1: wait for an interrupt acknowledgment. ie = 0: interrupt request acknowledgment is disabled. ie = 1: interrupt request acknowledgment is enabled. 4. pr is a flag contained in pr00l, pr00h, pr 01l, pr01h, pr02l, pr10 l, pr10h, pr11l, pr11h, and pr12l. pr = 00: specify level 0 with pr1 = 0, pr0 = 0 (higher priority level) pr = 01: specify level 1 with pr1 = 0, pr0 = 1 pr = 10: specify level 2 with pr1 = 1, pr0 = 0 pr = 11: specify level 3 with pr1 = 1, pr0 = 1 (lower priority level) chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 633 figure 16-10. examples of multip le interrupt se rvicing (1/2) example 1. multiple inte rrupt servicing occurs twice main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 11) intyy (pr = 10) intzz (pr = 01) ie = 0 ie = 0 ie = 0 ie = 1 ie = 1 ie = 1 during servicing of interrupt intxx, two interrupt re quests, intyy and intzz, are acknowledged, and multiple interrupt servicing takes place. before each interrupt re quest is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledgment. example 2. multiple interrupt servicing does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 10) intyy (pr = 11) ei reti ie = 0 ie = 0 ei 1 instruction execution reti ie = 1 ie = 1 interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and mu ltiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 00: specify level 0 with pr1 = 0, pr0 = 0 (higher priority level) pr = 01: specify level 1 with pr1 = 0, pr0 = 1 pr = 10: specify level 2 with pr1 = 1, pr0 = 0 pr = 11: specify level 3 with pr1 = 1, pr0 = 1 (lower priority level) ie = 0: interrupt request acknowledgment is disabled ie = 1: interrupt request acknowledgment is enabled. chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 634 figure 16-10. examples of multip le interrupt se rvicing (2/2) example 3. multiple interrupt servicing do es not occur because inte rrupts are not enabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 11) intyy (pr = 00) ie = 0 ie = 0 ie = 1 ie = 1 interrupts are not enabled during servicing of interrupt int xx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and multiple interrupt serv icing does not take place. the intyy interrupt request is held pending, and is acknowledged following ex ecution of one main processing instruction. pr = 00: specify level 0 with pr1 = 0, pr0 = 0 (higher priority level) pr = 01: specify level 1 with pr1 = 0, pr0 = 1 pr = 10: specify level 2 with pr1 = 1, pr0 = 0 pr = 11: specify level 3 with pr1 = 1, pr0 = 1 (lower priority level) ie = 0: interrupt request acknowledgment is disabled ie = 1: interrupt request acknowledgment is enabled. chapter 16 interrupt functions preliminary user?s manual u19291ej1v0ud 635 16.4.4 interrupt request hold there are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the ne xt instruction. these instructions (interrupt request hol d instructions) are listed below. ? mov psw, #byte ? mov psw, a ? mov1 psw. bit, cy ? set1 psw. bit ? clr1 psw. bit ? retb ? reti ? pop psw ? btclr psw. bit, $addr8 ? ei ? di ? skc ? sknc ? skz ? sknz ? manipulation instructions for t he if0l, if0h, if1l, if1h, if2l, mk 0l, mk0h, mk1l, mk1h, mk2l, pr00l, pr00h, pr01l, pr01h, pr02l, pr10l, pr10h, pr11l, pr11h, and pr12l registers caution the brk instruction is not one of the above-listed interrupt re quest hold instructions. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared. therefore, even if a maskable interrupt re quest is generated during execution of the brk instruction, the interrupt re quest is not acknowledged. figure 16-11 shows the timing at which interrupt requests are held pending. figure 16-11. interrupt request hold instruction n instruction m psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other t han interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (interrupt request). preliminary user?s manual u19291ej1v0ud 636 chapter 17 key interrupt function the number of key interrupt input c hannels differs, depending on the product. 78k0r/kc3-l 78k0r/kd3-l 78k0r/ke3-l key interrupt input channels 6 ch 8 ch 17.1 functions of key interrupt a key interrupt (intkr) can be generated by setting t he key return mode register (krm) and inputting a falling edge to the key interrupt input pins (kr0 to kr7). table 17-1. assignment of k ey interrupt detection pins flag description krm0 controls kr0 signal in 1-bit units. krm1 controls kr1 signal in 1-bit units. krm2 controls kr2 signal in 1-bit units. krm3 controls kr3 signal in 1-bit units. krm4 controls kr4 signal in 1-bit units. krm5 controls kr5 signal in 1-bit units. krm6 controls kr6 signal in 1-bit units. krm7 controls kr7 signal in 1-bit units. 17.2 configuration of key interrupt the key interrupt includes the following hardware. table 17-2. configuration of key interrupt item configuration control register key return mode register (krm) remark kr0 to kr5: 78k0r/kc3-l kr0 to kr7: 78k0r/kd3-l and 78k0r/ke3-l chapter 17 key interrupt function preliminary user?s manual u19291ej1v0ud 637 figure 17-1. block diag ram of key interrupt intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0 remark kr0 to kr5: 78k0r/kc3-l kr0 to kr7: 78k0r/kd3-l and 78k0r/ke3-l chapter 17 key interrupt function preliminary user?s manual u19291ej1v0ud 638 17.3 register controlling key interrupt (1) key return mode register (krm) this register controls the krm0 to krm7 bits using the kr0 to kr7 signals, respectively. krm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 17-2. format of key return mode register (krm) krm7 does not detect key interrupt signal detects key interrupt signal krmn 0 1 key interrupt mode control krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 address: fff37h after reset: 00h r/w symbol 765432 0 cautions 1. if any of the krm0 to krm7 bits used is set to 1, set bits 0 to 7 (pu70 to pu77) of the corresponding pull-up resistor register 7 (pu7) to 1. 2. if krm is changed, the interrupt request flag may be set. therefore, disable interrupts and then change the krm register. clear the in terrupt request flag and enable interrupts. 3. the bits not used in the key inte rrupt mode can be used as normal ports. remarks 1. n = 0 to 7 2. kr0 to kr5: 78k0r/kc3-l kr0 to kr7: 78k0r/kd3-l and 78k0r/ke3-l preliminary user?s manual u19291ej1v0ud 639 chapter 18 standby function 18.1 standby function and configuration 18.1.1 standby function the standby function reduces the operat ing current of the system, and the fo llowing two modes are available. (1) halt mode halt instruction execution se ts the halt mode. in the halt mode, the cpu operation clock is stopped. if the high-speed system clock oscillator, internal high-speed oscillator, 20 mhz internal high-speed oscillator, or subsystem clock oscillator is operating before the halt mode is set, oscillation of each clock continues. in this mode, the operating current is not decreased as much as in the stop mode, but the halt mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations frequently. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the high-speed system clock oscillator and internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the cpu operating current. because this mode can be cleared by an interrupt reques t, it enables intermittent operations to be carried out. however, because a wait time is required to secure th e oscillation stabilization time after the stop mode is released when the x1 clock is selected, select the halt mode if it is necessary to start processing immediately upon interrupt request generation. in either of these two modes, all the contents of registers, flags and data me mory just before the standby mode is set are held. the i/o port output latches an d output buffer statuses are also held. cautions 1. the stop mode can be used only when the cpu is operating on the main system clock. the stop mode cannot be set while the cpu ope rates with the subsystem clock. the halt mode can be used when the cpu is operating on either the main system clock or the subsystem clock. 2. when shifting to the stop mode, be su re to stop the peripher al hardware operation operating with main system clock be fore executing stop instruction. 3. the following sequence is r ecommended for operating current reduction of the a/d converter when the standby function is used: first cl ear bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0 to stop the a/d conversion opera tion, and then execute the stop instruction. 4. the following sequence is recommended for operating current reduct ion of the comparator when the standby function is used: first clea r bit 7 (cnen) of the comparator n control register (cnctl) and bit 7 (cnvre) of the comp arator n internal refe rence voltage selection register to 0 to stop the comparator operati on, and then execute the stop instruction. 5. the following sequence is recomme nded for operating current reduction of the programmable gain amplifier when the standby function is used: first clear bit 7 (oaen) of the programmable gain amplifier control register (oam) to 0 to stop the programmable gain amplifier operation, and then execute the stop instruction. remark n = 0, 1 chapter 18 standby function preliminary user?s manual u19291ej1v0ud 640 cautions 6. it can be selected by the option byte whether the internal low- speed oscillator continues oscillating or stops in the ha lt or stop mode. for details , see chapter 23 option byte. 7. the stop instruction cannot be executed when the cpu operates on the 20 mhz internal high-speed oscillation clock. be sure to execute the stop in struction after shifting to internal high-speed oscillation clock operation. 18.1.2 registers controlling standby function the standby function is controlled by the following two registers. ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) remark for the registers that start, st op, or select the clock, see chapter 5 clock generator . chapter 18 standby function preliminary user?s manual u19291ej1v0ud 641 (1) oscillation stabilization time c ounter status register (ostc) this is the register that indicates the count status of the x1 clock osci llation stabilization time counter. the x1 clock oscillation stabilization time can be checked in the following case. ? if the x1 clock starts oscillation while the internal high -speed oscillation clock or s ubsystem clock is being used as the cpu clock. ? if the stop mode is entered and then re leased while the internal high-speed oscillation clock is being used as the cpu clock with the x1 clock oscillating. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lv i, wdt, and executing an illegal instruction), the stop instruction and mstop (bit 7 of csc regist er) = 1 clear this register to 00h. figure 18-1. format of oscillation stabilizati on time counter status register (ostc) address: fffa2h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc most 8 most 9 most 10 most 11 most 13 most 15 most 17 most 18 oscillation stabilization time status most 8 most 9 most 10 most 11 most 13 most 15 most 17 most 18 f x = 10 mhz f x = 20 mhz 0 0 0 0 0 0 0 0 2 8 /f x max. 25.6 s max. 12.8 s max. 1 0 0 0 0 0 0 0 2 8 /f x min. 25.6 s min. 12.8 s min. 1 1 0 0 0 0 0 0 2 9 /f x min. 51.2 s min. 25.6 s min. 1 1 1 0 0 0 0 0 2 10 /f x min. 102.4 s min. 51.2 s min. 1 1 1 1 0 0 0 0 2 11 /f x min. 204.8 s min. 102.4 s min. 1 1 1 1 1 0 0 0 2 13 /f x min. 819.2 s min. 409.6 s min. 1 1 1 1 1 1 0 0 2 15 /f x min. 3.27 ms min. 1.64 ms min. 1 1 1 1 1 1 1 0 2 17 /f x min. 13.11 ms min. 6.55 ms min. 1 1 1 1 1 1 1 1 2 18 /f x min. 26.21 ms min. 13.11 ms min. cautions 1. after the above ti me has elapsed, the bits are set to 1 in order from most8 and remain 1. 2. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. 3. the x1 clock oscillation stabilizatio n wait time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 18 standby function preliminary user?s manual u19291ej1v0ud 642 (2) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillation stabilization wait time when the stop mode is released. when the x1 clock is selected as the cpu clock, the operation waits for the time set using osts after the stop mode is released. when the internal high-speed oscillation clock is selected as the cpu clock, confirm with ostc that the desired oscillation stabilization time has elaps ed after the stop mode is released. the oscillation stabilization time can be checked up to the time set using ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 07h. figure 18-2. format of oscillation stabiliz ation time select register (osts) address: fffa3h after reset: 07h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 oscillation stabilization time selection osts2 osts1 osts0 f x = 10 mhz f x = 20 mhz 0 0 0 2 8 /f x 25.6 s setting prohibited 0 0 1 2 9 /f x 51.2 s 25.6 s 0 1 0 2 10 /f x 102.4 s 51.2 s 0 1 1 2 11 /f x 204.8 s 102.4 s 1 0 0 2 13 /f x 819.2 s 409.6 s 1 0 1 2 15 /f x 3.27 ms 1.64 ms 1 1 0 2 17 /f x 13.11 ms 6.55 ms 1 1 1 2 18 /f x 26.21 ms 13.11 ms cautions 1. to set the stop mode when the x1 cl ock is used as the cpu cl ock, set osts before executing the stop instruction. 2. setting the oscillation stabilization time to 20 s or less is prohibited. 3. before changing the setting of the osts regi ster, confirm that the count operation of the ostc register is completed. 4. do not change the value of the osts regi ster during the x1 clock oscillation stabilization time. 5. the oscillation stabilization time counter c ounts up to the oscillation stabilization time set by osts. if the stop mode is entered and then released while th e internal high-speed oscillation clock is being used as the cpu clo ck, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. 6. the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 18 standby function preliminary user?s manual u19291ej1v0ud 643 18.2 standby function operation 18.2.1 halt mode (1) halt mode the halt mode is set by executing t he halt instruction. halt mode can be set regardless of whether the cpu clock before the setting was the high-speed system clock, internal high-speed oscillation clock, 20 mhz internal high-speed oscillation clock, or subsystem clock. the operating statuses in t he halt mode are shown below. chapter 18 standby function preliminary user?s manual u19291ej1v0ud 644 table 18-1. operating statuses in halt mode (1/2) when halt instruction is executed while cpu is operating on main system clock halt mode setting item when cpu is operating on internal high-speed oscillation clock (f ih ) or 20 mhz internal high-speed oscillation clock (f ih20 ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f ex ) system clock clock supply to the cpu is stopped f ih , f ih20 operation continues (cannot be stopped) status before halt mode was set is retained f x operation continues (cannot be stopped) cannot operate main system clock f ex cannot operate operation continues (cannot be stopped) subsystem clock f xt status before halt mode was set is retained status before halt mode was set is retained f il set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: oscillates ? wton = 1 and wdstbyon = 0: stops cpu operation stopped flash memory operation stopped ram the value is retained port (latch) status before halt mode was set is retained timer array unit taus real-time counter (rtc) operable watchdog timer set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: operates ? wton = 1 and wdstbyon = 0: stops clock output/buzzer output note a/d converter programmable gain amplifier comparator serial array unit (sau) serial interface (iica) note multiplier/divider dma controller power-on-clear function low-voltage detection function external interrupt key interrupt function operable note this is not mounted onto 44-pin products of the 78k0r/kc3-l. remark f ih : internal high-speed oscillation clock f ih20 : 20 mhz internal high-speed oscillation clock f x : x1 clock f ex : external main system clock f xt : xt1 clock f il : internal low-speed oscillation clock chapter 18 standby function preliminary user?s manual u19291ej1v0ud 645 table 18-1. operating statuses in halt mode (2/2) note this is not mounted onto 44-pin products of the 78k0r/kc3-l. remark f ih : internal high-speed oscillation clock f ih20 : 20 mhz internal high-speed oscillation clock f x : x1 clock f ex : external main system clock f xt : xt1 clock f il : internal low-speed oscillation clock when halt instruction is executed while cpu is operating on subsystem clock halt mode setting item when cpu is operating on xt1 clock (f xt ) system clock clock supply to the cpu is stopped f ih , f ih20 f x main system clock f ex status before halt mode was set is retained subsystem clock f xt operation continues (cannot be stopped) f il set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: oscillates ? wton = 1 and wdstbyon = 0: stops cpu operation stopped flash memory operation stopped (wait st ate in low-current consumption mode) ram the value is retained port (latch) status before halt mode was set is retained timer array unit taus real-time counter (rtc) operable watchdog timer set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: operates ? wton = 1 and wdstbyon = 0: stops clock output/buzzer output note operable a/d converter cannot operate programmable gain amplifier comparator serial array unit (sau) operable serial interface (iica) note cannot operate multiplier/divider dma controller power-on-clear function low-voltage detection function external interrupt key interrupt function operable chapter 18 standby function preliminary user?s manual u19291ej1v0ud 646 (2) halt mode release the halt mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 18-3. halt mode release by interrupt request generation halt instruction wait operating mode halt mode operating mode oscillation high-speed system clock, internal high-speed oscillation clock, 20 mhz internal high-speed oscillation clock, or subsystem clock status of cpu standby release signal interrupt request remark the broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. chapter 18 standby function preliminary user?s manual u19291ej1v0ud 647 (b) release by reset signal generation when the reset signal is generated, halt mode is re leased, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 18-4. halt mode release by reset (1) when high-speed system clock is used as cpu clock halt instruction reset signal high-speed system clock (x1 oscillation) halt mode reset period oscillates oscillation stopped oscillates status of cpu normal operation (high-speed system clock) oscillation stabilization time (check by using ostc register) normal operation (internal high-speed oscillation clock) oscillation stopped starting x1 oscillation is specified by software. reset processing (about 2.1 to 5.8 ms) (2) when internal high-speed oscilla tion clock or 20 mhz internal high-speed oscillation clo ck is used as cpu clock halt instruction reset signal internal high-speed oscillation clock or 20 mhz internal high-speed oscillation clock normal operation (internal high-speed oscillation clock or 20 mhz internal high-speed oscillation clock) halt mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu wait for oscillation accuracy stabilization reset processing (about 2.1 to 5.8 ms) (3) when subsystem clo ck is used as cpu clock halt instruction reset signal subsystem clock (xt1 oscillation) normal operation (subsystem clock) halt mode reset period normal operation mode (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu oscillation stopped starting xt1 oscillation is specified by software. reset processing (about 2.1 to 5.8 ms) remark f x : x1 clock oscillation frequency chapter 18 standby function preliminary user?s manual u19291ej1v0ud 648 18.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by executing t he stop instruction, and it can be se t only when the cpu clock before the setting was the internal high-speed oscillation clock, x1 clock, or external main system clock. cautions 1. because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction and the system returns to the operating mode as soon as the wait time set us ing the oscillation stabilization time select register (osts) has elapsed. 2. the stop instruction cannot be executed when the cpu operates on the 20 mhz internal high-speed oscillation clock. be sure to execute the stop in struction after shifting to internal high-speed oscillation clock operation. the operating statuses in t he stop mode are shown below. chapter 18 standby function preliminary user?s manual u19291ej1v0ud 649 table 18-2. operating statuses in stop mode when stop instruction is executed while cpu is operating on main system clock stop mode setting item when cpu is operating on internal high-speed oscillation clock (f ih ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f ex ) system clock clock supply to the cpu is stopped f ih f x main system clock f ex stopped subsystem clock f xt status before stop mode was set is retained f il set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: oscillates ? wton = 1 and wdstbyon = 0: stops cpu operation stopped flash memory operation stopped ram the value is retained port (latch) status before stop mode was set is retained timer array unit taus operation disabled real-time counter (rtc) operable watchdog timer set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: operates ? wton = 1 and wdstbyon = 0: stops clock output/buzzer output note operable only when subs ystem clock is selected as the count clock a/d converter programmable gain amplifier comparator serial array unit (sau) operation disabled serial interface (iica) note wakeup by address match operable multiplier/divider dma controller operation disabled power-on-clear function low-voltage detection function external interrupt key interrupt function operable note this is not mounted onto 44-pin products of the 78k0r/kc3-l. remark f ih : internal high-speed oscillation clock f x : x1 clock f ex : external main system clock f xt : xt1 clock f il : internal low-speed oscillation clock chapter 18 standby function preliminary user?s manual u19291ej1v0ud 650 cautions 1. to use the peripheral ha rdware that stops operation in the stop mode, and the peripheral hardware for which the clock that stops oscillati ng in the stop mode after the stop mode is released, restart the peripheral hardware. 2. to stop the internal low-speed oscillation clo ck in the stop mode, use an option byte to stop the watchdog timer operation in the halt/stop m ode (bit 0 (wdstbyon) of 000c0h = 0), and then execute the stop instruction. 3. to shorten oscillation stabiliz ation time after the stop mode is released when the cpu operates with the high-speed system clock (x1 oscillation) , temporarily switch the cpu clock to the internal high-speed oscillation cl ock before the next execution of the stop instruction. before changing the cpu clock from the internal high-speed oscillation clock to the hi gh-speed system clock (x1 oscillation) after the stop mode is released, check the oscilla tion stabilization time with the oscillation stabilization time counter status register (ostc). 4. the stop instruction canno t be executed when the cpu operat es on the 20 mhz internal high- speed oscillation clock. be sure to execute the stop instruction after shifting to internal high- speed oscillation clock operation. (2) stop mode release the stop mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. after the oscillation stabilization time has elapsed, if interrupt acknowledg ment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 18-5. stop mode release by interrupt request generation (1/2) (1) when high-speed system clock (x 1 oscillation) is used as cpu clock normal operation (high-speed system clock) normal operation (high-speed system clock) oscillates oscillates stop instruction stop mode wait (set by osts) standby release signal oscillation stabilization wait (halt mode status) oscillation stopped high-speed system clock (x1 oscillation) status of cpu oscillation stabilization time (set by osts) interrupt request remark the broken lines indicate the case when the inte rrupt request that has re leased the standby mode is acknowledged. chapter 18 standby function preliminary user?s manual u19291ej1v0ud 651 figure 18-5. stop mode release by interrupt request generation (2/2) (2) when high-speed system clock (external clock in put) is used as cpu clock interrupt request stop instruction standby release signal status of cpu high-speed system clock (external clock input) oscillates normal operation (high-speed system clock) stop mode oscillation stopped oscillates normal operation (high-speed system clock) wait (2 clocks) supply of the clock is stopped (about 23.3 to 30.7 s) (3) when internal high-speed osc illation clock is used as cpu clock standby release signal status of cpu internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) oscillates stop mode oscillation stopped wait for oscillation accuracy stabilization interrupt request stop instruction normal operation (internal high-speed oscillation clock) oscillates wait (1 clock) supply of the clock is stopped (about 23.3 to 30.7 s) remark the broken lines indicate the case when the inte rrupt request that has re leased the standby mode is acknowledged. chapter 18 standby function preliminary user?s manual u19291ej1v0ud 652 (b) release by reset signal generation when the reset signal is generated, stop mode is released, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 18-6. stop mode release by reset (1) when high-speed system clock is used as cpu clock stop instruction reset signal high-speed system clock (x1 oscillation) normal operation (high-speed system clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu oscillation stabilization time (check by using ostc register) oscillation stopped starting x1 oscillation is specified by software. oscillation stopped reset processing (about 2.1 to 5.8 ms) (2) when internal high-speed osc illation clock is used as cpu clock stop instruction reset signal internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped status of cpu oscillates oscillation stopped wait for oscillation accuracy stabilization reset processing (about 2.1 to 5.8 ms) remark f x : x1 clock oscillation frequency preliminary user?s manual u19291ej1v0ud 653 chapter 19 reset function the following five operations are available to generate a reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop detection (3) internal reset by comparison of supply voltage and detection voltage of power-on-clear (poc) circuit (4) internal reset by comparison of supply voltage of the low-voltage detector (lvi) or input voltage (exlvi) from external input pin, and detection voltage (5) internal reset by execution of illegal instruction note external and internal resets start program execution from the address at 0000h and 0001h when the reset signal is generated. a reset is effected when a low level is input to the r eset pin, the watchdog timer overflows, or by poc and lvi circuit voltage detection or ex ecution of illegal instruction note , and each item of hardware is set to the status shown in tables 19-1 and 19-2. each pin is hi gh impedance during reset signal generation or during the oscillation stabilization time just after a reset release, exc ept for p140, which is low-level output. when a low level is input to the reset pin, the device is reset. it is released from the reset status when a high level is input to the reset pin and program execution is started with the internal high- speed oscillation clock after reset processing. a reset by the watchdog timer is autom atically released, and program execution starts using the internal high-speed oscillation clock (see figures 19-2 to 19-4 ) after reset processing. reset by poc and lvi circuit power supply detection is automatically released when v dd v por or v dd v lvi after the reset, and program execution starts using the internal high-speed oscillation clock (see chapter 20 power-on-clear circuit and chapter 21 low-voltage detector ) after reset processing. note the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circu it emulator or on-chip debug emulator. cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. (to perform an external reset upon power application, a low l evel of at least 10 s must be continued during the period in which the s upply voltage is within the operating range (v dd 1.8 v).) 2. during reset input, the x1 clo ck, xt1 clock, internal high-speed oscillati on clock, and internal low-speed oscillation clock stop oscillating. external main system clock input becomes invalid. 3. when the stop mode is released by a rese t, the ram contents in the stop mode are held during reset input. 4. when reset is effected, port pin p140 is se t to low-level output and other port pins become high-impedance, because each sf r and 2nd sfr are initialized. remark v por : poc power supply rise detection voltage chapter 19 reset function preliminary user?s manual u19291ej1v0ud 654 figure 19-1. block di agram of reset function lvirf wdrf reset control flag register (resf) internal bus watchdog timer reset signal reset power-on clear circuit reset signal low-voltage detector reset signal reset signal reset signal to lvim/lvis register clear set clear set trap reset signal by execution of illegal instruction set clear resf register read signal caution an lvi circuit internal r eset does not reset the lvi circuit. remarks 1. lvim: low-voltage detection register 2. lvis: low-voltage detection level select register chapter 19 reset function preliminary user?s manual u19291ej1v0ud 655 figure 19-2. timing of reset by reset input delay hi-z normal operation cpu status reset period (oscillation stop) normal operation (internal high-speed oscillation clock) reset internal reset signal port pin (except p140) port pin (p140 note 1 ) note 2 high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock starting x1 oscillation is specified by software. reset processing (about 2.1 to 5.8 ms) wait for oscillation accuracy stabilization delay figure 19-3. timing of reset du e to watchdog timer overflow normal operation reset period (oscillation stop) cpu status watchdog timer overflow internal reset signal hi-z note 2 high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) wait for oscillation accuracy stabilization reset processing port pin (except p140) port pin (p140 note 1 ) (about 195 to 322 s) notes 1. p140 pin is not mounted onto 44-pi n products of the 78k0r/kc3-l. 2. when p140 is set to high-level output before reset is effected, the output signal of p140 can be dummy- output as a reset signal to an external device, because p140 outputs a low level when reset is effected. to release a reset signal to an external devi ce, set p140 to high-level output by software. caution a watchdog timer internal reset resets the watchdog timer. chapter 19 reset function preliminary user?s manual u19291ej1v0ud 656 figure 19-4. timing of reset in stop mode by reset input delay normal operation cpu status reset period (oscillation stop) reset internal reset signal stop instruction execution stop status (oscillation stop) high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock hi-z note 2 starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) wait for oscillation accuracy stabilization reset processing (about 2.1 to 5.8 ms) (about 30 to 170 s) delay port pin (except p140) port pin (p140 note 1 ) notes 1. p140 pin is not mounted onto 44-pi n products of the 78k0r/kc3-l. 2. set p140 to high-level output by software. when p1 40 is set to high-level output before reset is effected, the output signal of p140 can be dummy-output as a reset signal to an external device, because p140 outputs a low level when reset is effe cted. to release a reset signal to an external device, set p140 to high-level output by software. remark for the reset timing of the power-on-cl ear circuit and low-voltage detector, see chapter 20 power- on-clear circuit and chapter 21 low-voltage detector . chapter 19 reset function preliminary user?s manual u19291ej1v0ud 657 table 19-1. operation st atuses during reset period item during reset period system clock clock supply to the cpu is stopped. f ih operation stopped f x operation stopped (x1 and x2 pins are input port mode) main system clock f ex clock input invalid (pin is input port mode) subsystem clock f xt operation stopped (xt1 and xt2 pins are input port mode) f il cpu flash memory operation stopped ram operation stopped (the value, however, is reta ined when the voltage is at least the power-on- clear detection voltage.) port (latch) set p140 to low-level output. the port pins except for p140 become high impedance. timer array unit taus real-time counter (rtc) watchdog timer clock output/buzzer output note a/d converter programmable gain amplifier comparator serial array unit (sau) serial interface (iica) note multiplier/divider dma controller operation stopped power-on-clear function dete ction operation possible low-voltage detection function operation stopped (however, operation continues at lvi reset) external interrupt key interrupt function operation stopped note this is not mounted onto 44-pin products of the 78k0r/kc3-l. remark f ih : internal high-speed oscillation clock f x : x1 oscillation clock f ex : external main system clock f xt : xt1 oscillation clock f il : internal low-speed oscillation clock chapter 19 reset function preliminary user?s manual u19291ej1v0ud 658 table 19-2. hardware statuses after reset acknowledgment (1/4) hardware after reset acknowledgment note 1 program counter (pc) the contents of the reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 06h data memory undefined note 2 ram general-purpose registers undefined note 2 port registers (p0 to p8, p12, p14, p15) (output latches) 00h pm0 to pm8, pm12, pm15 ffh port mode registers pm14 feh port input mode registers 3, 7, 8 (pim3, pim7, pim8) 00h port output mode registers 3, 7 (pom3, pom7) 00h pull-up resistor option registers (pu0, pu1, pu3 to pu5, pu7, pu12, pu14) 00h clock operation mode control register (cmc) 00h clock operation status control register (csc) c0h system clock control register (ckc) 09h 20 mhz internal high-speed oscillation control register (dscctl) 00h oscillation stabilization time counter status register (ostc) 00h oscillation stabilization time select register (osts) 07h noise filter enable registers 0, 1, 2 (nfen0, nfen1, nfen2) 00h peripheral enable registers 0, 1, 2 (per0, per1, per2) 00h operation speed mode control register (osmc) 00h timer data registers 00, 01, 02, 03, 04, 05, 06, 07 (tdr00, tdr01, tdr02, tdr03, tdr04, tdr05, tdr06, tdr07) 0000h timer mode registers 00, 01, 02, 03, 04, 05, 06, 07 (tmr00, tmr01, tmr02, tmr03, tmr04, tmr05, tmr06, tmr07) 0000h timer status registers 00, 01, 02, 03, 04, 05, 06, 07 (tsr00, tsr01, tsr02, tsr03, tsr04, tsr05, tsr06, tsr07) 0000h timer input select register 0 (tis0) 00h timer counter registers 00, 01, 02, 03, 04, 05, 06, 07 (tcr00, tcr01, tcr02, tcr03, tcr04, tcr05, tcr06, tcr07) ffffh timer channel enable status register 0 (te0) 0000h timer channel start trigger register 0 (ts0) 0000h timer channel stop trigger register 0 (tt0) 0000h timer clock select register 0 (tps0) 0000h timer channel output register 0 (to0) 0000h timer channel output enable register 0 (toe0) 0000h timer channel output level register 0 (tol0) 0000h timer array unit (taus) timer channel output mode register 0 (tom0) 0000h notes 1. during reset signal generation or oscillation st abilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. remark the special function register (s fr) mounted depend on the product. see 3.2.4 special fu nction registers (sfrs) and 3.2.5 extended special function registers (2nd sfrs: 2nd special function registers) . chapter 19 reset function preliminary user?s manual u19291ej1v0ud 659 table 19-2. hardware statuses after reset acknowledgment (2/4) hardware status after reset acknowledgment note 1 sub-count register (rsubc) 0000h second count register (sec) 00h minute count register (min) 00h hour count register (hour) 12h week count register (week) 00h day count register (day) 01h month count register (month) 01h year count register (year) 00h watch error correction register (subcud) 00h alarm minute register (alarmwm) 00h alarm hour register (alarmwh) 12h alarm week register alarmww) 00h control register 0 (rtcc0) 00h control register 1 (rtcc1) 00h real-time counter control register 2 (rtcc2) 00h clock output/buzzer output controller clock output select registers 0, 1 (cks0, cks1) 00h watchdog timer enable register (wdte) 1ah/9ah note 2 10-bit a/d conversion result register (adcr) 0000h 8-bit a/d conversion result register (adcrh) 00h mode register (adm) 00h analog input channel specification register (ads) 00h a/d converter a/d port configuration register (adpc) 10h serial data registers 00, 01, 02, 03 (sdr00, sdr01, sdr02, sdr03) 0000h serial status registers 00, 01, 02, 03 (ssr00, ssr01, ssr02, ssr03) 0000h serial flag clear trigger registers 00, 01, 02, 03 (sir00, sir01, sir02, sir03) 0000h serial mode registers 00, 01, 02, 03 (smr00, smr01, smr02, smr03) 0020h serial communication operation setting registers 00, 01, 02, 03 (scr00, scr01, scr02, scr03) 0087h serial channel enable status register 0 (se0) 0000h serial channel start trigger register 0 (ss0) 0000h serial channel stop trigger register 0 (st0) 0000h serial clock select register 0 (sps0) 0000h serial output register 0 (so0) 0f0fh serial output enable register 0 (soe0) 0000h serial array unit (sau) input switch control register (isc) 00h notes 1. during reset signal generation or oscillation st abilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. the reset value of wdte is dete rmined by the option byte setting. remark the special function register (s fr) mounted depend on the product. see 3.2.4 special fu nction registers (sfrs) and 3.2.5 extended special function registers (2nd sfrs: 2nd special function registers) . chapter 19 reset function preliminary user?s manual u19291ej1v0ud 660 table 19-2. hardware statuses after reset acknowledgment (3/4) hardware status after reset acknowledgment note 1 iica shift register (iica) 00h iica status register (iics) 00h iica flag register (iicf) 00h iica control register 0 (iictl0) 00h iica control register 1 (iictl1) 00h iica low-level width setting register (iicwl) ffh iica high-level width setting register (iicwh) ffh serial interface iica slave address register (sva) 00h multiplication/division data r egister a (l) (mdal) 0000h multiplication/division data r egister a (h) (mdah) 0000h multiplication/division data r egister b (l) (mdbl) 0000h multiplication/division data r egister b (h) (mdbh) 0000h multiplication/division data register c (l) (mdcl) 0000h multiplication/division data register c (h) (mdch) 0000h multiplier/divider multiplication/division control register (mduc) 00h key interrupt key return mode register (krm) 00h reset function reset control flag register (resf) undefined note 2 low-voltage detection register (lvim) 00h note 3 low-voltage detector low-voltage detection level select register (lvis) 0eh note 2 sfr address registers 0, 1 (dsa0, dsa1) 00h ram address registers 0l, 0h, 1l, 1h (dra0l, dra0h, dra1l, dra1h) 00h byte count registers 0l, 0h, 1l, 1h (dbc0l, dbc0h, dbc1l, dbc1h) 00h mode control registers 0, 1 (dmc0, dmc1) 00h dma controller operation control registers 0, 1 (drc0, drc1) 00h notes 1. during reset signal generation or oscillation st abilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. these values vary depending on the reset source. reset source register reset input reset by poc reset by execution of illegal instruction reset by wdt reset by lvi trap bit set (1) held held wdrf bit held set (1) held resf lvirf bit cleared (0) cleared (0) held held set (1) lvis cleared (0eh) cleared (0eh) cleared (0eh) cleared (0eh) held 3. this value varies depending on the reset source and the option byte. remark the special function register (s fr) mounted depend on the product. see 3.2.4 special fu nction registers (sfrs) and 3.2.5 extended special function registers (2nd sfrs: 2nd special function registers) . chapter 19 reset function preliminary user?s manual u19291ej1v0ud 661 table 19-2. hardware statuses after reset acknowledgment (4/4) hardware status after reset acknowledgment note request flag registers 0l, 0h, 1l, 1h, 2l (if0l, if0h, if1l, if1h, if2l) 00h mask flag registers 0l, 0h, 1l, 1h, 2l (mk0l, mk0h, mk1l, mk1h, mk2l) ffh priority specification flag registers 00l, 00h, 01l, 01h, 02l, 10l, 10h, 11l, 11h, 12l (pr00l, pr00h, pr01l, pr01h, pr10l, pr10h, pr11l, pr11h, pr02l, pr12l) ffh external interrupt rising edge enable register 0 (egp0) 00h interrupt external interrupt falling edge enable register 0 (egn0) 00h programmable gain amplifier programmable gain amplifier control register (oam) 00h comparator 0 control register (c0ctl) 00h comparator 0 internal reference voltage setting register (c0rvm) 00h comparator 1 control register (c1ctl) 00h comparator comparator 1 internal reference voltage setting register (c1rvm) 00h note during reset signal generation or oscillation stabilizat ion time wait, only the pc contents among the hardware statuses become undefined. all other hardwar e statuses remain unchanged after reset. remark the special function register (s fr) mounted depend on the product. see 3.2.4 special fu nction registers (sfrs) and 3.2.5 extended special function registers (2nd sfrs: 2nd special function registers) . chapter 19 reset function preliminary user?s manual u19291ej1v0ud 662 19.1 register for confirming reset source many internal reset generation sources exist in the 78k0r/kx3 -l. the reset control flag register (resf) is used to store which source has generated the reset request. resf can be read by an 8-bit memory manipulation instruction. reset input, reset by power-on-clear (poc) circui t, and reading resf clear trap, wdrf, and lvirf. figure 19-5. format of reset control flag register (resf) address: fffa8h after reset: undefined r symbol 7 6 5 4 3 2 1 0 resf trap note 1 undefined undefined wdrf note 1 undefined undefined undefined lvirf note 1 trap internal reset request by execution of illegal instruction note 2 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. wdrf internal reset request by watchdog timer (wdt) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. lvirf internal reset request by low-voltage detector (lvi) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. notes 1. the value after reset varies depending on the reset source. 2. the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction ex ecution not issued by emul ation with the in-circuit emulator or on-chip debug emulator. cautions 1. do not read data by a 1-bit memory manipulation instruction. 2. do not make a judgment based on only the read value of the resf register 8-bit data, because bits other than trap, w drf, and lvirf b ecome undefined. 3. when the lvi default start f unction (bit 0 (lvioff) of 000c1h = 0) is used, lvirf flag may become 1 from the beginning de pending on the power-on waveform. the status of resf when a reset request is generated is shown in table 19-3. table 19-3. resf status when reset request is generated reset source flag reset input reset by poc reset by execution of illegal instruction reset by wdt reset by lvi trap set (1) held held wdrf held set (1) held lvirf cleared (0) cleared (0) held held set (1) preliminary user?s manual u19291ej1v0ud 663 chapter 20 power-on-clear circuit 20.1 functions of power-on-clear circuit the power-on-clear circuit (poc) has the following functions. ? generates internal reset signal at power on. the reset signal is released when the supply voltage (v dd ) exceeds 1.61 v 0.09 v note . caution if the low-voltage detector (l vi) is set to on by an option byte by default, the reset signal is not released until the supply voltage (v dd ) exceeds 2.07 v 0.2 v note . ? compares supply voltage (v dd ) and detection voltage (v pdr = 1.59 v 0.09 v note ), generates internal reset signal when v dd < v pdr . note these are preliminary values and subject to change. caution if an internal reset signal is generated in the poc circuit, trap, wdrf, and lvirf of the reset control flag register (resf) is cleared. remark this product incorporates multiple hardware functi ons that generate an internal reset signal. a flag that indicates the reset source is located in the reset control flag register (resf) for when an internal reset signal is generated by the watchdog timer (wdt), low-voltage-detector (lvi), or illegal instruction execution. resf is not cleared to 00h and the flag is set to 1 when an internal reset signal is generated by wdt or lvi. for details of resf, see chapter 19 reset function . chapter 20 power-on-clear circuit preliminary user?s manual u19291ej1v0ud 664 20.2 configuration of power-on-clear circuit the block diagram of the power-on-clear circuit is shown in figure 20-1. figure 20-1. block diagram of power-on-clear circuit ? + reference voltage source internal reset signal v dd v dd 20.3 operation of power-on-clear circuit ? an internal reset signal is generated on pow er application. when the supply voltage (v dd ) exceeds the detection voltage (v pdr = 1.61 v 0.09 v note ), the reset status is released. caution if the low-voltage detector (l vi) is set to on by an option byte by default, the reset signal is not released until the supply voltage (v dd ) exceeds 2.07 v 0.2 v note . ? the supply voltage (v dd ) and detection voltage (v pdr = 1.59 v 0.09 v note ) are compared. when v dd < v pdr , the internal reset signal is generated. note these are preliminary values and subject to change. the timing of generation of the internal reset signal by t he power-on-clear circuit and low-voltage detector is shown below. chapter 20 power-on-clear circuit preliminary user?s manual u19291ej1v0ud 665 figure 20-2. timing of generation of intern al reset signal by power-on-clear circuit and low-voltage detector (1/2) (1) when lvi is off upon power a pplication (option byte: lvioff = 1) internal high-speed oscillation clock (f ih ) high-speed system clock (f mx ) (when x1 oscillation is selected) starting oscillation is specified by software v pdr = 1.59 v (typ.) note 6 v lvi operation stops v por = 1.61 v (typ.) note 6 starting oscillation is specified by software cpu 0 v supply voltage (v dd ) 1.8 v note 1 0.5 v/ms (min.) note 2 starting oscillation is specified by software wait for oscillation accuracy stabilization note 4 wait for oscillation accuracy stabilization note 3 wait for oscillation accuracy stabilization note 3 reset processing (about 195 to 322 s) set lvi to be used for reset set lvi to be used for reset set lvi to be used for interrupt normal operation (internal high-speed oscillation clock) note 5 operation stops reset period (oscillation stop) reset period (oscillation stop) normal operation (internal high-speed oscillation clock) note 5 normal operation (internal high-speed oscillation clock ) note 5 reset processing (about 2.1 to 5.8 ms) reset processing (about 2.1 to 5.8 ms) internal reset signal notes 1. the operation guaranteed range is 1.8 v v dd 5.5 v. to make the state at lower than 1.8 v reset state when the supply voltage falls, us e the reset function of the low-vo ltage detector, or input the low level to the reset pin. 2. if the rate at which the voltage rises to 1.8 v afte r power application is slower than 0.5 v/ms (min.), input a low level to the reset pin before the voltage r eaches to 1.8 v, or set lvi to on by default by using an option byte (option byte: lvioff = 0). 3. the reset processing time, such as when waiting for internal voltage stabilization, includes the oscillation accuracy stabilization time of t he internal high-speed oscillation clock. 4. the internal reset processing time includes the o scillation accuracy stabilization time of the internal high-speed oscillation clock. 5. the internal high-speed oscillation clock and a hi gh-speed system clock or subsystem clock can be selected as the cpu clock. to us e the x1 clock, use the ostc regi ster to confirm the lapse of the oscillation stabilization time. to us e the xt1 clock, use the timer func tion for confirmation of the lapse of the stabilization time. 6. this is a preliminary value and subject to change. caution set the low-voltage detector by software after the reset status is released (see chapter 21 low-voltage detector). remark v lvi : lvi detection voltage v por : poc power supply rise detection voltage v pdr : poc power supply fall detection voltage chapter 20 power-on-clear circuit preliminary user?s manual u19291ej1v0ud 666 figure 20-2. timing of generation of intern al reset signal by power-on-clear circuit and low-voltage detector (2/2) (2) when lvi is on upon power app lication (option byte: lvioff = 0) internal high-speed oscillation clock (f ih ) high-speed system clock (f mx ) (when x1 oscillation is selected) v pdr = 1.59 v (typ.) note 3 v lvi operation stops v por = 1.61 v (typ.) note 3 cpu 0 v supply voltage (v dd ) 1.8 v note 1 v lvi = 2.07 v (typ.) note 3 wait for oscillation accuracy stabilization note 4 wait for oscillation accuracy stabilization note 4 wait for oscillation accuracy stabilization note 4 set lvi (v lvi = 2.07 v) to be used for reset (default) set lvi (v lvi = 2.07 v) to be used for reset (default) change lvi detection voltage (v lvi ) set lvi to be used for interrupt starting oscillation is specified by software starting oscillation is specified by software starting oscillation is specified by software normal operation (internal high-speed oscillation clock) note 2 normal operation (internal high-speed oscillation clock) note 2 operation stops reset period (oscillation stop) normal operation (internal high-speed oscillation clock) note 2 reset period (oscillation stop) reset processing time reset processing time (about 195 to 322 s) poc processing time reset processing time poc processing time internal reset signal note 5 note 5 notes 1. the operation guaranteed range is 1.8 v v dd 5.5 v. to make the state at lower than 1.8 v reset state when the supply voltage falls, us e the reset function of the low-vo ltage detector, or input the low level to the reset pin. 2. the internal high-speed oscillation clock and a hi gh-speed system clock or subsystem clock can be selected as the cpu clock. to us e the x1 clock, use the ostc regi ster to confirm the lapse of the oscillation stabilization time. to us e the xt1 clock, use the timer func tion for confirmation of the lapse of the stabilization time. 3. these are preliminary values and subject to change. 4. the internal reset processing time includes the o scillation accuracy stabilization time of the internal high-speed oscillation clock. 5. the following times are required between reaching the poc detection voltag e (1.61 v (typ.)) and starting normal operation. ? when the time to reach 2.07 v (typ.) from 1.61 v (typ.) is less than 5.8 ms: a poc processing time of about 2.1 to 6.2 ms is required between reaching 1.61 v (typ.) and starting normal operation. ? when the time to reach 2.07 v (typ.) from 1.61 v (typ.) is greater than 5.8 ms: a reset processing time of about 195 to 322 s is required between reaching 2.07 v (typ.) and starting normal operation. caution set the low-voltage detector by software after the reset status is released (see chapter 21 low-voltage detector). remark v lvi : lvi detection voltage v por : poc power supply rise detection voltage v pdr : poc power supply fall detection voltage chapter 20 power-on-clear circuit preliminary user?s manual u19291ej1v0ud 667 20.4 cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v por , v pdr ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcont roller can be arbitrarily set by taking the following action. chapter 20 power-on-clear circuit preliminary user?s manual u19291ej1v0ud 668 figure 20-3. example of software processing after reset release (2/2) ? checking reset source yes no check reset source power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector no wdrf of resf register = 1? lvirf of resf register = 1? yes no reset processing by illegal instruction execution note trap of resf register = 1? yes note the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. preliminary user?s manual u19291ej1v0ud 669 chapter 21 low-voltage detector 21.1 functions of low-voltage detector the low-voltage detector (lvi ) has the following functions. ? the lvi circuit compares the supply voltage (v dd ) with the detection voltage (v lvi ) or the input voltage from an external input pin (exlvi) with the detection voltage (v exlvi = 1.21 v 0.1 v note ), and generates an internal reset or internal interrupt signal. ? the low-voltage detector (lvi) can be set to on by an option byte by default. if it is se t to on to raise the power supply from the poc detection voltage (v por = 1.61 v (typ.)) or lower, the internal reset signal is generated when the supply voltage (v dd ) < detection voltage (v lvi = 2.07 v 0.2 v note ). after that, the internal reset signal is generated when the supply voltage (v dd ) < detection voltage (v lvi = 2.07 v 0.1 v note ). ? the supply voltage (v dd ) or the input voltage from the external in put pin (exlvi) can be selected to be detected by software. ? a reset or an interrupt can be selected to be generated after detection by software. ? detection levels (v lvi ,16 levels) of supply voltage can be changed by software. ? operable in stop mode. note this is a preliminary value and subject to change. the reset and interrupt signals are generated as follows depending on selection by software. selection of level detection of supply voltage (v dd ) (lvisel = 0) selection level detection of input voltage from external input pin (exlvi) (lvisel = 1) selects reset (lvimd = 1). selects interrupt (lvimd = 0). selects reset (lvimd = 1). selects interrupt (lvimd = 0). generates an internal reset signal when v dd < v lvi and releases the reset signal when v dd v lvi . generates an internal interrupt signal when v dd drops lower than v lvi (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ). generates an internal reset signal when exlvi < v exlvi and releases the reset signal when exlvi v exlvi . generates an internal interrupt signal when exlvi drops lower than v exlvi (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ). remark lvisel: bit 2 of low-voltage detection register (lvim) lvimd: bit 1 of lvim while the low-voltage detector is operat ing, whether the supply voltage or t he input voltage from an external input pin is more than or less than the detection level can be che cked by reading the low-voltage detection flag (lvif: bit 0 of lvim). when the low-voltage detector is used to reset, bit 0 (lvirf) of the reset control flag regi ster (resf) is set to 1 if reset occurs. for details of resf, see chapter 19 reset function . chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 670 21.2 configuration of low-voltage detector the block diagram of the low-voltage detector is shown in figure 21-1. figure 21-1. block diagram of low-voltage detector lvis1 lvis0 lvion ? + reference voltage source v dd internal bus n-ch low-voltage detection level select register (lvis) low-voltage detection register (lvim) lvis2 lvis3 lvif intlvi internal reset signal 4 lvisel exlvi/p120/ intp0 lvimd v dd low-voltage detection level selector selector selector 21.3 registers controlli ng low-voltage detector the low-voltage detector is contro lled by the following registers. ? low-voltage detection register (lvim) ? low-voltage detection level select register (lvis) ? port mode register 12 (pm12) (1) low-voltage detection register (lvim) this register sets low-voltag e detection and the operation mode. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 671 figure 21-2. format of low-volta ge detection register (lvim) <0> lvif <1> lvimd <2> lvisel 3 0 4 0 5 0 6 0 <7> lvion symbol lvim address: fffa9h after reset: 00h note 1 r/w note 2 lvion notes 3, 4 enables low-voltage detection operation 0 disables operation 1 enables operation lvisel note 3 voltage detection selection 0 detects level of supply voltage (v dd ) 1 detects level of input voltage from external input pin (exlvi) lvimd low-voltage detection operation mode (interrupt/reset) selection 0 ? lvisel = 0: generates an internal interrupt signal when the supply voltage (v dd ) drops lower than the detection voltage (v lvi ) (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ). ? lvisel = 1: generates an interrupt signal when the input voltage from an external input pin (exlvi) drops lower than the detection voltage (v exlvi ) (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ). 1 ? lvisel = 0: generates an internal reset signal when the supply voltage (v dd ) < detection voltage (v lvi ) and releases the reset signal when v dd v lvi . ? lvisel = 1: generates an internal reset signal when the input voltage from an external input pin (exlvi) < detection voltage (v exlvi ) and releases the reset signal when exlvi v exlvi . lvif low-voltage detection flag 0 ? lvisel = 0: supply voltage (v dd ) detection voltage (v lvi ), or when lvi operation is disabled ? lvisel = 1: input voltage from external input pin (exlvi) detection voltage (v exlvi ), or when lvi operation is disabled 1 ? lvisel = 0: supply voltage (v dd ) < detection voltage (v lvi ) ? lvisel = 1: input voltage from external input pin (exlvi) < detection voltage (v exlvi ) notes 1. the reset value changes depending on the rese t source and the setting of the option byte. this register is not cleared (00h) by lvi reset. it is set to ?82h? when a reset signal other than lv i is applied if option byte lvioff = 0, and to ?00h? if option byte lvioff = 1. 2. bit 0 is read-only. 3. lvion, lvimd, and lvisel are cleared to 0 in t he case of a reset other than an lvi reset. these are not cleared to 0 in the case of an lvi reset. chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 672 note 4. when lvion is set to 1, operation of the comparator in the lvi circuit is started. use software to wait for the following periods of time, between when lv ion is set to 1 and when the voltage is confirmed with lvif. ? operation stabilization time (10 s (max.)) ? minimum pulse width (200 s (min.)) ? detection delay time (200 s (max.)) the lvif value for these periods may be set/cl eared regardless of the voltage level, and can therefore not be used. also, the lviif interrupt request flag may be set to 1 in these periods. cautions 1. to stop lvi, follow either of the procedures below. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. 2. input voltage from external input pin (exlvi) must be exlvi < v dd . 3. when lvi is used in interrupt mode (lvimd = 0) and lvisel is set to 0, an interrupt request signal (intlvi) that disables lvi operation (clears lvion) when the supply voltage (v dd ) is less than or equal to the detection voltage (v lvi ) (if lvisel = 1, input voltage of external input pin (exlvi) is less than or equal to the detection voltage (v exlvi )) is generated and lviif may be set to 1. chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 673 (2) low-voltage detection l evel select register (lvis) this register selects the low-voltage detection level. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation input sets this register to 0eh. figure 21-3. format of low-voltage dete ction level select register (lvis) 0 lvis0 1 lvis1 2 lvis2 3 lvis3 4 0 5 0 6 0 7 0 symbol lvis address: fffaah after reset: 0eh note 1 r/w lvis3 lvis2 lvis1 lvis0 detection level 0 0 0 0 v lvi0 (4.22 0.1 v) note 2 0 0 0 1 v lvi1 (4.07 0.1 v) note 2 0 0 1 0 v lvi2 (3.92 0.1 v) note 2 0 0 1 1 v lvi3 (3.76 0.1 v) note 2 0 1 0 0 v lvi4 (3.61 0.1 v) note 2 0 1 0 1 v lvi5 (3.45 0.1 v) note 2 0 1 1 0 v lvi6 (3.30 0.1 v) note 2 0 1 1 1 v lvi7 (3.15 0.1 v) note 2 1 0 0 0 v lvi8 (2.99 0.1 v) note 2 1 0 0 1 v lvi9 (2.84 0.1 v) note 2 1 0 1 0 v lvi10 (2.68 0.1 v) note 2 1 0 1 1 v lvi11 (2.53 0.1 v) note 2 1 1 0 0 v lvi12 (2.38 0.1 v) note 2 1 1 0 1 v lvi13 (2.22 0.1 v) note 2 1 1 1 0 v lvi14 (2.07 0.1 v) note 2 1 1 1 1 v lvi15 (1.91 0.1 v) note 2 notes 1. the reset value changes depending on the reset source. if the lvis register is reset by lvi, it is not reset but holds the current value. the value of this register is reset to ?0eh? if a reset other than by lvi is effected. 2. these are preliminary values and subject to change. caution 1. be sure to cl ear bits 4 to 7 to ?0?. chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 674 cautions 2. change the lvis value with either of the following methods. ? when changing the value after stopping lvi <1> stop lvi (lvion = 0). <2> change the lvis register. <3> set to the mode used as an interrupt (lvimd = 0). <4> mask lvi interrupts (lvimk = 1). <5> enable lvi operation (lvion = 1). <6> before cancelling the lvi interrupt mask (lvimk = 0), clear it with software because an lviif flag may be set when lvi operation is enabled. ? when changing the value after setting to the mode used as an interrupt (lvimd = 0) <1> mask lvi interrupts (lvimk = 1). <2> set to the mode used as an interrupt (lvimd = 0). <3> change the lvis register. <4> before cancelling the lvi interrupt mask (lvimk = 0), clear it with software because an lviif flag may be set when the lvis register is changed. 3. when an input voltage from the externa l input pin (exlvi) is detected, the detection voltage (v exlvi ) is fixed. therefore, setting of lvis is not necessary. (3) port mode register 12 (pm12) when using the p120/exlvi/intp0 pin for external low-volt age detection potential input, set pm120 to 1. at this time, the output latch of p120 may be 0 or 1. pm12 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 21-4. format of port mode register 12 (pm12) 0 pm120 1 1 2 1 3 1 4 1 5 1 6 1 7 1 symbol pm12 address: fff2ch after reset: ffh r/w pm120 p120 pin i/o mode selection 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 675 21.4 operation of low-voltage detector the low-voltage detector can be us ed in the following two modes. (1) used as reset (lvimd = 1) ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ), generates an internal reset signal when v dd < v lvi , and releases internal reset when v dd v lvi . ? if lvisel = 1, compares the input voltage from external input pin (exlvi) and detection voltage (v exlvi ), generates an internal reset signal when exlvi < v exlvi , and releases internal reset when exlvi v exlvi . remark the low-voltage detector (lvi) can be set to on by an option byte by default. if it is set to on to raise the power supply from the poc detection voltage (v por = 1.61 v (typ.)) or lower, the internal reset signal is generated when the supply voltage (v dd ) < detection voltage (v lvi = 2.07 v 0.2 v note ). after that, the internal reset signal is generated when the supply voltage (v dd ) < detection voltage (v lvi = 2.07 v 0.1 v note ). (2) used as interrupt (lvimd = 0) ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ). when v dd drops lower than v lvi (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ), generates an interrupt signal (intlvi). ? if lvisel = 1, compares the input voltage from external input pin (exlvi) and detection voltage (v exlvi = 1.21 v 0.1 v note ). when exlvi drops lower than v exlvi (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ), generates an interrupt signal (intlvi). note this is a preliminary value and subject to change. while the low-voltage detector is operat ing, whether the supply voltage or t he input voltage from an external input pin is more than or less than the detection level can be che cked by reading the low-voltage detection flag (lvif: bit 0 of lvim). remark lvimd: bit 1 of low-voltage detection register (lvim) lvisel: bit 2 of lvim chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 676 21.4.1 when used as reset (1) when detecting level of supply voltage (v dd ) (a) when lvi default start function stopped is set (lvioff = 1) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low-voltage detection re gister (lvim) to 0 (detects level of supply voltage (v dd )) (default value). <3> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltage detection level selection register (lvis). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for the following periods of time (total 410 s). ? operation stabilization time (10 s (max.)) ? minimum pulse width (200 s (min.)) ? detection delay time (200 s (max.)) <6> wait until it is checked that (supply voltage (v dd ) detection voltage (v lvi )) by bit 0 (lvif) of lvim. <7> set bit 1 (lvimd) of lvim to 1 (generates reset when the level is detected). figure 21-5 shows the timing of the internal reset signal generated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <7> above. cautions 1. be sure to execute <1>. when lvim k = 0, an interrupt may o ccur immediately after the processing in <4>. 2. if supply voltage (v dd ) detection voltage (v lvi ) when lvimd is set to 1, an internal reset signal is not generated. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0. chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 677 figure 21-5. timing of low-voltage dete ctor internal reset signal generation (bit: lvisel = 0, option byte: lvioff = 1) l <1> <2> <4> <5> <6> <7> v lvi v pdr = 1.59 v (typ.) v por = 1.61 v (typ.) internal reset signal set lvi to be used for reset supply voltage (v dd ) lvimk flag (set by software) time h note 1 lvisel flag (set by software) lvion flag (set by software) not cleared not cleared not cleared not cleared wait time <3> cleared cleared cleared lvif flag lvimd flag (set by software) lvirf flag note 3 lvi reset signal cleared by software cleared by software poc reset signal note 2 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lviif flag of the interrupt request flag registers and the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag re gister (resf). for details of resf, see chapter 19 reset function . remarks 1. <1> to <7> in figure 21-5 above correspond to <1> to <7> in the description of ?when starting operation? in 21.4.1 (1) (a) when lvi default star t function stopped is set (lvioff = 1). 2. v por : poc power supply rise detection voltage v pdr : poc power supply fall detection voltage chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 678 (b) when lvi default start function enabled is set (lvioff = 0) ? when starting operation start in the following initial setting state. ? set bit 7 (lvion) of lvim to 1 (enables lvi operation) ? clear bit 2 (lvisel) of the low-voltage detection regi ster (lvim) to 0 (detects level of supply voltage (v dd )) ? set the low-voltage detection level selectio n register (lvis) to 0eh (default value: v lvi = 2.07 v 0.1 v ). ? set bit 1 (lvimd) of lvim to 1 (generat es reset when the level is detected) ? set bit 0 (lvif) of lvim to 0 (?supply voltage (v dd ) detection voltage (v lvi )?) figure 21-6 shows the timing of the internal rese t signal generated by the low-voltage detector. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0. caution even when the lvi default start function is used, if it is set to lvi operation prohibition by the software, it operates as follows: ? does not perform low-voltage detection during lvion = 0. ? if a reset is generated while lvion = 0, lvion will be re-set to 1 when the cpu starts after reset release. there is a pe riod when low-voltage detecti on cannot be performed normally, however, when a reset occurs due to wd t and illegal instruction execution. this is due to the fact that while the pulse width detected by lvi must be 200 s max., lvion = 1 is set upon reset occurrence, and th e cpu starts operating without waiting for the lvi stabilization time. chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 679 figure 21-6. timing of low-voltage dete ctor internal reset signal generation (bit: lvisel = 0, option byte: lvioff = 0) l v lvi = 2.07 v (typ.) v por = 1.61 v (typ.) v pdr = 1.59 v (typ.) h h internal reset signal supply voltage (v dd ) lvimk flag (set by software) lvisel flag (set by software) lvion flag (set by software) lvif flag lvimd flag (set by software) lvirf flag lvi reset signal poc reset signal time h note 1 not cleared not cleared not cleared not cleared cleared by software cleared by software cleared by software note 2 cleared cleared interrupt operation mode is set by setting lvimd to 0 (lvi interrupt is masked) change lvi detection voltage (v lvi ) reset mode is set by setting lvimd to 1 v lvi value after a change notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. lvirf is bit 0 of the reset control flag register (resf). when the lvi default start function (bit 0 (lvio ff) of 000c1h = 0) is used, the lvirf flag may become 1 from the beginning due to the power-on waveform. for details of resf, see chapter 19 reset function . remark v por : poc power supply rise detection voltage v pdr : poc power supply fall detection voltage chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 680 (2) when detecting level of input vo ltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regist er (lvim) to 1 (detects level of input voltage from external input pin (exlvi)). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to wait for the following periods of time (total 410 s). ? operation stabilization time (10 s (max.)) ? minimum pulse width (200 s (min.)) ? detection delay time (200 s (max.)) <5> wait until it is checked that (input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.))) by bit 0 (lvif) of lvim. <6> set bit 1 (lvimd) of lvim to 1 (generates reset signal when the level is detected). figure 21-7 shows the timing of the internal reset signal generated by the low-volt age detector. the numbers in this timing chart correspond to <1> to <6> above. cautions 1. be sure to execute <1>. when lvim k = 0, an interrupt may oc cur immediately after the processing in <3>. 2. if input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.)) when lvimd is set to 1, an intern al reset signal is not generated. 3. input voltage from external input pin (exlvi) must be exlvi < v dd . ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0. chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 681 figure 21-7. timing of low-voltage dete ctor internal reset signal generation (bit: lvisel = 1) v exlvi set lvi to be used for reset lvimk flag (set by software) lvif flag lvirf flag note 3 lvi reset signal internal reset signal lvion flag (set by software) lvimd flag (set by software) lvisel flag (set by software) <1> <2> <3> <4> wait time <5> <6> note 2 not cleared not cleared not cleared not cleared not cleared not cleared not cleared not cleared not cleared cleared by software cleared by software time h note 1 input voltage from external input pin (exlvi) notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lviif flag of the interrupt request flag registers and the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag re gister (resf). for details of resf, see chapter 19 reset function . remark <1> to <6> in figure 21-7 above correspond to <1> to <6> in the description of ? when starting operation? in 21.4.1 (2) when detecting level of input voltage from external input pin (exlvi) . chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 682 21.4.2 when used as interrupt (1) when detecting level of supply voltage (v dd ) (a) when lvi default start function stopped is set (lvioff = 1) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low-voltage detection re gister (lvim) to 0 (detects level of supply voltage (v dd )) (default value). clear bit 1 (lvimd) of lvim to 0 (generates interrupt signal when the level is detected) (default value). <3> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltag e detection level selection register (lvis). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for the following periods of time (total 410 s). ? operation stabilization time (10 s (max.)) ? minimum pulse width (200 s (min.)) ? detection delay time (200 s (max.)) <6> confirm that ?supply voltage (v dd ) detection voltage (v lvi )? when detecting the falling edge of v dd , or ?supply voltage (v dd ) < detection voltage (v lvi )? when detecting the rising edge of v dd , at bit 0 (lvif) of lvim. <7> clear the interrupt request flag of lvi (lviif) to 0. <8> release the interrupt mask flag of lvi (lvimk). <9> execute the ei instruction (w hen vector interrupts are used). figure 21-8 shows the timing of the interrupt signal ge nerated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <8> above. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 683 figure 21-8. timing of low-voltage de tector interrupt signal generation (bit: lvisel = 0, option byte: lvioff = 1) intlvi l <1> <3> <6> <7> <2> <4> l v lvi v por = 1.61 v (typ.) v pdr = 1.59 v (typ.) internal reset signal supply voltage (v dd ) lvimk flag (set by software) lvisel flag (set by software) lvion flag (set by software) lvimd flag (set by software) lvif flag lviif flag cleared by software <8> cleared by software <5> wait time note 3 note 2 note 2 note 2 note 1 note 3 time notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). 3. if lvi operation is disabled when the supply voltage (v dd ) is less than or equal to the detection voltage (v lvi ), an interrupt request signal (intlvi) is generated and lviif may be set to 1. remarks 1. <1> to <8> in figure 21-8 above correspond to <1> to <8> in the description of ?when starting operation? in 21.4.2 (1) (a) when lvi default star t function stopped is set (lvioff = 1). 2. v por : poc power supply rise detection voltage v pdr : poc power supply fall detection voltage chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 684 (b) when lvi default start function enabled is set (lvioff = 0) ? when starting operation <1> start in the following initial setting state. ? set bit 7 (lvion) of lvim to 1 (enables lvi operation) ? clear bit 2 (lvisel) of the low-voltage detection re gister (lvim) to 0 (detects level of supply voltage (v dd )) ? set the low-voltage detection level selectio n register (lvis) to 0eh (default value: v lvi = 2.07 v 0.1 v ). ? set bit 1 (lvimd) of lvim to 1 (generat es reset when the level is detected) ? set bit 0 (lvif) of lvim to 0 (detects falling edge ?supply voltage (v dd ) detection voltage (v lvi )?) <2> clear bit 1 (lvimd) of lvim to 0 (generates inte rrupt signal when the level is detected) (default value). <3> release the interrupt mask flag of lvi (lvimk). <4> execute the ei instruction (w hen vector interrupts are used). figure 21-9 shows the timing of the interrupt signal ge nerated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <3> above. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. cautions 1. even when the lvi default start function is used, if it is set to lvi operation prohibition by the software, it operates as follows: ? does not perform low-voltage detection during lvion = 0. ? if a reset is generated while lvion = 0, lvion will be re-set to 1 when the cpu starts after reset release. there is a period wh en low-voltage detection cannot be performed normally, however, when a reset occurs due to wdt and illegal instruction execution. this is due to the fact that while the pulse width detected by lvi must be 200 s max., lvion = 1 is set upon reset occurrence, a nd the cpu starts operating without waiting for the lvi stabilization time. 2. when the lvi default start function (bit 0 (l vioff) of 000c1h = 0) is used, the lvirf flag may become 1 from the beginning due to the power-on waveform. for details of resf, see chapter 19 reset function. chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 685 figure 21-9. timing of low-voltage de tector interrupt signal generation (bit: lvisel = 0, option byte: lvioff = 0) intlvi l v lvi = 2.07 v (typ.) v por = 1.61 v (typ.) v pdr = 1.59 v (typ.) <1> <2> internal reset signal supply voltage (v dd ) lvimk flag (set by software) lvisel flag (set by software) lvion flag (set by software) lvimd flag (set by software) lvif flag lviif flag cleared by software <3> cleared by software note 2 note 2 note 3 note 1 time v lvi value after a change mask lvi interrupts (lvimk = 1) cancelling the lvi interrupt mask (lvimk = 0) change lvi detection voltage (v lvi ) notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. if lvi operation is disabled when the supply voltage (v dd ) is less than or equal to the detection voltage (v lvi ), an interrupt request signal (intlvi) is generated and lviif may be set to 1. 3. the lviif flag may be set when the lvi detection voltage is changed. remarks 1. <1> to <3> in figure 21-9 above correspond to <1> to <3> in the description of ?when starting operation? in 21.4.2 (1) (b) when lvi default start function enabled is set (lvioff = 0). 2. v por : poc power supply rise detection voltage v pdr : poc power supply fall detection voltage chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 686 (2) when detecting level of input vo ltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regist er (lvim) to 1 (detects level of input voltage from external input pin (exlvi)). clear bit 1 (lvimd) of lvim to 0 (generates interrupt signal when the level is detected) (default value). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to wait for the following periods of time (total 410 s). ? operation stabilization time (10 s (max.)) ? minimum pulse width (200 s (min.)) ? detection delay time (200 s (max.)) <5> confirm that ?input voltage fr om external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.))? when detecting the falling edge of exlvi, or ?input vo ltage from external input pin (exlvi) < detection voltage (v exlvi = 1.21 v (typ.))? when detecting the rising e dge of exlvi, at bit 0 (lvif) of lvim. <6> clear the interrupt request flag of lvi (lviif) to 0. <7> release the interrupt mask flag of lvi (lvimk). <8> execute the ei instruction (w hen vector interrupts are used). figure 21-10 shows the timing of the interrupt signal ge nerated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <7> above. caution input voltage from external i nput pin (exlvi) must be exlvi < v dd . ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 687 figure 21-10. timing of low-voltage detector interrupt signal generation (bit: lvisel = 1) v exlvi l lvimk flag (set by software) lvif flag intlvi lviif flag lvion flag (set by software) lvisel flag (set by software) lvimd flag (set by software) input voltage from external input pin (exlvi) time <1> note 1 <7> cleared by software <2> <3> <5> note 2 note 2 note 2 <6> cleared by software <4> wait time note 3 note 3 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). 3. if lvi operation is disabled when the input voltage of ex ternal input pin (exlvi) is less than or equal to the detection voltage (v exlvi ), an interrupt request signal (intlv i) is generated and lviif may be set to 1. remark <1> to <7> in figure 21-10 above correspond to <1> to <7> in the description of ?when starting operation? in 21.4.2 (2) when detecting level of in put voltage from external input pin (exlvi) . chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 688 21.5 cautions for low-voltage detector (1) measures method wh en supply voltage (v dd ) frequently fluctuates in the vicinity of the lvi detection voltage (v lvi ) in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. operation example 1: when used as reset the system may be repeatedly reset and released from the reset status. the time from reset release through microcontroller operation start can be set arbitrarily by the following action. chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 689 figure 21-11. example of software processing after reset release (1/2) ? if supply voltage fluctuation is 50 ms or less in vicinity of lvi detection voltage ; check the reset source, etc. note ; setting of detection level by lvis. the low-voltage detector operates (lvion = 1). reset initialization processing <1> 50 ms has passed? (tmif0n = 1?) initialization processing <2> setting timer array unit (to measure 50 ms) ; initial setting for port. setting of division ratio of system clock, such as setting of timer or a/d converter. yes no setting lvi clearing wdt detection voltage or higher (lvif = 0?) yes restarting timer array unit (tt0n = 1 ts0n = 1) no ; the timer counter is cleared and the timer is started. lvi reset ;f clk = internal high-speed oscillation clock (8.4 mhz (max.)) (default) source: f clk (8.4 mhz (max.))/2 12 , where comparison value = 102: ? 50 ms timer starts (ts0n = 1). note a flowchart is shown on the next page. remarks 1. if bit 2 (lvisel) of the low voltage detection register (lvim) is set to ?1?, the meanings of the above words change as follows. ? supply voltage (v dd ) input voltage from external input pin (exlvi) ? detection voltage (v lvi ) detection voltage (v exlvi = 1.21 v) 2. n = 0 to 7 chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 690 figure 21-11. example of software processing after reset release (2/2) ? checking reset source yes no check reset source power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector yes wdrf of resf register = 1? lvirf of resf register = 1? yes no reset processing by illegal instruction execution note trap of resf register = 1? no note when instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. remark if bit 2 (lvisel) of the low voltage detection regist er (lvim) is set to ?1?, the meanings of the above words change as follows. ? supply voltage (v dd ) input voltage from external input pin (exlvi) ? detection voltage (v lvi ) detection voltage (v exlvi = 1.21 v) chapter 21 low-voltage detector preliminary user?s manual u19291ej1v0ud 691 operation example 2: when used as interrupt interrupt requests may be generated frequently. take the following action. preliminary user?s manual u19291ej1v0ud 692 chapter 22 regulator 22.1 regulator overview the 78k0r/kx3-l contains a circuit for operating the device with a constant voltage. at this time, in order to stabilize the regulator output voltage, connect the regc pin to v ss via a capacitor (0.47 to 1 f: target). however, when using the stop mode that has been entered since operat ion of the internal high-speed oscillation clock and external main system clock, 0.47 f is recommended. also, use a capacitor with good characteristics, since it is used to stabilize internal voltage. the regulator output voltage is norma lly 2.4 v (typ.), and in the low consum ption current mode, 1.8 v (typ.). 22.2 registers controlling regulator (1) regulator mode c ontrol register (rmc) this register sets the output voltage of the regulator. rmc is set with an 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 22-1. format of regulator mode control register (rmc) address: f00f4h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 rmc rmc[7:0] control of output voltage of regulator 5ah fixed to low consumption current mode (1.8 v) 00h switches normal current mode (2.4 v) and low consumption current mode (1.8 v) according to the condition (refer to table 22-1 ) other than above setting prohibited cautions 1. the rmc register can be rewritten only in the low cons umption current mode (refer to table 22-1). in other words, rewrite this re gister during cpu operation with the subsystem clock (f xt ) while the high-speed system clock (f mx ), the high-speed internal oscillation clock (f ih ), and the 20 mhz internal hi gh-speed oscillation clock (f ih20 ) are both stopped. 2. when using the setting fixed to the low c onsumption current mode, the rmc register can be used in the following cases. chapter 22 regulator preliminary user?s manual u19291ej1v0ud 693 caution 4. a wait is required to change the ope ration speed mode control register (osmc) after changing the rmc register. wait for 2 ms by software when setting to low consumption current mode and 10 s when setting to normal curre nt mode, as described in the procedure shown below. ? when setting to low consumption current mode <1> select a frequency of 1 mhz for f clk . <2> set rmc to 5ah (set the regulator to low consumption current mode). <3> wait for 2 ms. <4> set flpc and fsel of os mc to 1 and 0, respectively. ? when setting to normal current mode <1> set rmc to 00h (set the regulator to normal current mode). <2> wait for 10 s. <3> change flpc and fsel of osmc. <4> change the f clk frequency. table 22-1. regulator output voltage conditions mode output voltage condition during reset pin reset in stop mode (except during ocd mode) when both the high-speed system clock (f mx ), the high-speed internal oscillation clock (f ih ), and the 20 mhz internal high-speed oscillation clock (f ih20 ) are stopped during cpu operation with the subsystem clock (f xt ) low consumption current mode 1.8 v when both the high-speed system clock (f mx ), the high-speed internal oscillation clock (f ih ), and the 20 mhz internal high-speed oscillation clock (f ih20 ) are stopped during the halt mode when the cpu operation with the subsystem clock (f xt ) has been set normal current mode 2.4 v other than above preliminary user?s manual u19291ej1v0ud 694 chapter 23 option byte 23.1 functions of option bytes addresses 000c0h to 000c3h of the flash memory of the 78k0r/kx3-l form an option byte area. option bytes consist of user option byte (000c0h to 000c2h) and on-chip debug option byte (000c3h). upon power application or resetting and starting, an opti on byte is automatically referenced and a specified function is set. when using the product, be sure to se t the following functions by using the option bytes. to use the boot swap operation during self programming, 000c0h to 000c3h are replaced by 010c0h to 010c3h. therefore, set the same values as 000c0h to 000c3h to 010c0h to 010c3h. caution be sure to set ffh to 000c2h (000c2h/ 010c2h when the boot swap operation is used). 23.1.1 user option byte (000c0h to 000c2h/010c0h to 010c2h) (1) 000c0h/010c0h { operation of watchdog timer ? operation is stopped or enabl ed in the halt or stop mode. { setting of interval time of watchdog timer { operation of watchdog timer ? operation is stopped or enabled. { setting of window open period of watchdog timer { setting of interval interrupt of watchdog timer ? used or not used caution set the same value as 000c0h to 010c0h when the boot swap operation is used because 000c0h is replaced by 010c0h. (2) 000c1h/010c1h { setting of lvi upon reset release (upon power application) ? lvi is on or off by default upon reset release (re set by reset pin excluding lvi, poc, wdt, or illegal instructions). { setting of internal high-speed oscillator frequency ? select from 1 mhz, 8 mhz, or 20 mhz. caution set the same value as 000c1h to 010c1h when the boot swap operation is used because 000c1h is replaced by 010c1h. (3) 000c2h/010c2h { be sure to set ffh, as these addresses are reserved areas. caution set ffh to 010c2h when the boot swap operation is used because 000c2h is replaced by 010c2h. chapter 23 option byte preliminary user?s manual u19291ej1v0ud 695 23.1.2 on-chip debug option byte (000c3h/ 010c3h) { control of on-chip debug operation ? on-chip debug operation is disabled or enabled. { handling of data of flash memory in case of failure in on-chip debug security id authentication ? data of flash memory is erased or not erased in case of failure in on-chip debug security id authentication. caution set the same value as 000c3h to 010c3h when the boot swap operation is used because 000c3h is replaced by 010c3h. 23.2 format of user option byte the format of user option byte is shown below. figure 23-1. format of user option byte (000c0h/010c0h) (1/2) address: 000c0h/010c0h note 1 7 6 5 4 3 2 1 0 wdtinit window1 window0 wdton wdcs2 wdcs1 wdcs0 wdstbyon wdtinit use of interval interrupt of watchdog timer 0 interval interrupt is not used. 1 interval interrupt is generated when 75% of the overflow time is reached. window1 window0 watchdog timer window open period note 2 0 0 25% 0 1 50% 1 0 75% 1 1 100% wdton operation control of watchdog timer counter 0 counter operation disabled (counting stopped after reset) 1 counter operation enabled (counting started after reset) wdcs2 wdcs1 wdcs0 watc hdog timer overflow time (f il = 33 khz (max.)) 0 0 0 2 10 /f il (31.03 ms) 0 0 1 2 11 /f il (62.06 ms) 0 1 0 2 12 /f il (124.1 ms) 0 1 1 2 13 /f il (248.2 ms) 1 0 0 2 15 /f il (992.9 ms) 1 0 1 2 17 /f il (3.971 s) 1 1 0 2 18 /f il (7.943 s) 1 1 1 2 20 /f il (31.17 s) chapter 23 option byte preliminary user?s manual u19291ej1v0ud 696 figure 23-1. format of user option byte (000c0h/010c0h) (2/2) address: 000c0h/010c0h note 1 7 6 5 4 3 2 1 0 wdtinit window1 window0 wdton wdcs2 wdcs1 wdcs0 wdstbyon wdstbyon operation control of watc hdog timer counter (halt/stop mode) 0 counter operation stopped in halt/stop mode note 2 1 counter operation enabled in halt/stop mode notes 1. set the same value as 000c0h to 010c0h when t he boot swap operation is used because 000c0h is replaced by 010c0h. 2. the window open period is 100% when wdstbyo n = 0, regardless the value of window1 and window0. caution the watchdog timer conti nues its operation during self-program ming of the flash memory and eeprom emulation. during processing, the inte rrupt acknowledge time is delayed. set the overflow time and window size taki ng this delay into consideration. remark f il : internal low-speed oscillation clock frequency figure 23-2. format of user option byte (000c1h/010c1h) address: 000c1h/010c1h note 1 7 6 5 4 3 2 1 0 1 1 1 1 1 frqsel2 frqsel1 lvioff frqsel2 frqsel1 internal high-speed oscillator frequency 0 1 8 mhz/20 mhz note 2 1 0 1 mhz note 3 other than the above setting prohibited lvioff setting of lvi on power application 0 lvi is on by default (lvi default start function enabled) upon reset release (upon power application) 1 lvi is off by default (lvi default start function stopped) upon reset release (upon power application) notes 1. set the same value as 000c1h to 010c1h when t he boot swap operation is used because 000c1h is replaced by 010c1h. 2. when 8 mhz or 20 mhz has been selected, the 8 mhz internal high-speed oscillator automatically starts oscillating after reset release. to use t he 20 mhz internal high-speed oscillator to operate the microcontroller, oscillation is started by setting bit 0 (dscon) of the 20 mhz internal high-speed oscillation control register (dscctl) to 1 with v dd 2.7 v. the circuit cannot be changed to a 1 mhz internal high-speed oscillator wh ile the microcontroller operates. 3. when 1 mhz has been selected, the microcontro ller operates on the 1 mhz internal high-speed oscillator after reset release. the circuit cannot be changed to an 8 mhz or 20 mhz internal high- speed oscillator while the microcontroller operates. ( cautions are listed on the next page.) chapter 23 option byte preliminary user?s manual u19291ej1v0ud 697 cautions 1. be sure to set bits 7 to 3 to ?1?. 2. even when the lvi default start function is u sed, if it is set to lvi operation prohibition by the software, it operates as follows: ? does not perform low-voltage detection during lvion = 0. ? if a reset is generated while lvion = 0, lvion will be re-set to 1 when the cpu starts after reset release. there is a period when low-vo ltage detection cannot be performed normally, however, when a reset occurs due to wd t and illegal instruction execution. this is due to the fact that while the pulse width det ected by lvi must be 200 s max., lvion = 1 is set upon reset occurrence, and the cpu starts operating without waiting for the lvi stabilization time. figure 23-3. format of option byte (000c2h/010c2h) address: 000c2h/010c2h note 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 note be sure to set ffh to 000c2h, as these addresses ar e reserved areas. also set ffh to 010c2h when the boot swap operation is used because 000c2h is replaced by 010c2h. 23.3 format of on-chip debug option byte the format of on-chip debug option byte is shown below. figure 23-4. format of on-chip de bug option byte (000c3h/010c3h) address: 000c3h/010c3h note 7 6 5 4 3 2 1 0 ocdenset 0 0 0 0 1 0 ocdersd ocdenset ocdersd control of on-chip debug operation 0 0 disables on-chip debug operation. 0 1 setting prohibited 1 0 erases data of flash memory in case of failures in enabling on-chip debugging and authenticating on-chip debug security id. 1 1 does not erases data of flash memory in case of failures in enabling on-chip debugging and authenticating on-chip debug security id. note set the same value as 000c3h to 010c3h when the boot swap operation is used because 000c3h is replaced by 010c3h. caution bits 7 and 0 (ocdenset and ocdersd) can only be specified a value. be sure to set 000010b to bits 6 to 1. remark the value on bits 3 to 1 will be written over when the on-chip debug function is in use and thus it will become unstable after the setting. however, be sure to set the default values (0, 1, and 0) to bits 3 to 1 at setting. chapter 23 option byte preliminary user?s manual u19291ej1v0ud 698 23.4 setting of option byte the user option byte and on-chip debug option byte c an be set using the ra78k0r or pm+ linker option, in addition to describing to the source. when doing so, the c ontents set by using the linke r option take precedence, even if descriptions exist in the source, as mentioned below. see the ra78k0r assembler package user?s manual for how to set the linker option. a software description example of the option byte setting is shown below. opt cseg opt_byte db 10h ; does not use interval inte rrupt of watchdog timer, ; enables watchdog timer operation, ; window open period of watchdog timer is 25%, ; overflow time of watchdog timer is 2 10 /f il , ; stops watchdog timer operation during halt/stop mode db 0fbh ; select 8 mhz or 20 mhz for internal high-speed oscillator ; stops lvi default start function db 0ffh ; reserved area db 85h ; enables on-chip debug operation, does not erase flash memory ; data when security id authorization fails when the boot swap function is used dur ing self programming, 000c0h to 000c3h is switched to 010c0h to 010c3h. describe to 010c0h to 010c3h, therefore, the same values as 000c0h to 000c3h as follows. opt2 cseg at 010c0h db 10h ; does not use interval interrupt of watchdog timer, ; enables watchdog timer operation, ; window open period of watchdog timer is 25%, ; overflow time of watchdog timer is 2 10 /f il , ; stops watchdog timer operation during halt/stop mode db 0fbh ; select 8 mhz or 20 mhz for internal high-speed oscillator ; stops lvi default start function db 0ffh ; reserved area db 85h ; enables on-chip debug operation, does not erase flash memory ; data when security id authorization fails caution to specify the option byte by using assembly language, use opt_ byte as the relocation attribute name of the cseg pseudo instru ction. to specify the option by te to 010c0h to 010c3h in order to use the boot swap function, u se the relocation attribute at to specify an absolute address. preliminary user?s manual u19291ej1v0ud 699 chapter 24 flash memory the 78k0r/kx3-l incorporates the flash memory to whic h a program can be written, erased, and overwritten while mounted on the board. 24.1 writing with flash memory programmer data can be written to the flash memory on-board or o ff-board, by using a dedicated flash memory programmer. (1) on-board programming the contents of the flash memory can be rewritten after the 78k0r/kx3 -l has been mounted on the target system. the connectors that connect the dedicated fl ash memory programmer must be mounted on the target system. (2) off-board programming data can be written to the flash memory with a dedicat ed program adapter (fa series ) before the 78k0r/kx3-l is mounted on the target system. remark the fa series is a product of na ito densei machida mfg. co., ltd. table 24-1. wiring between 78k0r/kx3-l and dedicated flash memory programmer pin no. pin configuration of dedicated flash memory programmer kc3-l 44-pin kc3-l 48-pin kd3-l ke3-l signal name i/o pin function pin name lqfp (10x10) tqfp (7x7) lqfp (10x10) lqfp (12x12), lqfp (10x10), tqfp (7x7) fbga (5x5) si/rxd input receive signal tool0/p40 2 39 4 5 d6 so/txd output transmit signal sck output transfer clock ? ? ? ? ? ? clk output clock output ? ? ? ? ? ? /reset output reset signal reset 3 40 5 6 e7 flmd0 output mode signal flmd0 6 43 8 9 e8 v dd 11 48 13 15 b7 ev dd ? ? ? 16 a8 v dd i/o v dd voltage generation/ power monitoring av ref 32 23 38 47 g1 v ss 10 47 12 13 c7 ev ss ? ? ? 14 b8 gnd ? ground av ss 33 24 39 48 h1 note under development chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 700 examples of the recommended connection when using the adapter for flash memory writing are shown below. figure 24-1. example of wiring ad apter for flash memory writing ( 44-pin products of 78k0r/kc3-l) gnd vdd vdd2 writer interface v dd (1.8 to 5.5 v) gnd si so sck clk /reset flmd0 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 701 figure 24-2. example of wiring ad apter for flash memory writing ( 48-pin products of 78k0r/kc3-l) gnd vdd vdd2 writer interface v dd (1.8 to 5.5 v) gnd si so sck clk /reset flmd0 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 702 figure 24-3. example of wiring adapter for flash memory wr iting (78k0r/kd3-l) gnd vdd vdd2 writer interface v dd (1.8 to 5.5 v) gnd si so sck clk /reset flmd0 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 52 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 22 23 24 25 26 chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 703 figure 24-4. example of wiring adapter for flash memory writing (78k0r/ke3-l) gnd vdd vdd2 writer interface gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 si so sck clk /reset flmd0 v dd (1.8 to 5.5 v) chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 704 24.2 programming environment the environment required for writing a program to the fl ash memory of the 78k0r/kx3-l is illustrated below. figure 24-5. environment for wr iting program to flash memory rs-232c usb 78k0r/kx3-l flmd0 v dd v ss reset tool0 (dedicated single-line uart) host machine dedicated flash memory programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y yy xxxxx xxxxxx xxxx x x x x y y y y s tat v e a host machine that controls the dedicated flash memory programmer is necessary. to interface between the dedicated flash memory pr ogrammer and the 78k0r/kx3-l, the tool0 pin is used for manipulation such as writing and erasing via a dedicated si ngle-line uart. to write the flash memory off-board, a dedicated program adapter (fa series) is necessary. 24.3 communication mode communication between the dedicated flash memory programmer and the 78k0r/kx3-l is established by serial communication using the tool0 pin via a dedicat ed single-line uart of the 78k0r/kx3-l. transfer rate: 115,200 bps to 1,000,000 bps figure 24-6. communication with de dicated flash memory programmer v dd /ev dd v ss /ev ss reset tool0 flmd0 flmd0 v dd gnd /reset si/rxd so/txd dedicated flash memory programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y xxxxx xxxxxx xxxx x x x x y yy y statve 78k0r/kx3-l chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 705 when using the flashpro4 as the dedicated flash memory programmer, the flashpro4, flashpro5 generates the following signals for the 78k0r/kx3-l. for details, refer to the user?s manual for the flashpro4, flashpro5. table 24-2. pin connection flashpro4, flashpro5 78k0r/kx3-l connection signal name i/o pin function pin name flmd0 output mode signal flmd0 v dd i/o v dd voltage generation/power monitoring v dd , ev dd , av ref gnd ? ground v ss , ev ss , av ss clk output clock output ? /reset output reset signal reset si/rxd input receive signal tool0 so/txd output transmit signal sck output transfer clock ? remark : be sure to connect the pin. : the pin does not have to be connected. 24.4 connection of pins on board to write the flash memory on-board, connectors that connect the dedicat ed flash memory programmer must be provided on the target system. first provide a function that selects the no rmal operation mode or flash memory programming mode on the board. when the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after re set. therefore, if the external device does not recognize t he state immediately after reset, the pins must be handled as described below. 24.4.1 flmd0 pin (1) in flash memory programming mode directly connect this pin to a flash memory programmer w hen data is written by the flash memory programmer. this supplies a writing voltage of the v dd level to the flmd0 pin. the flmd0 pin does not have to be pulled down externally because it is internally pulled down by reset. to pull it down externally, use a resistor of 1 k to 200 k . (2) in normal operation mode it is recommended to leave this pin open during normal operation. the flmd0 pin must always be kept at the v ss level before reset release but does not have to be pulled down externally because it is internally pulled down by rese t. however, pulling it down must be kept selected (i.e., flmdpup = ?0?, default value) by using bit 7 (flmdpup ) of the background event control register (bectl) (see 24.5 (1) back ground event control register ). to pull it down externally, use a resistor of 200 k or smaller. self programming and the rewriting of flash memory with the programmer c an be prohibited using hardware, by directly connecting this pin to the v ss pin. chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 706 (3) in self programming mode it is recommended to leave this pin open when using the se lf programming function. to pull it down externally, use a resistor of 100 k to 200 k . in the self programming mode, the setting is swit ched to pull up in the self programming library. figure 24-7. flmd0 pin connection example 78k0r/kx3-l flmd0 dedicated flash memory programmer connection pin 24.4.2 tool0 pin in the flash memory programming mode, connect this pin directly to the dedicated flash memory programmer or pull it up by connecting it to ev dd via an external resistor. when on-chip debugging is enabled in the normal operat ion mode, pull this pin up by connecting it to ev dd via an external resistor, and be sure to keep inputting the v dd level to the tool0 pin before reset is released (pulling down this pin is prohibited). remark the sau and iica pins are not used for communica tion between the 78k0r/kx3-l and dedicated flash memory programmer, because single-line uart is used. 24.4.3 reset pin signal conflict will occur if the reset signal of the ded icated flash memory programmer is connected to the reset pin that is connected to the reset sign al generator on the board. to prevent this conflict, isolate the connection with the reset signal generator. the flash memory will not be correctly prog rammed if the reset signal is input from the user system while the flash memory programming mode is set . do not input any signal ot her than the reset signal of the dedicated flash memory programmer. figure 24-8. signal conflict (reset pin) input pin dedicated flash memory programmer connection pin another device signal conflict output pin in the flash memory programming mode, a signal output by another device will conflict with the signal output by the dedicated flash memory programmer. therefore, isolate the signal of another device. 78k0r/kx3-l chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 707 24.4.4 port pins when the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately afte r reset. if external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to ev dd note or ev ss note via a resistor. note with products without an ev ss pin, connect them to v ss . with products without an ev dd pin, connect them to v dd . 24.4.5 regc pin connect the regc pin to gnd via a capacitor (0.47 to 1 f: target) in the same manner as during normal operation. however, when using the stop mode that has bee n entered since operation of the internal high-speed oscillation clock and external main system clock, 0.47 f is recommended. also, use a capacitor with good characteristics, since it is us ed to stabilize internal voltage. 24.4.6 x1 and x2 pins connect x1 and x2 in the same status as in the normal operation mode. remark in the flash memory programming mode, the internal high-speed oscillation clock (f ih ) is used. 24.4.7 power supply to use the supply voltage output of the flash memory programmer, connect the v dd pin to v dd of the flash memory programmer, and the v ss pin to gnd of the flash memory programmer. to use the on-board supply voltage, connect in compliance with the normal operation mode. however, when using the on-board supp ly voltage, be sure to connect the v dd and v ss pins to v dd and gnd of the flash memory programmer to use the power moni tor function with the flash memory programmer. supply the same other power supplies (ev dd , ev ss , av ref , and av ss ) as those in the normal operation mode. chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 708 24.5 registers controlling flash memory (1) background event control register (bectl) even if the flmd0 pin is not controlled externally, it can be controlled by so ftware with the bectl register to set the self-programming mode. however, depending on the processing of the flmd0 pin, it may not be possible to set the self-programming mode by software. when using bectl, leaving the flmd0 pin open is recommended. when pulling it down externally, use a resistor with a resistance of 100 k or more. in addition, in the normal operation mode, use bectl with the pull down selection. in the self-progra mming mode, the setting is switched to pull up in the self- programming library. the bectl register is set by a 1-bit or 8-bit memory manipula tion instruction. reset input sets this register to 00h. figure 24-9. format of background event control register (bectl) address: fffbeh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 bectl flmdpup 0 0 0 0 0 0 0 flmdpup software control of flmd0 pin 0 selects pull-down 1 selects pull-up 24.6 programming method 24.6.1 controlling flash memory the following figure illustrates the proc edure to manipulate the flash memory. figure 24-10. flash memory manipulation procedure start manipulate flash memory end? yes controlling flmd0 pin and reset pin no end flash memory programming mode is set chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 709 26.6.2 flash memory programming mode to rewrite the contents of t he flash memory by using the dedicated fl ash memory programmer, set the 78k0r/kx3- l in the flash memory programming mode. to set the mode, set the flmd0 pin and tool0 pin to v dd and clear the reset signal. change the mode by using a jumper when writing the flash memory on-board. figure 24-11. flash memory programming mode v dd reset 5.5 v 0 v v dd 0 v flmd0 v dd 0 v tool0 v dd 0 v flash memory programming mode table 24-3. relationship between flmd0 pi n and operation mode after reset release flmd0 operation mode 0 normal operation mode v dd flash memory programming mode 24.6.3 selecting communication mode communication mode of the 78k0r/kx3-l as follows. table 24-4. communication modes standard setting note 1 communication mode port speed frequency multiply rate pins used 1-line mode (dedicated single-line uart) uart-ch0 1 mbps note 2 ? ? tool0 notes 1. selection items for standard settings on gu i of the flash memory programmer. 2. because factors other than the baud rate error, such as the signal waveform slew, also affect uart communication, thoroughly evaluate the slew as well as the baud rate error. chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 710 24.6.4 communication commands the 78k0r/kx3-l communicates with the dedicated flash memory programmer by using commands. the signals sent from the flash memory programmer to the 78k0r/k x3-l are called commands, and the signals sent from the 78k0r/kx3-l to the dedicated flash memory programmer are called response. figure 24-12. communication commands command response 78k0r/kx3-l dedicated flash memory programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve the flash memory control commands of the 78k0r/kx3-l are listed in the table below. all these commands are issued from the programmer and the 78k0r/kx3-l perform processing corresponding to the respective commands. table 24-5. flash memory control commands classification command name function verify verify compares the contents of a specified area of the flash memory with data transmitted from the programmer. chip erase erases the entire flash memory. erase block erase erases a specified area in the flash memory. blank check block blank check checks if a specified block in the flash memory has been correctly erased. write programming writes data to a sp ecified area in the flash memory. silicon signature gets 78k0r/kx3-l information (such as the part number and flash memory configuration). version get gets the 78k0r/kx3-l firmware version. getting information checksum gets the checksum data for a specified area. security security set sets security information. reset used to detect synchronization status of communication. others baud rate set sets baud rate when uart communication mode is selected. the 78k0r/kx3-l returns a response for the command iss ued by the dedicated flash memory programmer. the response names sent from the 78k0r/kx3-l are listed below. table 24-6. response names response name function ack acknowledges command/data. nak acknowledges illegal command/data. chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 711 24.7 security settings the 78k0r/kx3-l supports a security function that prohibits rewriting the user program wr itten to the internal flash memory, so that the program cannot be changed by an unauthorized person. the operations shown below can be performed using the se curity set command. the security setting is valid when the programming mode is set next. ? disabling batch erase (chip erase) execution of the block erase and batch erase (chip eras e) commands for entire blocks in the flash memory is prohibited by this setting during on-board/off-board prog ramming. once execution of the batch erase (chip erase) command is prohibited, all of the prohibition settings (including prohibition of batch erase (chip erase)) can no longer be cancelled. caution after the security setting for the batch erase is set, erasure ca nnot be performed for the device. in addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be wr itten, because th e erase command is disabled. ? disabling block erase execution of the block erase command fo r a specific block in the flash memo ry is prohibited during on-board/off- board programming. however, blocks can be erased by means of self programming. ? disabling write execution of the write and block erase commands for entire blocks in the flash memory is prohibited during on- board/off-board programming. however, blocks can be written by means of self programming. ? disabling rewriting boot cluster 0 execution of the batch erase (chi p erase) command, block erase command, and write command on boot cluster 0 (00000h to 00fffh) in the flash memo ry is prohibited by this setting. the batch erase (chip erase), block eras e, write commands, and rewriting boot cluster 0 are enabled by the default setting when the flash memory is shipped. security can be set by on-board/off-board programming and self programming. each security setting can be used in combination. all the security settings are cleared by exec uting the batch erase (chip erase) command. table 24-7 shows the relationship between the erase and write commands when the 78k0r/kx3-l security function is enabled. remark to prohibit writing and erasing during self-programming, use the flash sealed window function (see 24.8.2 for detail). chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 712 table 24-7. relationship between en abling security function and command (1) during on-board/off-board programming executed command valid security batch erase (chip erase) block erase write prohibition of batch erase (c hip erase) cannot be erased in batch can be performed note . prohibition of block erase can be performed. prohibition of writing can be erased in batch. blocks cannot be erased. cannot be performed. prohibition of rewriting boot cluster 0 cannot be erased in batch boot cluster 0 cannot be erased. boot cluster 0 cannot be written. note confirm that no data has been wri tten to the write area. because data cannot be erased after batch erase (chip erase) is prohibited, do not wr ite data if the data has not been erased. (2) during self programming executed command valid security block erase write prohibition of batch erase (chip erase) prohibition of block erase prohibition of writing blocks can be erased. can be performed. prohibition of rewriting boot cluster 0 boot cluster 0 cannot be erased. boot cluster 0 cannot be written. remark to prohibit writing and erasing during self-programming, use the flash sealed window function (see 24.8.2 for detail). table 24-8. setting security in each programming mode (1) on-board/off-board programming security security setting how to disable security setting prohibition of batch erase (chip er ase) cannot be disabled after set. prohibition of block erase prohibition of writing execute batch erase (chip erase) command prohibition of rewriting boot cluster 0 set via gui of dedicated flash memory programmer, etc. cannot be disabled after set. (2) self programming security security setting how to disable security setting prohibition of batch erase (chip er ase) cannot be disabled after set. prohibition of block erase prohibition of writing prohibition of rewriting boot cluster 0 set by using information library. execute batch erase (chip erase) command during on-board/off-board programming (cannot be disabled during self programming) chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 713 24.8 flash memory programming by self-programming the 78k0r/kx3-l supports a self-programming function that can be used to rewrite the flash memory via a user program. because this function allows a user application to rewrite the flash memory by using the 78k0r/kx3-l self- programming library, it can be used to upgrade the program in the field. if an interrupt occurs during self-programming, self -programming can be temporarily stopped and interrupt servicing can be executed. if an unma sked interrupt request is generated in the ei state, t he request branches directly from the self-programming library to the interrupt routine. after the self-programming mode is later restored, self-programming can be resumed. however, the interrupt response time is differ ent from that of the normal operation mode. cautions 1. the self-programmi ng function cannot be used when th e cpu operates with the subsystem clock. 2. in the self-programming mode, call the self-programming start library (flashstart). 3. to prohibit an interrupt during self-progra mming, in the same way as in the normal operation mode, execute the self-programming lib rary in the state where the ie flag is cleared (0) by the di instruction. to enable an interrupt, clear (0 ) the interrupt mask flag to accept in the state where the ie flag is set (1) by the ei instruction, and then execute the self-programming library. 4. the self-programming function is disabled in the low consumption curre nt mode. for details of the low consumption current mode, see chapter 22 regulator. chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 714 the following figure illustrates a flow of rewriting t he flash memory by using a self programming library. figure 24-13. flow of self programming (rewriting flash memory) flashstart flashenv checkflmd flashblockblankcheck yes no flashblockerase flashwordwrite flashblockverify flashend yes no no flashblockerase flashwordwrite flashblockverify yes start of self programming normal completion setting operating environment normal completion? end of self programming normal completion? normal completion? error chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 715 24.8.1 boot swap function if rewriting the boot area failed by temporary power failure or other reasons, restarti ng a program by resetting or overwriting is disabled due to dat a destruction in the boot area. the boot swap function is used to avoid this problem. before erasing boot cluster 0 note , which is a boot program area, by self-p rogramming, write a new boot program to boot cluster 1 in advance. when the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firmware of the 78k0r/k x3-l, so that boot cluster 1 is used as a boot area. after that, erase or write t he original boot program area, boot cluster 0. as a result, even if a power failure occurs while the bo ot programming area is being rewritten, the program is executed correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next. note a boot cluster is a 4 kb area and boot clusters 0 and 1 are swapped by the boot swap function. figure 24-14. boot swap function boot program (boot cluster 0) new boot program (boot cluster 1) user program self-programming to boot cluster 1 self-programming to boot cluster 0 execution of boot swap by firmware user program boot program (boot cluster 0) user program new user program (boot cluster 0) new boot program (boot cluster 1) user program new boot program (boot cluster 1) boot program (boot cluster 0) user program xxxxxh 02000h 00000h 01000h boot boot boot boot in an example of above figure, it is as follows. boot cluster 0: boot program area before boot swap boot cluster 1: boot program area after boot swap chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 716 figure 24-15. example of executing boot swapping 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 boot cluster 1 booted by boot cluster 0 block number erasing block 4 boot cluster 0 program 01000h 00000h boot program program program program boot program boot program boot program program program program boot program boot program boot program boot program boot program boot program boot program boot program program program program boot program boot program boot program boot program boot program boot program boot program boot program erasing block 5 erasing block 6 erasing block 7 boot program boot program boot program boot program boot program boot program boot program boot program boot program boot program boot program boot program boot program boot program booted by boot cluster 1 01000h 00000h erasing block 6 erasing block 7 erasing block 4 erasing block 5 boot swap writing blocks 4 to 7 writing blocks 4 to 7 01000h 00000h new boot program new program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new program new program new program chapter 24 flash memory preliminary user?s manual u19291ej1v0ud 717 24.8.2 flash shield window function the flash shield window function is provided as one of the security functions for self-programming. writing and erasing to the flash memory within the range specified as a window are enabled during self- programming, and writing and erasing to the flash memory outside the specified range are prohibited. the window range can be expanded or reduced by setting and change during on-board/off-board programming and self-programming. however, the shield function be comes effective only during self-programming. in on- board/off-board programming, writing and erasing to the flash memory outside the window range are enabled. caution if the rewrite-prohibited area of the boot cl uster 0 overlaps with the fl ash shield window range, prohibition to rewrite the bo ot cluster 0 takes priority. table 24-9. relationship between flash shield wi ndow function setting/change methods and commands execution commands programming conditions window range setting/change methods block erase write self-programming specify the starting and ending blocks by the set information library. block erasing is enabled only within the window range. writing is enabled only within the range of window range. on-board/off-board programming specify the starting and ending blocks on gui of dedicated flash memory programmer, etc. block erasing is enabled also outside the window range. writing is enabled also outside the window range. remark see 24.7 security settings to prohibit writing/erasing during on-board/off-board programming. preliminary user?s manual u19291ej1v0ud 718 chapter 25 on-chip debug function 25.1 connecting qb-mini2 to 78k0r/kx3-l the 78k0r/kx3-l uses the v dd , flmd0, reset, tool0, tool1 note 1 , and v ss pins to communicate with the host machine via an on-chip debug emulator (qb-mini2). caution the 78k0r/kx3-l has an on-chip debug fu nction, which is provided for development and evaluation. do not use the on-chip debug func tion in products designated for mass production, because the guaranteed nu mber of rewritable times of the flash memory may be exceeded when this function is used, and product reliability th erefore cannot be guaranteed. nec electronics is not liable for problems occurring when the on-chip debug function is used. figure 25-1. connection exampl e of qb-mini2 and 78k0r/kx3-l v dd flmd0 tool0 reset_in clk_in rxd note 2 flmd0 reset v dd reset_out qb-mini2 target connector gnd tool1 note 1 v ss ev dd txd note 2 78k0r/kx3-l target reset notes 1. connection is not required for communication in 1-line mode but required for communication in 2-line mode. at this time, perform necessary connections according to table 2-2 connection of unused pins since tool1 is an unused pin when qb-mini2 is unconnected. 2. connecting the dotted line is not necessary si nce rxd and txd are shorted within qb-min2. when using the other flash memory programmer, rxd and txd may not be shorted within the programmer. in this case, they must be sh orted on the target system. remark the flmd0 pin is recommended to be open for self-programming in on-chip debugging. to pull down externally, use a resistor of 100 k or more. 1-line mode (single line uart) using the tool0 pin or 2- line mode using the tool0 and tool1 pins is used for serial communication for flash memory programming, 1-line mode is used. 1-line mode or 2-line mode is used for on- chip debugging. table 25-1 lists the differences between 1-line mode and 2-line mode. chapter 25 on-chip debug function preliminary user?s manual u19291ej1v0ud 719 table 25-1. lists the differences be tween 1-line mode and 2-line mode. communicat ion mode flash memory programming function debugging function 1-line mode available ? pseudo real-time ram monitor (rrm) function not supported. ? dmm function (rewriting memory in run) not supported. ? the debugger speed is two to four times slower than 2-line mode. 2-line mode none ? pseudo real-time ram monitor (rrm) function supported ? dmm function (rewriting memory in run) supported remark 2-line mode is not used for flash programming, howeve r, even if tool1 pin is connected with clk_in of qb-mini2, writing is perform ed normally with no problem. 25.2 on-chip debug security id the 78k0r/kx3-l has an on-chip debug operation c ontrol bit in the flash memory at 000c3h (see chapter 23 option byte ) and an on-chip debug security id setting area at 000c4h to 000cdh, to prevent third parties from reading memory content. when the boot swap function is used, also set a value t hat is the same as that of 010c3h and 010c4h to 010cdh in advance, because 000c3h, 000c4h to 000cdh and 010c3h, and 010c4h to 010cdh are switched. for details on the on-chip debug security id, refer to the qb-mini2 on-chip debug emulator with programming function user?s manual (u18371e) . table 25-2. on-chip debug security id address on-chip debug security id 000c4h to 000cdh 010c4h to 010cdh any id code of 10 bytes 25.3 securing of user resources to perform communication between the 78k0r/kx3-l and qb -mini2, as well as each d ebug function, the securing of memory space must be done beforehand. if nec electronics assembler ra78k0r or compiler cc78k0r is used, the items can be set by using linker options. (1) securement of memory space the shaded portions in figure 25-2 are the areas reserv ed for placing the debug monitor program, so user programs or data cannot be allocated in these spaces . when using the on-chip deb ug function, these spaces must be secured so as not to be used by the user progra m. moreover, this area must not be rewritten by the user program. chapter 25 on-chip debug function preliminary user?s manual u19291ej1v0ud 720 figure 25-2. memory spaces where de bug monitor programs are allocated (1 kb) : area used for on-chip debugging note 1 note 2 internal rom use prohibited internal ram internal rom area boot cruster 1 debug monitor area (10 bytes) debug monitor area (2 bytes) debug monitor area (2 bytes) security id area (10 bytes) debug monitor area (10 bytes) security id area (10 bytes) on-chip debug option byte area (1 byte) on-chip debug option byte area (1 byte) note 2 stack area for debugging (6 bytes) note 3 02000h 010d8h 010ceh 010c4h 010c3h 01002h 01000h 000d8h 000ceh 000c4h 000c3h 00002h 00000h internal ram area boot cruster 0 notes 1. address differs depending on products as follows. products ( ): internal rom address of note 1 pd78f1000 (16 kb) 03c00h to 03fffh pd78f1001, 78f1004, 78f1007 (32 kb) 07c00h to 07fffh pd78f1002, 78f1005, 78f1008 (48 kb) 0bc00h to 0bfffh pd78f1003, 78f1006, 78f1009 (64 kb) 0fc00h to 0ffffh 2. in debugging, reset vector is rewritten to address allocated to a monitor program. 3. since this area is allocated immediately before the stack area, the address of this area varies depending on the stack increase and decrease. that is, 6 ex tra bytes are consumed for the stack area used. for details of the way to secure of the memory space, refer to the qb-mini2 on-chip debug emulator with programming function u ser?s manual (u18371e) . preliminary user?s manual u19291ej1v0ud 721 chapter 26 bcd correction circuit 26.1 bcd correction circuit function the result of addition/subtraction of the bcd (binary-coded decimal) code and bcd code can be obtained as bcd code with this circuit. the decimal correction operation result is obtained by perf orming addition/subtraction having the a register as the operand and then adding/ subtracting the bcdadj register. 26.2 registers used by bcd correction circuit the bcd correction circuit uses the following registers. ? bcd correction result register (bcdadj) (1) bcd correction result register (bcdadj) the bcdadj register stores correct ion values for obtaini ng the add/subtract resu lt as bcd code through add/subtract instructions using t he a register as the operand. the value read from the bcdadj regist er varies depending on the value of the a register when it is read and those of the cy and ac flags. bcdadj is read by an 8-bit memory manipulation instruction. reset input sets this register to undefined. figure 26-1. format of bcd correct ion result register (bcdadj) address: f00feh after reset: undefined r symbol 7 6 5 4 3 2 1 0 bcdadj chapter 26 bcd correction circuit preliminary user?s manual u19291ej1v0ud 722 26.3 bcd correction circuit operation the basic operation of the bcd correction circuit is as follows. (1) addition: calculating the result of adding a bcd code value and another bcd code value by using a bcd code value <1> the bcd code value to which addition is performed is stored in the a register. <2> by adding the value of the a register and the second operand (value of one more bcd code to be added) as are in binary, the binary operation result is stored in the a register and the correction value is stored in the bcdadj register. <3> decimal correction is performed by adding in binary t he value of the a register (addition result in binary) and the bcdadj register (correction value), and the correction result is stored in the a register and cy register. caution the value read from the bcdadj regist er varies depending on the value of the a register when it is read and those of th e cy and ac flags. therefore, execute the instruction <3> after the instru ction <2> instead of executing any other instructions. to perform bcd correction in the interrupt en abled state, saving and restoring the a register is required within the interrupt func tion. psw (cy flag and ac flag) is restored by the reti instruction. an example is shown below. examples 1: 99 + 89 = 188 instruction a register cy register ac flag bcdadj register mov a, #99h ; <1> 99h ? ? ? add a, #89h ; <2> 22h 1 1 66h add a, !bcdadj ; <3> 88h 1 0 ? examples 2: 85 + 15 = 100 instruction a register cy register ac flag bcdadj register mov a, #85h ; <1> 85h ? ? ? add a, #15h ; <2> 9ah 0 0 06h add a, !bcdadj ; <3> 00h 1 1 ? examples 3: 80 + 80 = 160 instruction a register cy register ac flag bcdadj register mov a, #80h ; <1> 80h ? ? ? add a, #80h ; <2> 00h 1 0 60h add a, !bcdadj ; <3> 60h 1 0 ? chapter 26 bcd correction circuit preliminary user?s manual u19291ej1v0ud 723 (2) subtraction: calculating the r esult of subtracting a bcd code valu e from another bcd code value by using a bcd code value <1> the bcd code value from which subtracti on is performed is stored in the a register. <2> by subtracting the value of the second operand (value of bcd code to be subtracted) from the a register as is in binary, the calculation result in binary is st ored in the a register, and the correction value is stored in the bcdadj register. <3> decimal correction is performed by subtracting the va lue of the bcdadj register (correction value) from the a register (subtraction result in binary) in binary, and the correction result is stored in the a register and cy register. caution the value read from the bcdadj regist er varies depending on the value of the a register when it is read and those of th e cy and ac flags. therefore, execute the instruction <3> after the instru ction <2> instead of executing any other instructions. to perform bcd correction in the interrupt en abled state, saving and restoring the a register is required within the interrupt func tion. psw (cy flag and ac flag) is restored by the reti instruction. an example is shown below. example: 91 ? 52 = 39 instruction a register cy register ac flag bcdadj register mov a, #91h ; <1> 91h ? ? ? sub a, #52h ; <2> 3fh 0 1 06h sub a, !bcdadj ; <3> 39h 0 0 ? preliminary user?s manual u19291ej1v0ud 724 chapter 27 instruction set this chapter lists the instructions in the 78k0r microcont roller instruction set. for details of each operation and operation code, refer to the separate document 78k0r microcontrollers instru ctions user?s manual (u17792e) . remark the shaded parts of the tables in table 27-5 operation list indicate the operation or instruction format that is newly added for the 78k0r microcontrollers. 27.1 conventions used in operation list 27.1.1 operand identifier s and specification methods operands are described in the ?operand? column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler s pecifications for details). when there are two or more description methods, select one of them. al phabetic letters in capitals and the sym bols, #, !, !!, $, $!, [ ], and es: are keywords and are described as they are. each symbol has the following meaning. ? #: immediate data specification ? !: 16-bit absolute address specification ? !!: 20-bit absolute address specification ? $: 8-bit relative address specification ? $!: 16-bit relative address specification ? [ ]: indirect address specification ? es:: extension address specification in the case of immediate data, describe an appropriate nu meric value or a label. when using a label, be sure to describe the #, !, !!, $, $!, [ ], and es: symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1 , r2, etc.) can be used for description. table 27-1. operand identifi ers and specification methods identifier description method r rp sfr sfrp x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special-function register symbol (sfr symbol) special-function register sy mbols (16-bit manipulatable sf r symbol. even addresses only note ) saddr saddrp ffe20h to fff1fh immediate data or labels ffe20h to ff1fh immediate data or labels (even addresses only note ) addr20 addr16 addr5 00000h to fffffh immediate data or labels 0000h to ffffh immediate data or labels (only ev en addresses for 16-bit data transfer instructions note ) 0080h to 00bfh immediate data or labels (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label rbn rb0 to rb3 note bit 0 = 0 when an odd address is specified. remark for special-function register symbol, see table 3-5 sfr list and table 3-6 extended sfr (2nd sfr) list . chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 725 27.1.2 description of operation column the operation when the instruction is exec uted is shown in the ?operation? colu mn using the following symbols. table 27-2. symbols in ?operation? column symbol function a a register; 8-bit accumulator x x register b b register c c register d d register e e register h h register l l register es es register cs cs register ax ax register pair; 16-bit accumulator bc bc register pair de de register pair hl hl register pair pc program counter sp stack pointer psw program status word cy carry flag ac auxiliary carry flag z zero flag rbs register bank select flag ie interrupt request enable flag () memory contents indicated by address or register contents in parentheses x h , x l x s , x h , x l 16-bit registers: x h = higher 8 bits, x l = lower 8 bits 20-bit registers: x s = (bits 19 to 16), x h = (bits 15 to 8), x l = (bits 7 to 0) logical product (and) logical sum (or) exclusive logical sum (exclusive or) ? inverted data addr5 16-bit immediate data (even addresses only in 0080h to 00bfh) addr16 16-bit immediate data addr20 20-bit immediate data jdisp8 signed 8-bit data (displacement value) jdisp16 signed 16-bit data (displacement value) chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 726 27.1.3 description of flag operation column the change of the flag value when the in struction is executed is shown in t he ?flag? column using the following symbols. table 27-3. symbols in ?flag? column symbol change of flag value (blank) 0 1 r unchanged cleared to 0 set to 1 set/cleared according to the result previously saved value is restored 27.1.4 prefix instruction instructions with ?es:? have a prefix operation code as a prefix to extend t he accessible data area to the 1 mb space (00000h to fffffh), by adding the es register va lue to the 64 kb space from f0000h to fffffh. when a prefix operation code is attached as a pr efix to the target instruction, only one instruction immediately after the prefix operation code is executed as the addr esses with the es register value added. table 27-4. use example of prefix operation code opcode instruction 1 2 3 4 5 mov !addr16, #byte cfh !addr16 #byte ? mov es:!addr16, #byte 11h cfh !addr16 #byte mov a, [hl] 8bh ? ? ? ? mov a, es:[hl] 11h 8bh ? ? ? caution set the es register value with mov es, a, etc., before executing th e prefix instruction. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 727 27.2 operation list table 27-5. operation list (1/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy r, #byte 2 1 ? r byte saddr, #byte 3 1 ? (saddr) byte sfr, #byte 3 1 ? sfr byte !addr16, #byte 4 1 ? (addr16) byte a, r note 3 1 1 ? a r r, a note 3 1 1 ? r a a, saddr 2 1 ? a (saddr) saddr, a 2 1 ? (saddr) a a, sfr 2 1 ? a sfr sfr, a 2 1 ? sfr a a, !addr16 3 1 4 a (addr16) !addr16, a 3 1 ? (addr16) a psw, #byte 3 3 ? psw byte a, psw 2 1 ? a psw psw, a 2 3 ? psw a es, #byte 2 1 ? es byte es, saddr 3 1 ? es (saddr) a, es 2 1 ? a es es, a 2 1 ? es a cs, #byte 3 1 ? cs byte a, cs 2 1 ? a cs cs, a 2 1 ? cs a a, [de] 1 1 4 a (de) [de], a 1 1 ? (de) a [de + byte], #byte 3 1 ? (de + byte) byte a, [de + byte] 2 1 4 a (de + byte) [de + byte], a 2 1 ? (de + byte) a a, [hl] 1 1 4 a (hl) [hl], a 1 1 ? (hl) a 8-bit data transfer mov [hl + byte], #byte 3 1 ? (hl + byte) byte notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 728 table 27-5. operation list (2/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, [hl + byte] 2 1 4 a (hl + byte) [hl + byte], a 2 1 ? (hl + byte) a a, [hl + b] 2 1 4 a (hl + b) [hl + b], a 2 1 ? (hl + b) a a, [hl + c] 2 1 4 a (hl + c) [hl + c], a 2 1 ? (hl + c) a word[b], #byte 4 1 ? (b + word) byte a, word[b] 3 1 4 a (b + word) word[b], a 3 1 ? (b + word) a word[c], #byte 4 1 ? (c + word) byte a, word[c] 3 1 4 a (c + word) word[c], a 3 1 ? (c + word) a word[bc], #byte 4 1 ? (bc + word) byte a, word[bc] 3 1 4 a (bc + word) word[bc], a 3 1 ? (bc + word) a [sp + byte], #byte 3 1 ? (sp + byte) byte a, [sp + byte] 2 1 ? a (sp + byte) [sp + byte], a 2 1 ? (sp + byte) a b, saddr 2 1 ? b (saddr) b, !addr16 3 1 4 b (addr16) c, saddr 2 1 ? c (saddr) c, !addr16 3 1 4 c (addr16) x, saddr 2 1 ? x (saddr) x, !addr16 3 1 4 x (addr16) es:!addr16, #byte 5 2 ? (es, addr16) byte a, es:!addr16 4 2 5 a (es, addr16) es:!addr16, a 4 2 ? (es, addr16) a a, es:[de] 2 2 5 a (es, de) es:[de], a 2 2 ? (es, de) a es:[de + byte],#byte 4 2 ? ((es, de) + byte) byte a, es:[de + byte] 3 2 5 a ((es, de) + byte) 8-bit data transfer mov es:[de + byte], a 3 2 ? ((es, de) + byte) a notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 729 table 27-5. operation list (3/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, es:[hl] 2 2 5 a (es, hl) es:[hl], a 2 2 ? (es, hl) a es:[hl + byte],#byte 4 2 ? ((es, hl) + byte) byte a, es:[hl + byte] 3 2 5 a ((es, hl) + byte) es:[hl + byte], a 3 2 ? ((es, hl) + byte) a a, es:[hl + b] 3 2 5 a ((es, hl) + b) es:[hl + b], a 3 2 ? ((es, hl) + b) a a, es:[hl + c] 3 2 5 a ((es, hl) + c) es:[hl + c], a 3 2 ? ((es, hl) + c) a es:word[b], #byte 5 2 ? ((es, b) + word) byte a, es:word[b] 4 2 5 a ((es, b) + word) es:word[b], a 4 2 ? ((es, b) + word) a es:word[c], #byte 5 2 ? ((es, c) + word) byte a, es:word[c] 4 2 5 a ((es, c) + word) es:word[c], a 4 2 ? ((es, c) + word) a es:word[bc], #byte 5 2 ? ((es, bc) + word) byte a, es:word[bc] 4 2 5 a ((es, bc) + word) es:word[bc], a 4 2 ? ((es, bc) + word) a b, es:!addr16 4 2 5 b (es, addr16) c, es:!addr16 4 2 5 c (es, addr16) mov x, es:!addr16 4 2 5 x (es, addr16) a, r note 3 1 (r = x) 2 (other than r = x) 1 ? a r a, saddr 3 2 ? a (saddr) a, sfr 3 2 ? a sfr a, !addr16 4 2 ? a (addr16) a, [de] 2 2 ? a (de) a, [de + byte] 3 2 ? a (de + byte) a, [hl] 2 2 ? a (hl) a, [hl + byte] 3 2 ? a (hl + byte) a, [hl + b] 2 2 ? a (hl + b) 8-bit data transfer xch a, [hl + c] 2 2 ? a (hl + c) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 730 table 27-5. operation list (4/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, es:!addr16 5 3 ? a (es, addr16) a, es:[de] 3 3 ? a (es, de) a, es:[de + byte] 4 3 ? a ((es, de) + byte) a, es:[hl] 3 3 ? a (es, hl) a, es:[hl + byte] 4 3 ? a ((es, hl) + byte) a, es:[hl + b] 3 3 ? a ((es, hl) + b) xch a, es:[hl + c] 3 3 ? a ((es, hl) + c) a 1 1 ? a 01h x 1 1 ? x 01h b 1 1 ? b 01h c 1 1 ? c 01h saddr 2 1 ? (saddr) 01h !addr16 3 1 ? (addr16) 01h oneb es:!addr16 4 2 ? (es, addr16) 01h a 1 1 ? a 00h x 1 1 ? x 00h b 1 1 ? b 00h c 1 1 ? c 00h saddr 2 1 ? (saddr) 00h !addr16 3 1 ? (addr16) 00h clrb es:!addr16 4 2 ? (es,addr16) 00h [hl + byte], x 3 1 ? (hl + byte) x 8-bit data transfer movs es:[hl + byte], x 4 2 ? (es, hl + byte) x rp, #word 3 1 ? rp word saddrp, #word 4 1 ? (saddrp) word sfrp, #word 4 1 ? sfrp word ax, saddrp 2 1 ? ax (saddrp) saddrp, ax 2 1 ? (saddrp) ax ax, sfrp 2 1 ? ax sfrp sfrp, ax 2 1 ? sfrp ax ax, rp note 3 1 1 ? ax rp 16-bit data transfer movw rp, ax note 3 1 1 ? rp ax notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except rp = ax remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 731 table 27-5. operation list (5/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy ax, !addr16 3 1 4 ax (addr16) !addr16, ax 3 1 ? (addr16) ax ax, [de] 1 1 4 ax (de) [de], ax 1 1 ? (de) ax ax, [de + byte] 2 1 4 ax (de + byte) [de + byte], ax 2 1 ? (de + byte) ax ax, [hl] 1 1 4 ax (hl) [hl], ax 1 1 ? (hl) ax ax, [hl + byte] 2 1 4 ax (hl + byte) [hl + byte], ax 2 1 ? (hl + byte) ax ax, word[b] 3 1 4 ax (b + word) word[b], ax 3 1 ? (b + word) ax ax, word[c] 3 1 4 ax (c + word) word[c], ax 3 1 ? (c + word) ax ax, word[bc] 3 1 4 ax (bc + word) word[bc], ax 3 1 ? (bc + word) ax ax, [sp + byte] 2 1 ? ax (sp + byte) [sp + byte], ax 2 1 ? (sp + byte) ax bc, saddrp 2 1 ? bc (saddrp) bc, !addr16 3 1 4 bc (addr16) de, saddrp 2 1 ? de (saddrp) de, !addr16 3 1 4 de (addr16) hl, saddrp 2 1 ? hl (saddrp) hl, !addr16 3 1 4 hl (addr16) ax, es:!addr16 4 2 5 ax (es, addr16) es:!addr16, ax 4 2 ? (es, addr16) ax ax, es:[de] 2 2 5 ax (es, de) es:[de], ax 2 2 ? (es, de) ax ax, es:[de + byte] 3 2 5 ax ((es, de) + byte) es:[de + byte], ax 3 2 ? ((es, de) + byte) ax ax, es:[hl] 2 2 5 ax (es, hl) 16-bit data transfer movw es:[hl], ax 2 2 ? (es, hl) ax notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 732 table 27-5. operation list (6/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy ax, es:[hl + byte] 3 2 5 ax ((es, hl) + byte) es:[hl + byte], ax 3 2 ? ((es, hl) + byte) ax ax, es:word[b] 4 2 5 ax ((es, b) + word) es:word[b], ax 4 2 ? ((es, b) + word) ax ax, es:word[c] 4 2 5 ax ((es, c) + word) es:word[c], ax 4 2 ? ((es, c) + word) ax ax, es:word[bc] 4 2 5 ax ((es, bc) + word) es:word[bc], ax 4 2 ? ((es, bc) + word) ax bc, es:!addr16 4 2 5 bc (es, addr16) de, es:!addr16 4 2 5 de (es, addr16) movw hl, es:!addr16 4 2 5 hl (es, addr16) xchw ax, rp note 3 1 1 ? ax rp ax 1 1 ? ax 0001h onew bc 1 1 ? bc 0001h ax 1 1 ? ax 0000h 16-bit data transfer clrw bc 1 1 ? bc 0000h a, #byte 2 1 ? a, cy a + byte saddr, #byte 3 2 ? (saddr), cy (saddr) + byte a, r note 4 2 1 ? a, cy a + r r, a 2 1 ? r, cy r + a a, saddr 2 1 ? a, cy a + (saddr) a, !addr16 3 1 4 a, cy a + (addr16) a, [hl] 1 1 4 a, cy a + (hl) a, [hl + byte] 2 1 4 a, cy a + (hl + byte) a, [hl + b] 2 1 4 a, cy a + (hl + b) a, [hl + c] 2 1 4 a, cy a + (hl + c) a, es:!addr16 4 2 5 a, cy a + (es, addr16) a, es:[hl] 2 2 5 a,cy a + (es, hl) a, es:[hl + byte] 3 2 5 a,cy a + ((es, hl) + byte) a, es:[hl + b] 3 2 5 a,cy a + ((es, hl) + b) 8-bit operation add a, es:[hl + c] 3 2 5 a,cy a + ((es, hl) + c) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except rp = ax 4. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 733 table 27-5. operation list (7/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, #byte 2 1 ? a, cy a + byte + cy saddr, #byte 3 2 ? (saddr), cy (saddr) + byte + cy a, r note 3 2 1 ? a, cy a + r + cy r, a 2 1 ? r, cy r + a + cy a, saddr 2 1 ? a, cy a + (saddr) + cy a, !addr16 3 1 4 a, cy a + (addr16) + cy a, [hl] 1 1 4 a, cy a + (hl) + cy a, [hl + byte] 2 1 4 a, cy a + (hl + byte) + cy a, [hl + b] 2 1 4 a, cy a + (hl + b) + cy a, [hl + c] 2 1 4 a, cy a + (hl + c) + cy a, es:!addr16 4 2 5 a, cy a + (es, addr16) + cy a, es:[hl] 2 2 5 a, cy a + (es, hl) + cy a, es:[hl + byte] 3 2 5 a, cy a + ((es, hl) + byte) + cy a, es:[hl + b] 3 2 5 a, cy a + ((es, hl) + b) + cy addc a, es:[hl + c] 3 2 5 a, cy a + ((es, hl) + c) + cy a, #byte 2 1 ? a, cy a ? byte saddr, #byte 3 2 ? (saddr), cy (saddr) ? byte a, r note 3 2 1 ? a, cy a ? r r, a 2 1 ? r, cy r ? a a, saddr 2 1 ? a, cy a ? (saddr) a, !addr16 3 1 4 a, cy a ? (addr16) a, [hl] 1 1 4 a, cy a ? (hl) a, [hl + byte] 2 1 4 a, cy a ? (hl + byte) a, [hl + b] 2 1 4 a, cy a ? (hl + b) a, [hl + c] 2 1 4 a, cy a ? (hl + c) a, es:!addr16 4 2 5 a, cy a ? (es:addr16) a, es:[hl] 2 2 5 a, cy a ? (es:hl) a, es:[hl + byte] 3 2 5 a, cy a ? ((es:hl) + byte) a, es:[hl + b] 3 2 5 a, cy a ? ((es:hl) + b) 8-bit operation sub a, es:[hl + c] 3 2 5 a, cy a ? ((es:hl) + c) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 734 table 27-5. operation list (8/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, #byte 2 1 ? a, cy a ? byte ? cy saddr, #byte 3 2 ? (saddr), cy (saddr) ? byte ? cy a, r note 3 2 1 ? a, cy a ? r ? cy r, a 2 1 ? r, cy r ? a ? cy a, saddr 2 1 ? a, cy a ? (saddr) ? cy a, !addr16 3 1 4 a, cy a ? (addr16) ? cy a, [hl] 1 1 4 a, cy a ? (hl) ? cy a, [hl + byte] 2 1 4 a, cy a ? (hl + byte) ? cy a, [hl + b] 2 1 4 a, cy a ? (hl + b) ? cy a, [hl + c] 2 1 4 a, cy a ? (hl + c) ? cy a, es:!addr16 4 2 5 a, cy a ? (es:addr16) ? cy a, es:[hl] 2 2 5 a, cy a ? (es:hl) ? cy a, es:[hl + byte] 3 2 5 a, cy a ? ((es:hl) + byte) ? cy a, es:[hl + b] 3 2 5 a, cy a ? ((es:hl) + b) ? cy subc a, es:[hl + c] 3 2 5 a, cy a ? ((es:hl) + c) ? cy a, #byte 2 1 ? a a byte saddr, #byte 3 2 ? (saddr) (saddr) byte a, r note 3 2 1 ? a a r r, a 2 1 ? r r a a, saddr 2 1 ? a a (saddr) a, !addr16 3 1 4 a a (addr16) a, [hl] 1 1 4 a a (hl) a, [hl + byte] 2 1 4 a a (hl + byte) a, [hl + b] 2 1 4 a a (hl + b) a, [hl + c] 2 1 4 a a (hl + c) a, es:!addr16 4 2 5 a a (es:addr16) a, es:[hl] 2 2 5 a a (es:hl) a, es:[hl + byte] 3 2 5 a a ((es:hl) + byte) a, es:[hl + b] 3 2 5 a a ((es:hl) + b) 8-bit operation and a, es:[hl + c] 3 2 5 a a ((es:hl) + c) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 735 table 27-5. operation list (9/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, #byte 2 1 ? a a byte saddr, #byte 3 2 ? (saddr) (saddr) byte a, r note 3 2 1 ? a a r r, a 2 1 ? r r a a, saddr 2 1 ? a a (saddr) a, !addr16 3 1 4 a a (addr16) a, [hl] 1 1 4 a a (hl) a, [hl + byte] 2 1 4 a a (hl + byte) a, [hl + b] 2 1 4 a a (hl + b) a, [hl + c] 2 1 4 a a (hl + c) a, es:!addr16 4 2 5 a a (es:addr16) a, es:[hl] 2 2 5 a a (es:hl) a, es:[hl + byte] 3 2 5 a a ((es:hl) + byte) a, es:[hl + b] 3 2 5 a a ((es:hl) + b) or a, es:[hl + c] 3 2 5 a a ((es:hl) + c) a, #byte 2 1 ? a a byte saddr, #byte 3 2 ? (saddr) (saddr) byte a, r note 3 2 1 ? a a r r, a 2 1 ? r r a a, saddr 2 1 ? a a (saddr) a, !addr16 3 1 4 a a (addr16) a, [hl] 1 1 4 a a (hl) a, [hl + byte] 2 1 4 a a (hl + byte) a, [hl + b] 2 1 4 a a (hl + b) a, [hl + c] 2 1 4 a a (hl + c) a, es:!addr16 4 2 5 a a (es:addr16) a, es:[hl] 2 2 5 a a (es:hl) a, es:[hl + byte] 3 2 5 a a ((es:hl) + byte) a, es:[hl + b] 3 2 5 a a ((es:hl) + b) 8-bit operation xor a, es:[hl + c] 3 2 5 a a ((es:hl) + c) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 736 table 27-5. operation list (10/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, #byte 2 1 ? a ? byte saddr, #byte 3 1 ? (saddr) ? byte a, r note 3 2 1 ? a ? r r, a 2 1 ? r ? a a, saddr 2 1 ? a ? (saddr) a, !addr16 3 1 4 a ? (addr16) a, [hl] 1 1 4 a ? (hl) a, [hl + byte] 2 1 4 a ? (hl + byte) a, [hl + b] 2 1 4 a ? (hl + b) a, [hl + c] 2 1 4 a ? (hl + c) !addr16, #byte 4 1 4 (addr16) ? byte a, es:!addr16 4 2 5 a ? (es:addr16) a, es:[hl] 2 2 5 a ? (es:hl) a, es:[hl + byte] 3 2 5 a ? ((es:hl) + byte) a, es:[hl + b] 3 2 5 a ? ((es:hl) + b) a, es:[hl + c] 3 2 5 a ? ((es:hl) + c) cmp es:!addr16, #byte 5 2 5 (es:addr16) ? byte a 1 1 ? a ? 00h x 1 1 ? x ? 00h b 1 1 ? b ? 00h c 1 1 ? c ? 00h saddr 2 1 ? (saddr) ? 00h !addr16 3 1 4 (addr16) ? 00h cmp0 es:!addr16 4 2 5 (es:addr16) ? 00h x, [hl + byte] 3 1 4 x ? (hl + byte) 8-bit operation cmps x, es:[hl + byte] 4 2 5 x ? ((es:hl) + byte) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 737 table 27-5. operation list (11/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy ax, #word 3 1 ? ax, cy ax + word ax, ax 1 1 ? ax, cy ax + ax ax, bc 1 1 ? ax, cy ax + bc ax, de 1 1 ? ax, cy ax + de ax, hl 1 1 ? ax, cy ax + hl ax, saddrp 2 1 ? ax, cy ax + (saddrp) ax, !addr16 3 1 4 ax, cy ax + (addr16) ax, [hl+byte] 3 1 4 ax, cy ax + (hl + byte) ax, es:!addr16 4 2 5 ax, cy ax + (es:addr16) addw ax, es: [hl+byte] 4 2 5 ax, cy ax + ((es:hl) + byte) ax, #word 3 1 ? ax, cy ax ? word ax, bc 1 1 ? ax, cy ax ? bc ax, de 1 1 ? ax, cy ax ? de ax, hl 1 1 ? ax, cy ax ? hl ax, saddrp 2 1 ? ax, cy ax ? (saddrp) ax, !addr16 3 1 4 ax, cy ax ? (addr16) ax, [hl+byte] 3 1 4 ax, cy ax ? (hl + byte) ax, es:!addr16 4 2 5 ax, cy ax ? (es:addr16) subw ax, es: [hl+byte] 4 2 5 ax, cy ax ? ((es:hl) + byte) ax, #word 3 1 ? ax ? word ax, bc 1 1 ? ax ? bc ax, de 1 1 ? ax ? de ax, hl 1 1 ? ax ? hl ax, saddrp 2 1 ? ax ? (saddrp) ax, !addr16 3 1 4 ax ? (addr16) ax, [hl+byte] 3 1 4 ax ? (hl + byte) ax, es:!addr16 4 2 5 ax ? (es:addr16) 16-bit operation cmpw ax, es: [hl+byte] 4 2 5 ax ? ((es:hl) + byte) multiply mulu x 1 1 ? ax a x notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 738 table 27-5. operation list (12/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy r 1 1 ? r r + 1 saddr 2 2 ? (saddr) (saddr) + 1 !addr16 3 2 ? (addr16) (addr16) + 1 [hl+byte] 3 2 ? (hl+byte) (hl+byte) + 1 es:!addr16 4 3 ? (es, addr16) (es, addr16) + 1 inc es: [hl+byte] 4 3 ? ((es:hl) + byte) ((es:hl) + byte) + 1 r 1 1 ? r r ? 1 saddr 2 2 ? (saddr) (saddr) ? 1 !addr16 3 2 ? (addr16) (addr16) ? 1 [hl+byte] 3 2 ? (hl+byte) (hl+byte) ? 1 es:!addr16 4 3 ? (es, addr16) (es, addr16) ? 1 dec es: [hl+byte] 4 3 ? ((es:hl) + byte) ((es:hl) + byte) ? 1 rp 1 1 ? rp rp + 1 saddrp 2 2 ? (saddrp) (saddrp) + 1 !addr16 3 2 ? (addr16) (addr16) + 1 [hl+byte] 3 2 ? (hl+byte) (hl+byte) + 1 es:!addr16 4 3 ? (es, addr16) (es, addr16) + 1 incw es: [hl+byte] 4 3 ? ((es:hl) + byte) ((es:hl) + byte) + 1 rp 1 1 ? rp rp ? 1 saddrp 2 2 ? (saddrp) (saddrp) ? 1 !addr16 3 2 ? (addr16) (addr16) ? 1 [hl+byte] 3 2 ? (hl+byte) (hl+byte) ? 1 es:!addr16 4 3 ? (es, addr16) (es, addr16) ? 1 increment/ decrement decw es: [hl+byte] 4 3 ? ((es:hl) + byte) ((es:hl) + byte) ? 1 shr a, cnt 2 1 ? (cy a 0 , a m ? 1 a m , a 7 0) cnt shrw ax, cnt 2 1 ? (cy ax 0 , ax m ? 1 ax m , ax 15 0) cnt a, cnt 2 1 ? (cy a 7 , a m a m ? 1 , a 0 0) cnt b, cnt 2 1 ? (cy b 7 , b m b m ? 1 , b 0 0) cnt shl c, cnt 2 1 ? (cy c 7 , c m c m ? 1 , c 0 0) cnt ax, cnt 2 1 ? (cy ax 15 , ax m ax m ? 1 , ax 0 0) cnt shlw bc, cnt 2 1 ? (cy bc 15 , bc m bc m ? 1 , bc 0 0) cnt sar a, cnt 2 1 ? (cy a 0 , a m ? 1 a m , a 7 a 7 ) cnt shift sarw ax, cnt 2 1 ? (cy ax 0 , ax m ? 1 ax m , ax 15 ax 15 ) cnt notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. 3. cnt indicates the bit shift count. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 739 table 27-5. operation list (13/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy ror a, 1 2 1 ? (cy, a 7 a 0 , a m ? 1 a m ) 1 rol a, 1 2 1 ? (cy, a 0 a 7 , a m + 1 a m ) 1 rorc a, 1 2 1 ? (cy a 0 , a 7 cy, a m ? 1 a m ) 1 rolc a, 1 2 1 ? (cy a 7 , a 0 cy, a m + 1 a m ) 1 ax,1 2 1 ? (cy ax 15 , ax 0 cy, ax m + 1 ax m ) 1 rotate rolwc bc,1 2 1 ? (cy bc 15 , bc 0 cy, bc m + 1 bc m ) 1 cy, saddr.bit 3 1 ? cy (saddr).bit cy, sfr.bit 3 1 ? cy sfr.bit cy, a.bit 2 1 ? cy a.bit cy, psw.bit 3 1 ? cy psw.bit cy,[hl].bit 2 1 4 cy (hl).bit saddr.bit, cy 3 2 ? (saddr).bit cy sfr.bit, cy 3 2 ? sfr.bit cy a.bit, cy 2 1 ? a.bit cy psw.bit, cy 3 4 ? psw.bit cy [hl].bit, cy 2 2 ? (hl).bit cy cy, es:[hl].bit 3 2 5 cy (es, hl).bit mov1 es:[hl].bit, cy 3 3 ? (es, hl).bit cy cy, saddr.bit 3 1 ? cy cy (saddr).bit cy, sfr.bit 3 1 ? cy cy sfr.bit cy, a.bit 2 1 ? cy cy a.bit cy, psw.bit 3 1 ? cy cy psw.bit cy,[hl].bit 2 1 4 cy cy (hl).bit and1 cy, es:[hl].bit 3 2 5 cy cy (es, hl).bit cy, saddr.bit 3 1 ? cy cy (saddr).bit cy, sfr.bit 3 1 ? cy cy sfr.bit cy, a.bit 2 1 ? cy cy a.bit cy, psw.bit 3 1 ? cy cy psw.bit cy, [hl].bit 2 1 4 cy cy (hl).bit bit manipulate or1 cy, es:[hl].bit 3 2 5 cy cy (es, hl).bit notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 740 table 27-5. operation list (14/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy cy, saddr.bit 3 1 ? cy cy (saddr).bit cy, sfr.bit 3 1 ? cy cy sfr.bit cy, a.bit 2 1 ? cy cy a.bit cy, psw.bit 3 1 ? cy cy psw.bit cy, [hl].bit 2 1 4 cy cy (hl).bit xor1 cy, es:[hl].bit 3 2 5 cy cy (es, hl).bit saddr.bit 3 2 ? (saddr).bit 1 sfr.bit 3 2 ? sfr.bit 1 a.bit 2 1 ? a.bit 1 !addr16.bit 4 2 ? (addr16).bit 1 psw.bit 3 4 ? psw.bit 1 [hl].bit 2 2 ? (hl).bit 1 es:!addr16.bit 5 3 ? (es, addr16).bit 1 set1 es:[hl].bit 3 3 ? (es, hl).bit 1 saddr.bit 3 2 ? (saddr.bit) 0 sfr.bit 3 2 ? sfr.bit 0 a.bit 2 1 ? a.bit 0 !addr16.bit 4 2 ? (addr16).bit 0 psw.bit 3 4 ? psw.bit 0 [hl].bit 2 2 ? (hl).bit 0 es:!addr16.bit 5 3 ? (es, addr16).bit 0 clr1 es:[hl].bit 3 3 ? (es, hl).bit 0 set1 cy 2 1 ? cy 1 1 clr1 cy 2 1 ? cy 0 0 bit manipulate not1 cy 2 1 ? cy cy notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 741 table 27-5. operation list (15/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy rp 2 3 ? (sp ? 2) (pc + 2) s , (sp ? 3) (pc + 2) h , (sp ? 4) (pc + 2) l , pc cs, rp, sp sp ? 4 $!addr20 3 3 ? (sp ? 2) (pc + 3) s , (sp ? 3) (pc + 3) h , (sp ? 4) (pc + 3) l , pc pc + 3 + jdisp16, sp sp ? 4 !addr16 3 3 ? (sp ? 2) (pc + 3) s , (sp ? 3) (pc + 3) h , (sp ? 4) (pc + 3) l , pc 0000, addr16, sp sp ? 4 call !!addr20 4 3 ? (sp ? 2) (pc + 4) s , (sp ? 3) (pc + 4) h , (sp ? 4) (pc + 4) l , pc addr20, sp sp ? 4 callt [addr5] 2 5 ? (sp ? 2) (pc + 2) s , (sp ? 3) (pc + 2) h , (sp ? 4) (pc + 2) l , pc s 0000, pc h (0000, addr5 + 1), pc l (0000, addr5), sp sp ? 4 brk ? 2 5 ? (sp ? 1) psw, (sp ? 2) (pc + 2) s , (sp ? 3) (pc + 2) h , (sp ? 4) (pc + 2) l , pc s 0000, pc h (0007fh), pc l (0007eh), sp sp ? 4, ie 0 ret ? 1 6 ? pc l (sp), pc h (sp + 1), pc s (sp + 2), sp sp + 4 reti ? 2 6 ? pc l (sp), pc h (sp + 1), pc s (sp + 2), psw (sp + 3), sp sp + 4 r r r call/ return retb ? 2 6 ? pc l (sp), pc h (sp + 1), pc s (sp + 2), psw (sp + 3), sp sp + 4 r r r notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 742 table 27-5. operation list (16/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy psw 2 1 ? (sp ? 1) psw, (sp ? 2) 00h, sp sp ? 2 push rp 1 1 ? (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 2 3 ? psw (sp + 1), sp sp + 2 r r r pop rp 1 1 ? rp l (sp), rp h (sp + 1), sp sp + 2 sp, #word 4 1 ? sp word sp, ax 2 1 ? sp ax ax, sp 2 1 ? ax sp hl, sp 3 1 ? hl sp bc, sp 3 1 ? bc sp movw de, sp 3 1 ? de sp addw sp, #byte 2 1 ? sp sp + byte stack manipulate subw sp, #byte 2 1 ? sp sp ? byte ax 2 3 ? pc cs, ax $addr20 2 3 ? pc pc + 2 + jdisp8 $!addr20 3 3 ? pc pc + 3 + jdisp16 !addr16 3 3 ? pc 0000, addr16 unconditio nal branch br !!addr20 4 3 ? pc addr20 bc $addr20 2 2/4 note 3 ? pc pc + 2 + jdisp8 if cy = 1 bnc $addr20 2 2/4 note 3 ? pc pc + 2 + jdisp8 if cy = 0 bz $addr20 2 2/4 note 3 ? pc pc + 2 + jdisp8 if z = 1 bnz $addr20 2 2/4 note 3 ? pc pc + 2 + jdisp8 if z = 0 bh $addr20 3 2/4 note 3 ? pc pc+3+jdisp8 if (z cy)=0 bnh $addr20 3 2/4 note 3 ? pc pc+3+jdisp8 if (z cy)=1 saddr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if (saddr).bit = 1 sfr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr20 3 3/5 note 3 ? pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if psw.bit = 1 [hl].bit, $addr20 3 3/5 note 3 6/8 pc pc + 3 + jdisp8 if (hl).bit = 1 conditional branch bt es:[hl].bit, $addr20 4 4/6 note 3 7/9 pc pc + 4 + jdisp8 if (es, hl).bit = 1 notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. this indicates the number of clocks ?when condition is not met/when condition is met?. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. chapter 27 instruction set preliminary user?s manual u19291ej1v0ud 743 table 27-5. operation list (17/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy saddr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if (saddr).bit = 0 sfr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr20 3 3/5 note 3 ? pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if psw.bit = 0 [hl].bit, $addr20 3 3/5 note 3 6/8 pc pc + 3 + jdisp8 if (hl).bit = 0 bf es:[hl].bit, $addr20 4 4/6 note 3 7/9 pc pc + 4 + jdisp8 if (es, hl).bit = 0 saddr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if (saddr).bit = 1 then reset (saddr).bit sfr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr20 3 3/5 note 3 ? pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit [hl].bit, $addr20 3 3/5 note 3 ? pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit condition al branch btclr es:[hl].bit, $addr20 4 4/6 note 3 ? pc pc + 4 + jdisp8 if (es, hl).bit = 1 then reset (es, hl).bit skc ? 2 1 ? next instruction skip if cy = 1 sknc ? 2 1 ? next instruction skip if cy = 0 skz ? 2 1 ? next instruction skip if z = 1 sknz ? 2 1 ? next instruction skip if z = 0 skh ? 2 1 ? next instruction skip if (z cy) = 0 conditional skip sknh ? 2 1 ? next instruction skip if (z cy) = 1 sel rbn 2 1 ? rbs[1:0] n nop ? 1 1 ? no operation ei ? 3 4 ? ie 1(enable interrupt) di ? 3 4 ? ie 0(disable interrupt) halt ? 2 3 ? set halt mode cpu control stop ? 2 3 ? set stop mode notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. this indicates the number of clocks ?when condition is not met/when condition is met?. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. 3. n indicates the number of register banks (n = 0 to 3) preliminary user?s manual u19291ej1v0ud 744 chapter 28 electrical specifications (target) cautions 1. these specifications of the 78k0r/kx3-l are target valu es, which may change after device evaluation. 2. the 78k0r/kx3-l has an on-chip debug func tion, which is provid ed for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the gu aranteed number of rewritable ti mes of the flash memory may be exceeded when this function is used, and produc t reliability therefore cannot be guaranteed. nec electronics is not liable for problems occurri ng when the on-chip debug function is used. 3. the pins mounted are as follows according to product. (1) port functions 78k0r/kc3-l 78k0r/kd3-l 78k0r/ke3-l port 44-pin 48-pin 52-pin 64-pin port 0 ? ? p00, p01 port 1 p10 to p13 p10 to p17 port 2 p20 to p27 port 3 p30 to p32 p30 to p33 port 4 p40, p41 p40 to p43 port 5 p50 to p52 p50 to p53 port 6 ? p60, p61 port 7 p70 to p75 p70 to p77 port 8 p80 to p83 port 12 p120 to p124 port 14 ? p140 p140, p141 port 15 p150, p151 p150 to p152 p150 to p153 (2) non-port functions (1/2) 78k0r/kc3-l 78k0r/kd3-l 78k0r/ke3-l function name 44-pin 48-pin 52-pin 64-pin power supply, ground v dd , av ref , v ss , av ss v dd , ev dd , av ref , v ss , ev ss , av ss regulator regc reset reset clock oscillation x1, x2, xt1, xt2, exclk writing to flash memory flmd0 interrupt intp0-intp7 timer slti, slto, ti02 to ti07, to02-to07 slti, slto, ti00, ti02 to ti07, to00, to02 to to07 real time counter rtcdiv, rtccl, rtc1hz comparator cmp0m, cmp0p, cmp1m, cmp1p programmable gain amplifier pgai chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 745 (2) non-port functions (2/2) 78k0r/kc3-l 78k0r/kd3-l 78k0r/ke3-l function name 44-pin 48-pin 52-pin 64-pin uart0 rxd0, txd0 uart1 rxd1, txd1 csi00 sck00, si00, so00 csi01 sck01, si01, so01 csi10 sck10, si10, so10 iic10 scl10, sda10 serial interface iica ? scl0, sda0 a/d converter ani0 to ani9 ani0 to ani10 ani0 to ani11 clock output/buzzer output ? pclbuz0 pclbuz0, pclbuz1 key interrupt kr0 to kr5 kr0 to kr7 low-voltage detector (lvi) exlvi on-chip debug function tool0, tool1 chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 746 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. absolute maximum ratings (t a = 25 c) (1/2) parameter symbols conditions ratings unit v dd ? 0.5 to +6.5 v ev dd ? 0.5 to +6.5 v v ss ? 0.5 to +0.3 v ev ss ? 0.5 to +0.3 v av ref ? 0.5 to v dd + 0.3 note 1 v supply voltage av ss ? 0.5 to +0.3 v regc pin input voltage v iregc regc ? 0.3 to 3.6 and ? 0.3 to v dd + 0.3 note 2 v v i1 p00, p01, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120 to p124, p141, exclk, reset, flmd0 ? 0.3 to ev dd + 0.3 and ? 0.3 to v dd + 0.3 note 1 v v i2 p60, p61 (n-ch open-drain) ? 0.3 to +6.5 v input voltage v i3 p20 to p27, p80 to p83, p150 to p153 ? 0.3 to av ref + 0.3 and ? 0.3 to v dd + 0.3 note 1 v v o1 p00, p01, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p60, p61, p70 to p77, p120, p140, p141 ? 0.3 to ev dd + 0.3 note 1 v output voltage v o2 p20 to p27, p80 to p83, p150 to p153 ? 0.3 to av ref + 0.3 v analog input voltage v an ani0 to ani11, pgai, cmp0m, cmp0p, cmp1m, cmp1p ? 0.3 to av ref + 0.3 note 1 and ? 0.3 to v dd + 0.3 note 1 v notes 1. must be 6.5 v or lower. 2. connect the regc pin to vss via a capacitor (0.47 to 1 f: target). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical dama ge, and therefore the product mu st be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of port pins. chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 747 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. absolute maximum ratings (t a = 25 c) (2/2) parameter symbols conditions ratings unit per pin p00, p01, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120, p140, p141 ? 10 ma p00, p01, p40 to p43, p120, p140, p141 ? 25 ma i oh1 total of all pins ? 80 ma p10 to p17, p30 to p33, p50 to p53, p70 to p77 ? 55 ma per pin ? 0.5 ma output current, high i oh2 total of all pins p20 to p27, p80 to p83, p150 to p153 ? 2 ma per pin p00, p01, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p60, p61, p70 to p77, p120, p140, p141 30 ma p00, p01, p40 to p43, p120, p140, p141 60 ma i ol1 total of all pins 200 ma p10 to p17, p30 to p33, p50 to p53, p60, p61, p70 to p77 140 ma per pin 1 ma output current, low i ol2 total of all pins p20 to p27, p80 to p83, p150 to p153 5 ma in normal operation mode operating ambient temperature t a in flash memory programming mode ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical dama ge, and therefore the product mu st be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of port pins. chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 748 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. x1 oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 2.7 v v dd 5.5 v 2.0 20.0 ceramic resonator c1 x2 x1 c2 v ss x1 clock oscillation frequency (f x ) note 1.8 v v dd < 2.7 v 2.0 5.0 mhz 2.7 v v dd 5.5 v 2.0 20.0 crystal resonator c1 x2 x1 c2 v ss x1 clock oscillation frequency (f x ) note 1.8 v v dd < 2.7 v 2.0 5.0 mhz note indicates only oscillator characteri stics. refer to ac characterist ics for instruction execution time. cautions 1. when using the x1 osc illator, wire as follows in the area encl osed by the bro ken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. since the cpu is started by the internal hi gh-speed oscillation clo ck after a reset release, check the x1 clock oscillation stab ilization time using the oscilla tion stabilization time counter status register (ostc) by the user. determine the oscillation stabilization time of the ostc register and oscillation stabilizat ion time select register (ost s) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. remark for the resonator selection and oscillator constan t, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 749 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. internal oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) oscillators parameters conditions min. typ. max. unit f ih1m 1 mhz 2.7 v v dd 5.5 v 8 mhz f ih8m 1.8 v v dd < 2.7 v 8 mhz internal high- speed oscillation clock frequency note f ih20m 2.7 v v dd 5.5 v 20 mhz internal low-speed oscillation clock frequency f il 30 khz note this only indicates the oscillator characteristics. refe r to ac characteristics for instruction execution time. xt1 oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit items conditions min. typ. max. unit crystal resonator xt1 xt2 c4 c3 rd v ss xt1 clock oscillation frequency (f xt ) note 32 32.768 35 khz note indicates only oscillator characteri stics. refer to ac characterist ics for instruction execution time. cautions 1. when using the xt1 oscillator, wire as follo ws in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. the xt1 oscillator is desi gned as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noi se than the x1 oscillato r. particular care is therefore required with the wiring meth od when the xt1 clock is used. remark for the resonator selection and oscillator constan t, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 750 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. recommended oscillator circuit constants xt1 oscillation: crystal resonator (t a = ? 40 to +85 c) oscillation voltage range recommended circuit constants manufacturer part number smd/ lead frequency (mhz) load capacitance cl (pf) xt1 oscllator oscillation mode note c1 (pf) c2 (pf) min. (v) max. (v) low power consumption oscillation 7 7 sp-t2a smd 4.4 ultra-low power consumption oscillation 7 7 low power consumption oscillation 5 5 vt-200 lead 6.0 ultra-low power consumption oscillation 5 5 low power consumption oscillation 4 3 seiko instruments inc. ssp-t7 small smd 32.768 3.7 ultra-low power consumption oscillation 4 3 1.8 5.5 note set the xt1 oscillation mode by using bits amphs1 and amphs0 of clock operation mode control register (cmc). caution the oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. if it is necessary to optimize the oscillator characteristics in the actual application, appl y to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and oscillati on frequency only indicate the oscillator characteristic. use the 78k0r/kx3-l so that the in ternal operation conditions are within the specifications of the dc and ac characteristics. chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 751 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. dc characteristics (1/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v ? 3.0 ma 2.7 v v dd < 4.0 v ? 1.0 ma per pin for p00, p01, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120, p140, p141 1.8 v v dd < 2.7 v ? 1.0 ma 4.0 v v dd 5.5 v ? 20.0 ma 2.7 v v dd < 4.0 v ? 10.0 ma total of p00, p01, p40 to p43, p120, p140, p141 (when duty = 70% note 2 ) 1.8 v v dd < 2.7 v ? 5.0 ma 4.0 v v dd 5.5 v ? 30.0 ma 2.7 v v dd < 4.0 v ? 19.0 ma total of p10 to p17, p30 to p33, p50 to p53, p70 to p77 (when duty = 70% note 2 ) 1.8 v v dd < 2.7 v ? 10.0 ma 4.0 v v dd 5.5 v ? 50.0 ma 2.7 v v dd < 4.0 v ? 29.0 ma i oh1 total of all pins (when duty = 60% note 2 ) 1.8 v v dd < 2.7 v ? 15.0 ma output current, high note 1 i oh2 per pin for p20 to p27, p80 to p83, p150 to p153 av ref v dd ? 0.1 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from the ev dd pin to an output pin. 2. specification under conditions where the duty factor is 60% or 70%. the output current value that has changed the duty ratio c an be calculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 752 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. dc characteristics (2/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 8.5 ma 2.7 v v dd < 4.0 v 1.0 ma per pin for p00, p01, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120, p140, p141 1.8 v v dd < 2.7 v 0.5 ma 4.0 v v dd 5.5 v 15.0 ma 2.7 v v dd < 4.0 v 3.0 ma per pin for p60, p61 1.8 v v dd < 2.7 v 2.0 ma 4.0 v v dd 5.5 v 20.0 ma 2.7 v v dd < 4.0 v 15.0 ma total of p00, p01, p40 to p43, p120, p140, p141 (when duty = 70% note 2 ) 1.8 v v dd < 2.7 v 9.0 ma 4.0 v v dd 5.5 v 45.0 ma 2.7 v v dd < 4.0 v 35.0 ma total of p10 to p17, p30 to p33, p50 to p53, p60, p61, p70 to p77 (when duty = 70% note 2 ) 1.8 v v dd < 2.7 v 20.0 ma 4.0 v v dd 5.5 v 65.0 ma 2.7 v v dd < 4.0 v 40.0 ma i ol1 total of all pins (when duty = 60% note 2 ) 1.8 v v dd < 2.7 v 29.0 ma output current, low note 1 i ol2 per pin for p20 to p27, p80 to p83, p150 to p153 av ref v dd 0.4 ma notes 1 . value of current at which the device operation is guaranteed even if the cu rrent flows from an output pin to the ev ss , v ss , and av ss pins. 2. specification under conditions where the duty factor is 60% or 70%. the output current value that has changed the duty ratio c an be calculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i ol 0.7)/(n 0.01) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 753 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. dc characteristics (3/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit v ih1 p01, p30, p33, p42, p43, p53, p123, p124, p141 0.7v dd v dd v v ih2 p00, p10 to p17, p31, p32, p40, p41, p50 to p52, p70 to p77, p120 to p122, exclk, reset normal input buffer 0.8v dd v dd v ttl input buffer 4.0 v v dd 5.5 v 2.2 v dd v ttl input buffer 2.7 v v dd < 4.0 v 2.0 v dd v v ih3 p31, p32, p71, p72, p74, p75 ttl input buffer 1.8 v v dd < 2.7 v 1.6 v dd v 2.7 v av ref v dd v ih4 p20 to p27, p81, p83, p150 to p153 av ref = v dd < 2.7 v 0.7av ref av ref v v ih5 p80, p82 av ref = v dd 0.8av ref av ref v v ih6 p60, p61 0.7v dd 6.0 v input voltage, high v ih7 flmd0 0.9v dd note v dd v note must be 0.9v dd or higher when used in the flash memory programming mode. caution the maximum value of v ih of pins p30 to p32, p70, p72, p73, and p75 is v dd , even in the n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of port pins. chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 754 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. dc characteristics (4/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit v il1 p01, p30, p33, p42, p43, p53, p123, p124, p141 0 0.3v dd v v il2 p00, p10 to p17, p31, p32, p40, p41, p50 to p52, p70 to p77, p120 to p122, exclk, reset normal input buffer 0 0.2v dd v ttl input buffer 4.0 v v dd 5.5 v 0 0.8 v ttl input buffer 2.7 v v dd < 4.0 v 0 0.5 v v il3 p31, p32, p71, p72, p74, p75 ttl input buffer 1.8 v v dd < 2.7 v 0 0.2 v 2.7 v av ref v dd v il4 p20 to p27, p81, p83, p150 to p153 av ref = v dd < 2.7 v 0 0.3av ref v v il5 p80, p82 av ref = v dd 0 0.2av ref v v il6 p60, p61 0 0.3v dd v input voltage, low v il7 flmd0 note 0 0.1v dd v note when disabling writing of the flash memory, c onnect the flmd0 pin processing directly to v ss , and maintain a voltage less than 0.1v dd . remark unless specified otherwise, the characte ristics of alternate-function pins ar e the same as those of port pins. chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 755 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. dc characteristics (5/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, i oh1 = ? 3.0 ma v dd ? 0.7 v v oh1 p00, p01, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120, p140, p141 1.8 v v dd 5.5 v, i oh1 = ? 1.0 ma v dd ? 0.5 v output voltage, high v oh2 p20 to p27, p80 to p83, p150 to p153 av ref v dd , i oh2 = ? 0.1 ma av ref ? 0.5 v 4.0 v v dd 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v v dd 5.5 v, i ol1 = 1.0 ma 0.5 v v ol1 p00, p01, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120, p140, p141 1.8 v v dd 5.5 v, i ol1 = 0.5 ma 0.4 v v ol2 p20 to p27, p80 to p83, p150 to p153 av ref = v dd , i ol2 = 0.4 ma 0.4 v 4.0 v v dd 5.5 v, i ol1 = 15.0 ma 2.0 v 4.0 v v dd 5.5 v, i ol1 = 5.0 ma 0.4 v 2.7 v v dd 5.5 v, i ol1 = 3.0 ma 0.4 v output voltage, low v ol3 p60, p61 1.8 v v dd 5.5 v, i ol1 = 2.0 ma 0.4 v caution p30 to p32, p70, p72, p73, and p75 do not output hi gh level in n-ch open-drain mode. remark unless specified otherwise, the characte ristics of alternate-function pins ar e the same as those of port pins. chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 756 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. dc characteristics (6/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit i lih1 p00, p01, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p60, p61, p70 to p77, p120, p141, flmd0, reset v i = v dd 1 a v i = av ref , 2.7 v av ref v dd i lih2 p20 to p27, p80 to p83, p150 to p153 v i = av ref , av ref = v dd < 2.7 v 1 a in input port 1 a input leakage current, high i lih3 p121 to p124 (x1, x2, xt1, xt2) v i = v dd in resonator connection 10 a i lil1 p00, p01, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p60, p61, p70 to p77, p120, p141, flmd0, reset v i = v ss ? 1 a v i = v ss , 2.7 v av ref v dd i lil2 p20 to p27, p80 to p83, p150 to p153 v i = v ss , av ref = v dd < 2.7 v ? 1 a in input port ? 1 a input leakage current, low i lil3 p121 to p124 (x1, x2, xt1, xt2) v i = v ss in resonator connection ? 10 a remark unless specified otherwise, the characte ristics of alternate-function pins ar e the same as those of port pins. chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 757 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. dc characteristics (7/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit on-chip pull-up resistance r u p00, p01, p10 to p17, p30 to p33, p40 to p43, p50 to p53, p70 to p77, p120, p141 v i = v ss , in input port 10 20 100 k flmd0 pin external pull-down resistance note r flmd0 when enabling the self-programming mode setting with software 100 k note it is recommended to leave the flmd0 pin open. if the pin is required to be pulled down externally, set r flmd0 to 100 k or more. 78k0r/kx3-l flmd0 pin r flmd0 remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of port pins. chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 758 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. dc characteristics (8/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit square wave input 6.5 t.b.d ma f mx = 20 mhz note 2 , v dd = 5.0 v resonator connection 6.8 t.b.d ma square wave input 6.5 t.b.d ma f mx = 20 mhz note 2 , v dd = 3.0 v resonator connection 6.8 t.b.d ma square wave input 3.5 t.b.d ma f mx = 10 mhz notes 2, 3 , v dd = 5.0 v resonator connection 3.6 t.b.d ma square wave input 3.5 t.b.d ma f mx = 10 mhz notes 2, 3 , v dd = 3.0 v resonator connection 3.6 t.b.d ma square wave input 1.9 t.b.d ma f mx = 5 mhz notes 2, 3 , v dd = 3.0 v resonator connection 2.0 t.b.d ma square wave input 1.5 t.b.d ma f mx = 5 mhz notes 2, 3 , v dd = 2.0 v resonator connection 1.5 t.b.d ma v dd = 5.0 v 6.8 t.b.d ma f ih20 = 20 mhz note 4 v dd = 3.0 v 6.8 t.b.d ma v dd = 5.0 v 2.8 t.b.d ma f ih = 8 mhz note 4 v dd = 3.0 v 2.8 t.b.d ma f ih = 1 mhz note 4 v dd = 3.0 v 200 t.b.d a v dd = 5.0 v 5.0 t.b.d a v dd = 3.0 v 5.0 t.b.d a f sub = 32.768 khz note 5 , t a = ? 40 to +70 c v dd = 2.0 v 5.0 t.b.d a v dd = 5.0 v 5.0 t.b.d a v dd = 3.0 v 5.0 t.b.d a supply current i dd1 note 1 operating mode f sub = 32.768 khz note 5 , t a = ? 40 to +85 c v dd = 2.0 v 5.0 t.b.d a notes 1. total current flowing into v dd , ev dd , and av ref , including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, programmable gain amplifier, comparator, lvi circuit, i/o port, and on-chip pull-up/pull-down resistors. 2. when internal high-speed oscillation, 20 mhz intern al high-speed oscillation, and subsystem clock are stopped. 3. when amph (bit 0 of clock operat ion mode control register (cmc)) = 0, flpc and fsel (bits 1 and 0 of operation speed mode control r egister (osmc)) = 0 and 0. 4. when high-speed system clock and subsystem clock are stopped. 5. when internal high-speed oscillation, 20 mhz internal high-speed oscillation, and high-speed system clock are stopped. when watchdog timer is stopped. remarks 1. f mx : high-speed system clock frequency (x1 clock oscill ation frequency or exte rnal main system clock frequency) 2. f ih20 : 20 mhz internal high-speed oscillation clock frequency 3. f ih : internal high-speed oscillation clock frequency 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 759 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. dc characteristics (9/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit square wave input 1.1 t.b.d ma f mx = 20 mhz note 2 , v dd = 5.0 v resonator connection 1.4 t.b.d ma square wave input 1.1 t.b.d ma f mx = 20 mhz note 2 , v dd = 3.0 v resonator connection 1.4 t.b.d ma square wave input 0.65 t.b.d ma f mx = 10 mhz notes 2, 3 , v dd = 5.0 v resonator connection 0.75 t.b.d ma square wave input 0.65 t.b.d ma f mx = 10 mhz notes 2, 3 , v dd = 3.0 v resonator connection 0.75 t.b.d ma square wave input 0.39 t.b.d ma f mx = 5 mhz notes 2, 3 , v dd = 3.0 v resonator connection 0.44 t.b.d ma square wave input 0.3 t.b.d ma f mx = 5 mhz notes 2, 3 , v dd = 2.0 v resonator connection 0.35 t.b.d ma v dd = 5.0 v 1.4 t.b.d ma f ih20 = 20 mhz note 4 v dd = 3.0 v 1.4 t.b.d ma v dd = 5.0 v 0.45 t.b.d ma f ih = 8 mhz note 4 v dd = 3.0 v 0.45 t.b.d ma supply current i dd2 note 1 halt mode f ih = 1 mhz note 4 v dd = 5.0 v 65 t.b.d a notes 1. total current flowing into v dd , ev dd , and av ref , including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . the maximum value includes the peripheral operation current. however, not including the current flowing into the a/ d converter, programmable ga in amplifier, comparator, lvi circuit, i/o port, and on-chip pull-up/pull-down resistor s. during halt instru ction execution by flash memory. 2. when internal high-speed oscillation, 20 mhz intern al high-speed oscillation, and subsystem clock are stopped. 3. when amph (bit 0 of clock operat ion mode control register (cmc)) = 0, flpc and fsel (bits 1 and 0 of operation speed mode control r egister (osmc)) = 0 and 0. 4. when high-speed system clock and subsystem clock are stopped. remarks 1. f mx : high-speed system clock frequency (x1 clock oscill ation frequency or exte rnal main system clock frequency) 2. f ih20 : 20 mhz internal high-speed oscillation clock frequency 3. f ih : internal high-speed oscillation clock frequency chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 760 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. dc characteristics (10/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 1.0 t.b.d a v dd = 3.0 v 1.0 t.b.d a f sub = 32.768 khz note 2 , t a = ? 40 to +70 c v dd = 2.0 v 1.0 t.b.d a v dd = 5.0 v 1.0 t.b.d a v dd = 3.0 v 1.0 t.b.d a i dd2 note 1 halt mode f sub = 32.768 khz note 2 , t a = ? 40 to +85 c v dd = 2.0 v 1.0 t.b.d a t a = ? 40 to +70 c 0.33 t.b.d a supply current i dd3 note 3 stop mode t a = ? 40 to +85 c 0.33 t.b.d a notes 1. total current flowing into v dd , ev dd , and av ref , including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . the maximum value includes the peripheral operation current. however, not including the current flowing into the a/ d converter, programmable ga in amplifier, comparator, lvi circuit, i/o port, and on-chip pull-up/pull-down resistor s. during halt instruct ion execution in flash memory. 2. when internal high-speed oscillation, 20 mhz internal high-speed oscillation, and high-speed system clock are stopped. when watchdog timer is stopped . when real-time counter is operating. 3. total current flowing into v dd , ev dd , and av ref , including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . the maximum value includes the peripheral operation current and stop leakage current. however, not including the cu rrent flowing into the a/d converter, programmable gain amplifier, comparator, lvi circuit, i/o port, and on- chip pull-up/pull-down resistors. when subsystem clock is stopped. when watchdog timer is stopped. remark f sub : subsystem clock frequency (xt1 clock oscillation frequency) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 761 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. dc characteristics (11/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit v dd = 3.0 v 0.2 1.0 a rtc operating current i rtc notes 1, 2 f sub = 32.768 khz v dd = 2.0 v 0.2 1.0 a watchdog timer operating current i wdt notes 2, 3 f il = 30 khz 0.31 t.b.d a high speed mode 1 av ref = v dd = 5.0 v 1.72 t.b.d ma high speed mode 2 av ref = v dd = 3.0 v 0.72 t.b.d ma normal mode av ref = v dd = 5.0 v 0.86 t.b.d ma a/d converter operating current i adc note 4 during conversion at maximum speed voltage boost mode av ref = v dd = 3.0 v 0.37 t.b.d ma programmable gain amplifier operating current i amp note 5 t.b.d t.b.d a av ref = v dd = 5.0 v t.b.d t.b.d a per channel when the internal reference voltage is not used av ref = v dd = 3.0 v t.b.d t.b.d a av ref = v dd = 5.0 v t.b.d t.b.d a comparator operating current i cmp note 6 per channel when the internal reference voltage is used av ref = v dd = 3.0 v t.b.d t.b.d a lvi operating current i lvi note 7 9 18 a notes 1. current flowing only to the real-time counter (excludi ng the operating current of the xt1 oscillator). the typ. value of the current value of the 78k0r/kx3-l is the sum of the typ. values of either i dd1 or i dd2 , and i rtc , when the real-time counter operates in operation mode or halt mode. the i dd1 and i dd2 max. values also include the real-time counter operating curr ent. when the real-time counter operates during f clk = f sub /2, the typ. value of i dd2 includes the real-time counter operating current. 2. when internal high-speed oscillation, 20 mhz inter nal high-speed oscillation, and high-speed system clock are stopped. 3. current flowing only to the watchdog timer (including the operating current of the 30 khz internal oscillator). the current value of the 78k 0r/kx3-l is the sum of i dd1 , i dd2 or i dd3 and i wdt when f clk = f sub /2 when the watchdog timer operates in stop mode. 4. current flowing only to the a/d converter (av ref pin). the current value of the 78k0r/kx3-l is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 5. current flowing only to the programmable gain amplifier (av ref pin). the current value of the 78k0r/kx3-l is the sum of i dd1 or i dd2 and i amp when the programmable gain amplifie r operates in an operation mode or the halt mode. 6. current flowing only to the comparator (av ref pin). the current value of the 78k0r/kx3-l is the sum of i dd1 or i dd2 and i cmp when the comparator operates in an operation mode or the halt mode. 7. current flowing only to the lvi circuit. the cu rrent value of the 78k0r/kx3-l is the sum of i dd1 , i dd2 or i dd3 and i lvi when the lvi circuit operates in t he operating, halt or stop mode. remarks 1. f il : internal low-speed oscillation clock frequency 2. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 3. f clk : cpu/peripheral hardware clock frequency chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 762 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. ac characteristics (1) basic operation (1/6) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 2.7 v v dd 5.5 v 0.05 8 s normal current mode 1.8 v v dd < 2.7 v 0.2 8 s main system clock (f main ) operation low consumption current mode 1 8 s subsystem clock (f sub ) operation 57.2 61 62.5 s instruction cycle (minimum instruction execution time) t cy in the self programming mode normal current mode 2.7 v v dd 5.5 v 0.05 0.5 s 2.7 v v dd 5.5 v 2.0 20.0 mhz external main system clock frequency f ex 1.8 v v dd < 2.7 v 2.0 5.0 mhz 2.7 v v dd 5.5 v 24 ns external main system clock input high-level width, low-level width t exh , t exl 1.8 v v dd < 2.7 v 96 ns ti00, ti02 to ti07 input high-level width, low-level width t tih , t til 1/f mck +10 ns 2.7 v v dd 5.5 v 10 mhz to00, to02 to to07 output frequency f to 1.8 v v dd < 2.7 v 5 mhz 2.7 v v dd 5.5 v 10 mhz pclbuz0, pclbuz1 output frequency f pcl 1.8 v v dd < 2.7 v 5 mhz interrupt input high-level width, low-level width t inth , t intl 1 s key interrupt input low-level width t kr 250 ns reset low-level width t rsl 10 s remarks 1. f mck : operation clock frequency of timer array unit (operation clock to be set by the cks0n bit of the tm r0n register. n: channel number (n = 0 to 7)) 2. for details on the normal current mode and low c onsumption current mode according to the regulator output voltage, refer to chapter 22 regulator . chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 763 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (1) basic operation (2/6) minimum instruction execution time during main system clock operation (fsel = 0, rmc = 00h) 8.0 1.0 0.2 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 1.8 2.1 cycle time t cy [ s] supply voltage v dd [v] guaranteed range of main system clock operation (fsel = 0, rmc = 00h) the range enclosed in dotted lines applies when the internal high-speed oscillation clock (8 mhz) is selected. remark fsel: bit 0 of the operation sp eed mode control register (osmc) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 764 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (1) basic operation (3/6) minimum instruction execution time during main system clock operation (fsel = 1, rmc = 00h) 8.0 1.0 0.2 0.1 0.05 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 1.8 guaranteed range of main system clock operation (fsel = 1, rmc = 00h) the range enclosed in dotted lines applies when the internal high-speed oscillation clock (8 mhz) is selected. supply voltage v dd [v] cycle time t cy [ s] caution the following operations are prohibited when v dd is less than 2.25 v. ? operation rewriting fsel from 0 to 1 ? releasing stop mode during f ex operation and f ih operation, when fsel is set to 1 (this must not be performed even if the fre quency is divided. the stop mode may be released during f x operation.) ? operation to switch f clk from f sub to f main , while fsel = 1 (this must not be performed even if the frequency is divided.) remarks 1. fsel: bit 0 of the operation sp eed mode control register (osmc) 2. f x : x1 clock oscillation frequency f ih : internal high-speed oscillation clock frequency f ex : external main system clock frequency f main : main system clock frequency f sub : subsystem clock frequency f clk : cpu/peripheral hardware clock frequency chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 765 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (1) basic operation (4/6) minimum instruction execution time during main sy stem clock operation (fsel = 0, rmc = 5ah) 8.0 1.0 0.2 0.1 0.05 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 0.01 1.8 cycle time t cy [ s] supply voltage v dd [v] guaranteed range of main system clock operation (fsel = 0, rmc = 5ah) the range enclosed in dotted lines applies when the internal high-speed oscillation clock (8 mhz) is selected. remarks 1. fsel: bit 0 of the operation sp eed mode control register (osmc) 2. the entire voltage range is 1 mhz (max.) when rmc is set to 5ah. chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 766 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (1) basic operation (5/6) minimum instruction execution time duri ng self programming mode (rmc = 00h) 8.0 1.0 0.5 0.1 0.2 0.05 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 0.01 2.7 1.8 cycle time t cy [ s] supply voltage v dd [v] guaranteed range of self programming mode (rmc = 00h) the range enclosed in dotted lines applies when the internal high-speed oscillation clock (8 mhz) is selected. remarks 1. fsel: bit 0 of the operation sp eed mode control register (osmc) 2. the self programming function cannot be used wh en rmc is set to 5ah or the cpu operates with the subsystem clock. chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 767 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (1) basic operation (6/6) ac timing test points v ih v il test points v ih v il external main system clock timing exclk 0.8v dd (min.) 0.2v dd (max.) 1/f ex t exl t exh ti timing ti00, ti02 to ti07, slti t til t tih interrupt request input timing intp0 to intp7 t intl t inth key interrupt input timing kr0 to kr7 t kr reset input timing reset t rsl chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 768 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (1/17) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (a) during communication at same potential (uart mode) (dedicat ed baud rate ge nerator output) parameter symbol conditions min. typ. max. unit f mck /6 bps transfer rate f clk = 20 mhz, f mck = f clk 3.3 mbps uart mode connection diagram (duri ng communication at same potential) 78k0r/kx3-l user's device txdq rxdq rx tx uart mode bit width (dur ing communication at same potential) (reference) baud rate error tolerance high-/low-bit width 1/transfer rate txdq rxdq caution select the normal input buffer for rxdq and the normal output mode for txdq by using the pimg and pomg registers. remarks 1. q: uart number (q = 0, 1) , g: pim and pom number (g = 3, 7) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cks0n bit of the sm r0n register. n: channel number (n = 0 to 3)) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 769 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (2/17) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (b) during communication at same pot ential (csi mode) (master mode, sckp... internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 200 ns sckp cycle time t kcy1 2.7 v v dd < 4.0 v 400 ns 1.8 v v dd < 2.7 v 800 ns 4.0 v v dd 5.5 v t kcy1 /2 ? 20 ns 2.7 v v dd < 4.0 v t kcy1 /2 ? 35 ns sckp high-/low-level width t kh1 , t kl1 1.8 v v dd < 2.7 v t kcy1 /2 ? 80 ns 4.0 v v dd 5.5 v 70 ns 2.7 v v dd < 4.0 v 100 ns sip setup time (to sckp ) note 1 t sik1 1.8 v v dd < 2.7 v 190 ns sip hold time (from sckp ) note 2 t ksi1 30 ns delay time from sckp to sop output note 3 t kso1 c = 50 pf note 4 40 ns notes 1. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and c kp0n = 1. the sip setup time becomes ?to sckp ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 2. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1. the sip hold time becomes ?from sckp ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 3. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp 0n = 1. the delay time to sop output becomes ?from sckp ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for sip and the normal output mode for sop and sckp by using the pimg and pomg registers. remark p: csi number (p = 00, 01, 10), n: channel number (n = 0 to 2), g: pim and pom number (g = 3, 7) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 770 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (3/17) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (c) during communication at same potential (csi mode) (slave m ode, sckp... external clock input) parameter symbol conditions min. typ. max. unit 16 mhz < f mck 8/f mck ns sckp cycle time t kcy2 f mck 16 mhz 6/f mck ns sckp high-/low-level width t kh2 , t kl2 t kcy2 /2 ns sip setup time (to sckp ) note 1 t sik2 1/f mck +80 ns sip hold time (from sckp ) note 2 t ksi2 50 ns 4.0 v v dd 5.5 v 1/f mck +120 ns 2.7 v v dd < 4.0 v 1/f mck +120 ns delay time from sckp to sop output note 3 t kso2 c = 50 pf note 4 1.8 v v dd < 2.7 v 1/f mck +180 ns notes 1. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and c kp0n = 1. the sip setup time becomes ?to sckp ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 2. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1. the sip hold time becomes ?from sckp ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 3. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp 0n = 1. the delay time to sop output becomes ?from sckp ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for sip and sckp and the normal output mode for sop by using the pimg and pomg registers. remarks 1. p: csi number (p = 00, 01, 10), g: pim and pom number (g = 3, 7) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cks0n bit of the sm r0n register. n: channel number (n = 0 to 2)) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 771 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (4/17) csi mode connection diagram (duri ng communication at same potential) 78k0r/kx3-l user's device sckp sop sck si sip so csi mode serial transfer timing (during communication at same potential) (when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1.) sip input data output data sop t kcy1, 2 t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp csi mode serial transfer timing (during communication at same potential) (when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0.) sip input data output data sop t kcy1, 2 t kh1, 2 t kl1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp remarks 1. p: csi number (p = 00, 01, 10) 2. n: channel number (n = 0 to 2) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 772 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (5/17) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (d) during communication at sam e potential (simplified i 2 c mode) parameter symbol conditions min. max. unit scl10 clock frequency f scl 2.7 v v dd 5.5 v, c b = 100 pf, r b = 3 k 400 khz hold time when scl10 = ?l? t low 2.7 v v dd 5.5 v, c b = 100 pf, r b = 3 k 995 ns hold time when scl10 = ?h? t high 2.7 v v dd 5.5 v, c b = 100 pf, r b = 3 k 995 ns data setup time (reception) t su:dat 2.7 v v dd 5.5 v, c b = 100 pf, r b = 3 k 1/f mck +120 ns data hold time (transmission) t hd:dat 2.7 v v dd 5.5 v, c b = 100 pf, r b = 3 k 0 160 ns simplified i 2 c mode connection diagram (durin g communication at same potential) 78k0r/kx3-l user's device sda10 scl10 sda scl v dd r b simplified i 2 c mode serial transfer timing (dur ing communication at same potential) sda10 t low 1/f scl t high t hd:dat scl10 t su:dat caution select the normal input buffer and the n-ch open drain output (v dd tolerance) mode for sda10 and the normal output mode for scl10 by using the pim3 and pom3 registers. remarks 1. r b [ ]:communication line (sda10) pull-up resistance, c b [f]: communication line (scl10, sda10) load capacitance 2. f mck : serial array unit operation clock frequency (operation clock to be set by the c ks02 bit of the smr02 register.) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 773 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (6/17) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss =av ss = 0 v) (e) communication at different potential (2.5 v, 3 v) ( uart mode) (dedicated baud rate generator output) (1/2) parameter symbol conditions min. typ. max. unit f mck /6 bps 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v f clk = 20 mhz, f mck = f clk 3.3 mbps f mck /6 bps transfer rate reception 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v f clk = 20 mhz, f mck = f clk 3.3 mbps caution select the ttl input buffer for rxdq and the n-ch open drain output (v dd tolerance) mode for txdq by using the pimg an d pomg registers. remarks 1. q: uart number (q = 0, 1) , g: pim and pom number (g = 3, 7) 2. v b [v]: communication line voltage 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cks0n bit of the smr0n register. n: channel number (n = 0 to 3)) 4. v ih and v il below are observation points for the ac characteristics of the serial array unit when communicating at different potentials in uart mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 774 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (7/17) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (e) communication at different potential (2.5 v, 3 v) ( uart mode) (dedicated baud rate generator output) (2/2) parameter symbol conditions min. typ. max. unit note 1 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v f clk = 16.8 mhz, f mck = f clk , c b = 50 pf, r b = 1.4 k , v b = 2.7 v 2.8 note 2 mbps note 3 transfer rate transmission 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v f clk = 19.2 mhz, f mck = f clk , c b = 50 pf, r b = 2.7 k , v b = 2.3 v 1.2 note 4 mbps notes 1. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 4.0 v v dd = ev dd 5.5 v and 2.7 v v b 4.0 v 1 maximum transfer rate = 2.2 { ? c b r b ln (1 ? v b )} 3 [bps] 1 2.2 transfer rate 2 ? { ? c b r b ln (1 ? v b )} baud rate error (theoretical value) = 1 100 [%] ( transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference between the transmission and reception sides. 2. this value as an example is calculated when the cond itions described in the ?conditions? column are met. refer to note 1 above to calculate the maximum transfer rate under conditions of the customer. 3. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v v dd = ev dd 4.0 v and 2.3 v v b 2.7 v 1 maximum transfer rate = 2.0 { ? c b r b ln (1 ? v b )} 3 [bps] 1 2.0 transfer rate 2 ? { ? c b r b ln (1 ? v b )} baud rate error (theoretical value) = 1 100 [%] ( transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference between the transmission and reception sides. 4. this value as an example is calculated when the condit ions described in the ?conditions? column are met. refer to note 3 above to calculate the maximum transfer rate under conditions of the customer. caution select the ttl input buffer for rxdq and the n-ch open drain output (v dd tolerance) mode for txdq by using the pimg an d pomg registers. (remarks are given on the next page.) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 775 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (8/17) remarks 1. r b [ ]:communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage 2. q: uart number (q = 0, 1) , g: pim and pom number (g = 3, 7) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cks0n bit of the sm r0n register. n: channel number (n = 0 to 3)) 4. v ih and v il below are observation points for the ac c haracteristics of the serial array unit when communicating at different potentials in uart mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 776 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (9/17) uart mode connection diagram (communication at different potential) 78k0r/kx3-l user's device txdq rxdq rx tx v b r b uart mode bit width (communication at different potential) (reference) txdq rxdq baud rate error tolerance baud rate error tolerance low-bit width high-/low-bit width high-bit width 1/transfer rate 1/transfer rate caution select the ttl input buffer for rxdq and the n-ch open drain output (v dd tolerance) mode for txdq by using the pimg an d pomg registers. remarks 1. r b [ ]:communication line (txdq) pull-up resistance, v b [v]: communication line voltage 2. q: uart number (q = 0, 1) , g: pim and pom number (g = 3, 7) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 777 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (10/17) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (f) communication at different potential (2.5 v, 3 v) (csi mode) (master mode , sckp... internal clock output) (1/2) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k 500 ns sckp cycle time t kcy1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 1000 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k t kcy1 /2 ? 120 ns sckp high-level width t kh1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k t kcy1 /2 ? 275 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k t kcy1 /2 ? 20 ns sckp low-level width t kl1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k t kcy1 /2 ? 35 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k 195 ns sip setup time (to sckp ) note t sik1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 380 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k 30 ns sip hold time (from sckp ) note t ksi1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 30 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k 165 ns delay time from sckp to sop output note t kso1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 320 ns note when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1. caution select the ttl input buffer for sip and the n-ch open drain output (v dd tolerance) mode for sop and sckp by using the pimg and pomg registers. remarks 1. r b [ ]:communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sip, sop, sckp) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00, 01, 10), n: channel number (n = 0 to 2), g: pim and pom number (g = 3, 7) 3. v ih and v il below are observation points for the ac characteristics of the serial array unit when communicating at different potentials in csi mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 778 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (11/17) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (f) communication at different potential (2.5 v, 3 v) (csi mode) (master mode , sckp... internal clock output) (2/2) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k 70 ns sip setup time (to sckp ) note t sik1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 100 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k 30 ns sip hold time (from sckp ) note t ksi1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 30 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k 40 ns delay time from sckp to sop output note t kso1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 50 pf, r b = 2.7 k 40 ns note when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. csi mode connection diagram (communication at different potential) v b r b 78k0r/kx3-l user's device chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 779 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (12/17) csi mode serial transfer timing: master m ode (communication at different potential) (when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp csi mode serial transfer timing: master m ode (communication at different potential) (when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp caution select the ttl input buffer for sip and the n-ch open drain output (v dd tolerance) mode for sop and sckp by using the pimg and pomg registers. remark p: csi number (p = 00, 01, 10), n: channel number (n = 0 to 2), g: pim and pom number (g = 3, 7) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 780 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (13/17) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (g) communication at different potential (2.5 v, 3 v) (csi mode) (slave mode, sckp... external clock input) parameter symbol conditions min. typ. max. unit 16.6 mhz < f mck 12/f mck ns 12.5 mhz < f mck 16.6 mhz 10/f mck ns 8.3 mhz < f mck 12.5 mhz 8/f mck ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v f mck 8.3 mhz 6/f mck ns 17.5 mhz < f mck 18/f mck ns 15 mhz < f mck 17.5 mhz 16/f mck ns 12.5 mhz < f mck 15 mhz 14/f mck ns 10 mhz < f mck 12.5 mhz 12/f mck ns 7.5 mhz < f mck 10 mhz 10/f mck ns 5 mhz < f mck 7.5 mhz 8/f mck ns sckp cycle time t kcy2 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v f mck 5 mhz 6/f mck ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v f kcy2 /2 ? 20 ns sckp high-/low-level width t kh2 , t kl2 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v f kcy2 /2 ? 35 ns sip setup time (to sckp ) note 1 t sik2 1/f mck + 90 ns sip hold time (from sckp ) note 2 t ksi2 50 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 1.4 k 1/f mck + 245 ns delay time from sckp to sop output note 3 t kso2 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 1/f mck + 400 ns (notes, caution and remarks are given on the next page.) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 781 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (14/17) notes 1. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and c kp0n = 1. the sip setup time becomes ?to sckp ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 2. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1. the sip hold time becomes ?from sckp ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. 3. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp 0n = 1. the delay time to sop output becomes ?from sckp ? when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0. csi mode connection diagram (communication at different potential) 78k0r/kx3-l user's device chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 782 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (15/17) csi mode serial transfer timing: slave mode (communication at different potential) (when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1) sip input data output data sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp csi mode serial transfer timing: slave mode (communication at different potential) (when dap0n = 0 and ckp0n = 1, or dap0n = 1 and ckp0n = 0) sip input data output data sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp caution select the ttl input buffer for sip and sckp and the n-ch open drain output (v dd tolerance) mode for sop by using the pimg and pomg registers. remark p: csi number (p = 00, 01, 10), n: channel number (n = 0 to 2), g: pim and pom number (g = 3, 7) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 783 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (16/17) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (h) communication at different potential (2.5 v, 3 v) (simplified i 2 c mode) parameter symbol conditions min. max. unit 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 1.4 k 400 khz scl10 clock frequency f scl 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 400 khz 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 1.4 k 1065 ns hold time when scl10 = ?l? t low 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 1065 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 1.4 k 445 ns hold time when scl10 = ?h? t high 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 445 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 1.4 k 1/f mck + 190 ns data setup time (reception) t su:dat 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 1/f mck + 190 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 1.4 k 0 160 ns data hold time (transmission) t hd:dat 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 0 160 ns caution select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for sda10 and the n-ch open drain output (v dd tolerance) mode for scl10 by us ing the pim3 and pom3 registers. remarks 1. r b [ ]:communication line (sda10, scl10) pull-up resistance, c b [f]: communication line (sda10, scl10) load capacitance, v b [v]: communication line voltage 2. f mck : serial array unit operation clock frequency (operation clock to be set by the c ks02 bit of the smr02 register.) 3. v ih and v il below are observation points for the ac char acteristics of the serial array unit when communicating at different potentials in simplified i 2 c mode. 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd 4.0 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 784 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (2) serial interface: se rial array unit (17/17) simplified i 2 c mode connection diagram (communication at different potential) 78k0r/kx3-l user's device sda10 scl10 sda scl v b r b v b r b simplified i 2 c mode serial transfer timing (communication at different potential) sda10 t low t high t hd : dat scl10 t su : dat 1/f scl caution select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for sda10 and the n-ch open drain output (v dd tolerance) mode for scl10 by us ing the pim3 and pom3 registers. remark r b [ ]:communication line (sda10, scl10) pull-up resistance, v b [v]: communication line voltage chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 785 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (3) serial interface: iica (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (a) iica standard mode high-speed mode parameter symbol conditions min. max. min. max. unit scl0 clock frequency f scl 0 100 0 400 khz setup time of restart condition note 1 t su:sta 4.7 0.6 s hold time t hd:sta 4.0 0.6 s hold time when scl0 = ?l? t low 4.7 1.3 s hold time when scl0 = ?h? t high 4.0 0.6 s data setup time (reception) t su:dat 250 100 ns data hold time (transmission) note 2 t hd:dat 0 0 0.9 s setup time of stop condition t su:sto 4.0 0.6 s bus-free time t buf 4.7 1.3 s rise time of sda0 and scl0 signals t r 1000 2.0+0.1 c b 300 ns fall time of sda0 and scl0 signals t f 300 2.0+0.1 c b 300 ns load capacitance value of each communication line (scl0, sda0) c b 400 400 pf notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wa it state is inserted in the ack (acknowledge) timing. iica serial transfer timing t low t r t high t f t hd:sta t buf stop condition start condition restart condition stop condition t su:dat t su:sta t su:sto t hd:sta t hd:dat scl0 sda0 chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 786 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. (4) serial interface: on-chip debug (uart) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (a) on-chip debug (uart) parameter symbol conditions min. typ. max. unit f clk /2 12 f clk /6 bps transfer rate flash memory programming mode 3.33 mbps 2.7 v v dd 5.5 v 10 mhz tool1 output frequency f tool1 1.8 v v dd < 2.7 v 2.5 mhz chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 787 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. a/d converter characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 10 bit 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr overall error notes 1, 2 ainl 1.8 v av ref < 2.7 v 1.2 %fsr high speed mode 1 2.5 66.6 s 4.0 v av ref 5.5 v normal mode 6.1 66.6 s high speed mode 1 4.5 66.6 s 2.7 v av ref < 4.0 v normal mode 12.2 66.6 s conversion time t conv 1.8 v av ref < 2.7 v voltage boost mode 27 66.6 s 4.0 v av ref 5.5 v normal mode 0.4 %fsr zero-scale error notes 1, 2 ezs 2.7 v av ref < 4.0 v normal mode 0.6 %fsr 4.0 v av ref 5.5 v normal mode 0.4 %fsr full-scale error notes 1, 2 efs 2.7 v av ref < 4.0 v normal mode 0.6 %fsr 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb integral non-linearity error note 1 ile 1.8 v av ref < 2.7 v 6.5 lsb 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb differential non-linearity error note 1 dle 1.8 v av ref < 2.7 v 2.0 lsb analog input voltage v ain 1.8 v av ref 5.5 v av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 788 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. programmable gain amplifier characteristics (t a = ? 40 to +85 c, 2.7 v v dd 5.5 v, 2.7 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input offset voltage vio amp t.b.d mv 1 gain 0.1av ref 0.45av ref v input voltage range vi amp other than above 0.1av ref /gain 0.9av ref /gain v maximum output voltage vo amp 0.1av ref 0.9av ref v sr f rising edge t.b.d v/ s slew rate sr r falling edge t.b.d v/ s gain rg 1 to 12 times operation stabilization wait time t amp 3 s remark slew rate: the change with respect to the rise or fall of the output voltage v/ s: the change in voltage per 1 s operation stabilization wait time: time requir ed until a state is entered where the dc and ac specifications of the pr ogrammable gain amplifier are satisfied after the operation of the programmable gain amplifier has been enabled (oaen of oam register = 1) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 789 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. comparator characteristics (t a = ? 40 to +85 c, 2.7 v v dd 5.5 v, 2.7 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input offset voltage vio cmp t.b.d mv input voltage range vi cmp 0.1av ref 0.9av ref v internal reference voltage deviation v iref t.b.d % t cr input amplitude = 100 mv, at rising edge note 1 t.b.d ns response time t cf input amplitude = 100 mv, at falling edge note 2 t.b.d ns operation stabilization wait time t cmp 1 s reference voltage stabilization wait time t vr 1 s notes 1. characteristics of pulse response when cmp0p input or programmable gain amplifier output changes from the comparator reference voltage ? 100 mv to the comparator reference voltage +100 mv. 2. characteristics of pulse response when cmp0p input or programmable gain amplifier output changes from the comparator reference voltage +100 mv to the comparator reference voltage ? 100 mv. 0 v +100 mv -100 mv comparator ref. voltage 5 v output voltage v o input voltage v in t cr t cf remark operation stabilization wait time: time requir ed until a state is entered where the dc and ac specifications of the comparator ar e satisfied after the operation of the comparator has been enabled (cnen of cnctl register = 1) (n = 0, 1) reference voltage time required until the volt age level of the inte rnal reference voltage stabilization wait time: circuit reaches 99% of the ideal value after the internal reference voltage has been enabled (cnvre of cnrvm register = 1) (n = 0, 1) chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 790 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. poc circuit characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit v por power supply rise time 1.52 1.61 1.70 v detection voltage v pdr power supply fall time 1.5 1.59 1.68 v power supply voltage rise inclination t pth change inclination of v dd : 0 v v por 0.5 v/ms minimum pulse width t pw when the voltage drops 200 s detection delay time 200 s poc circuit timing supply voltage (v dd ) time detection voltage v por (min.) detection voltage v por (typ.) detection voltage v por (max.) detection voltage v pdr (min.) detection voltage v pdr (typ.) detection voltage v pdr (max.) t pth t pw supply voltage rise time (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit maximum time to rise to 1.8 v (v dd (min.)) note (v dd : 0 v 1.8 v) t pup1 lvi default start function stopped is set (lvioff (option byte) = 1), when reset input is not used 3.6 ms maximum time to rise to 1.8 v (v dd (min.)) note (releasing reset input v dd : 1.8 v) t pup2 lvi default start function stopped is set (lvioff (option byte) = 1), when reset input is used 1.88 ms note make sure to raise the power s upply in a shorter time than this. supply voltage rise time timing ? when reset pin input is not used ? when reset pin input is used (when external reset is released by the reset pin, after poc has been released) 1.8 v 0 v poc i nternal signal t pup1 supply voltage (v dd ) time 1.8 v t pup2 0 v poc i nternal signal reset pin internal reset signal supply voltage (v dd ) time chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 791 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. lvi circuit characteristics (t a = ? 40 to +85 c, v pdr v dd = ev dd 5.5 v, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v lvi0 4.12 4.22 4.32 v v lvi1 3.97 4.07 4.17 v v lvi2 3.82 3.92 4.02 v v lvi3 3.66 3.76 3.86 v v lvi4 3.51 3.61 3.71 v v lvi5 3.35 3.45 3.55 v v lvi6 3.20 3.30 3.40 v v lvi7 3.05 3.15 3.25 v v lvi8 2.89 2.99 3.09 v v lvi9 2.74 2.84 2.94 v v lvi10 2.58 2.68 2.78 v v lvi11 2.43 2.53 2.63 v v lvi12 2.28 2.38 2.48 v v lvi13 2.12 2.22 2.32 v v lvi14 1.97 2.07 2.17 v supply voltage level v lvi15 1.81 1.91 2.01 v external input pin note 1 v exlvi exlvi < v dd , 1.8 v v dd 5.5 v 1.11 1.21 1.31 v detection voltage power supply voltage on power application v puplvi when lvi default start function enabled is set 1.87 2.07 2.27 v minimum pulse width t lw 200 s detection delay time 200 s operation stabilization wait time note 2 t lwait 10 s notes 1. the exlvi/p120/intp0 pin is used. 2. time required from setting bit 7 (lvion) of the lo w-voltage detection register (lvim) to 1 to operation stabilization remark v lvi(n ? 1) > v lvin : n = 1 to 15 lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lw t lwait lvion 1 chapter 28 electrical specifications (target) preliminary user?s manual u19291ej1v0ud 792 caution the pins mounted de pend on the product. refer to caution 3 at the beginning of this chapter. data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.5 note 5.5 v note the value depends on the poc detecti on voltage. when the voltage drop s, the data is retained until a poc reset is effected, but data is not re tained when a poc reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode flash memory programming characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v dd supply current i dd typ. = 10 mhz, max. = 20 mhz 6 20 ma cpu/peripheral hardware clock frequency f clk 2.7 v v dd 5.5 v 2 20 mhz number of rewrites per chip c erwr retention: 15 years 1 erase + 1 write after erase = 1 rewrite note 100 times note when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. preliminary user?s manual u19291ej1v0ud 793 chapter 29 package drawings 29.1 78k0r/kc3-l (44-pin products) pd78f1000gb-gaf-ax, 78f1001gb-gaf-ax, 78f1002gb-gaf-ax, 78f1003gb-gaf-ax s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.80 0.20 0.10 1.00 1.00 l lp l1 0.50 0.60 0.15 1.00 0.20 p44gb-80-gaf 3 + 5 ? 3 note each lead centerline is located within 0.20 mm of its true position at maximum material condition. detail of lead end 44-pin plastic lqfp (10x10) 0.35 + 0.08 ? 0.04 b 11 22 44 12 23 34 33 1 chapter 29 package drawings preliminary user?s manual u19291ej1v0ud 794 29.2 78k0r/kc3-l (48-pin products) pd78f1001ga-haa-ax, 78f1002ga- haa-ax, 78f1003ga-haa-ax s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 7.00 0.20 7.00 0.20 9.00 0.20 9.00 0.20 1.20 max. 0.10 0.05 1.00 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 0.75 0.75 l lp l1 0.50 0.60 0.15 1.00 0.20 p48ga-50-haa 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.20 b 12 24 1 48 13 25 37 36 48-pin plastic tqfp (fine pitch) (7x7) + 0.07 ? 0.03 chapter 29 package drawings preliminary user?s manual u19291ej1v0ud 795 29.3 78k0r/kd3-l pd78f1004gb-gag-ax, 78f1005g b-gag-ax, 78f1006gb-gag-ax s y e s x b m l c lp hd he zd ze a1 a2 a d e a3 s 0.125 + 0.08 ? 0.04 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.65 0.13 0.10 1.10 1.10 l lp l1 0.50 0.60 0.15 1.00 0.20 p52gb-65-gag 3 + 5 ? 3 note each lead centerline is located within 0.13mm of its true position at maximum material condition. detail of lead end 52-pin plastic lqfp (10x10) 0.30 b 13 26 1 52 14 27 39 40 l1 + 0.075 ? 0.025 chapter 29 package drawings preliminary user?s manual u19291ej1v0ud 796 29.4 78k0r/ke3-l pd78f1007gk-gaj-ax, 78f1008g k-gaj-ax, 78f1009gk-gaj-ax l c lp hd he zd ze l1 a1 a2 a d e 0.125 + 0.75 ? 0.25 (unit:mm) item dimensions d e hd he a a1 a2 a3 12.00 0.20 12.00 0.20 14.00 0.20 14.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.65 0.13 0.10 1.125 1.125 l lp l1 0.50 0.60 0.15 1.00 0.20 p64gk-65-gaj 3 + 5 ? 3 note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end 64-pin plastic lqfp (12x12) 0.30 + 0.08 ? 0.04 b 16 32 1 64 17 33 49 48 s y e s x b m a3 s chapter 29 package drawings preliminary user?s manual u19291ej1v0ud 797 pd78f1007gb-gah-ax, 78f1008g b-gah-ax, 78f1009gb-gah-ax s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 p64gb-50-gah 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.20 b 16 32 1 64 17 33 49 48 64-pin plastic lqfp(fine pitch)(10x10) + 0.07 ? 0.03 chapter 29 package drawings preliminary user?s manual u19291ej1v0ud 798 pd78f1007ga-hab-ax, 78f1008ga- hab-ax, 78f1009ga-hab-ax s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s note each lead centerline is located within 0.07mm of its true position at maximum material condition. detail of lead end 16 32 1 64 17 33 49 48 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 7.00 0.20 7.00 0.20 9.00 0.20 9.00 0.20 1.20 max. 0.10 0.05 1.00 0.05 0.25 c e x y zd ze 0.40 0.07 0.08 0.50 0.50 l lp l1 0.50 0.60 0.15 1.00 0.20 p64ga-40-hab 3 + 5 ? 3 0.16 b 64-pin plastic tqfp (fine pitch) (7x7) + 0.07 ? 0.03 chapter 29 package drawings preliminary user?s manual u19291ej1v0ud 799 pd78f1007f1-an1-a, 78f1008f1- an1-a, 78f1009f1-an1-a 64-pin plastic fbga (5x5) p64f1-50-an1 item dimensions d e w a a1 a2 e b x y y1 zd ze 5.00 0.10 5.00 0.10 0.50 0.20 0.21 0.05 0.32 0.05 0.90 0.10 0.69 (unit:mm) 0.05 0.08 0.20 0.75 0.75 s y1 s a a1 1 hgfedcba 2 3 4 5 6 7 8 a2 s y s e x bab m s wb s wa ze zd index mark b a d e preliminary user?s manual u19291ej1v0ud 800 appendix a development tools the following development t ools are available for the development of systems that employ the 78k0r/kx3-l. figure a-1 shows the developm ent tool configuration. appendix a development tools preliminary user?s manual u19291ej1v0ud 801 figure a-1. development tool configuration (1/2) (1) when using the in-circu it emulator qb-78k0rix3 note 4 language processing software assembler package c compiler package device file notes 1, 4 debugging software integrated debugger note 3 system simulator note 4 host machine (pc or ews) qb-78k0rix3 notes 3, 4 emulation probe target system software package project manager software package control software (windows only) note 2 power supply unit note 3 usb interface cable note 3 78k0r/ie3 microcontroller flash memory programmer note 3 flash memory write adapter < flash memory write environment > conversion adapter on-board programming off-board programming target connector notes 1. download the device file for 78k0r/kx3-l (df781 009) from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). 2. the project manager pm+ is in cluded in the assembler package. the pm+ is only used for windows. 3. in-circuit emulator qb-78k0rix3 is supplied with integrated debugger id78k0r-qb, on-chip debug emulator with programming function qb-mini2, power supply unit, and usb interface cable. any other products are sold separately. 4. under development appendix a development tools preliminary user?s manual u19291ej1v0ud 802 figure a-1. developmen t tool configuration (2/2) (2) when using the on-chip debug emulat or with programming function qb-mini2 language processing software ? assembler package ? c compiler package ? device file notes 1, 4 debugging software ? integrated debugger note 1 ? system simulator note 4 host machine (pc or ews) usb interface cable note 3 target connector target system ? software package ? project manager software package control software (windows only) note 2 qb-mini2 notes 3, 4 connection cable (16-pin cable) note 3 notes 1. download the device file for 78k0r/kx3-l (df781 009) and the integrated debugger (id78k0r-qb) from the download site for development tools (http://www.necel.com/micro /ods/eng/index.html). 2. the project manager pm+ is in cluded in the assembler package. the pm+ is only used for windows. 3. on-chip debug emulator qb-mini2 is supplied with usb interface cable, connection cables (10-pin cable and 16-pin cable), and 78k0-ocd board. any other products are sold separately. in addition, download the software for operating the qb-mini 2 from the download site for minicube2 (http://www.necel.com/micro/en/developmen t/asia/minicube2/minicube2.html). 4. under development appendix a development tools preliminary user?s manual u19291ej1v0ud 803 a.1 software package sp78k0r 78k0r series software package development tools (software) common to t he 78k0r microcontrollers are combined in this package. a.2 language processing software ra78k0r assembler package this assembler converts programs written in mnemonics into object codes executable with a microcontroller. this assembler is also provided with functi ons capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with a device file (df781009). appendix a development tools preliminary user?s manual u19291ej1v0ud 804 a.3 flash memory programming tools a.3.1 when using flash memory program mer pg-fp5, fl-pr5, pg-fp4 and fl-pr4 pg-fp5, fl-pr5, pg-fp4, fl-pr4 flash memory programmer flash memory programmer dedicated to mi crocontrollers with on-chip flash memory. flash memory programming adapter note flash memory programming adapter us ed connected to the flash memory programmer for use. note under development remarks 1. the fl-pr4 and fl-pr5 are a product of naito densei machida mfg. co., ltd. 2. use the latest version of the flash memory programming adapter. a.3.2 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this is a flash memory programmer dedicat ed to microcontrollers with on-chip flash memory. it is available also as on-chip debug emulator which serves to debug hardware and software when developing applicati on systems using the 78k0r/kx3-l microcontrollers. when using this as flash memory programmer, it should be used in combination with a connection cable (16-pin cable) and a usb interface cable that is used to connect the host machine. remark download the software for operating the qb-mi ni2 from the download site for minicube2 (http://www.necel.com/micro/en/developmen t/asia/minicube2/minicube2.html). appendix a development tools preliminary user?s manual u19291ej1v0ud 805 a.4 debugging tools (hardware) a.4.1 when using in-circu it emulator qb-78k0rix3 qb-78k0rix3 notes 1, 2 in-circuit emulator this in-circuit emulator serves to debug har dware and software when developing application systems using the 78k0r/kx3-l microcontrollers. it supports to the integrated debugger (id78k0r-qb). this emulator should be used in combination with a power supply unit and emulation probe, and the usb is used to conn ect this emulator to the host machine. qb-144-ca-01 check pin adapter this check pin adapter is used in waveform monitoring using the oscilloscope, etc. qb-80-ep-01t emulation probe this emulation probe is flexible type and used to connect the in-circuit emulator and target system. qb-xxxx-ea-xxx notes 1, 2 exchange adapter this exchange adapter is used to perform pin conver sion from the in-circuit emulator to target connector. qb-xxxx-ys-xxxx notes 1, 2 space adapter this space adapter is used to adjust the height bet ween the target system and in-circuit emulator. qb-xxxx-yq-xxx notes 1, 2 yq connector this yq connector is used to connect the target connector and exchange adapter. qb-xxxx-hq-xxx notes 1, 2 mount adapter this mount adapter is used to mount the target device with socket. qb-xxxx-nq-xxx notes 1, 2 target connector this target connector is used to mount on the target system. notes 1. under development 2. the part numbers of the exchange adapter, space adapter, yq connector, mount adapter, and target connector and the packages of the ta rget device are described below. package exchange adapter space adapter yq connector mount adapter target connector 44-pin plastic lqfp (gb-gaf type) qb-44gb- ea-04t qb-44gb- ys-01t qb-44gb- yq-01t qb-44gb- hq-01t qb-44gb- nq-01t 78k0r/ kc3-l 48-pin plastic lqfp (ga-haa type) qb-48ga- ea-04t qb-48ga- ys-01t qb-48ga- yq-01t qb-48ga- hq-01t qb-48ga- nq-01t 78k0r/ kd3-l 52-pin plastic lqfp (gb-gag type) qb-52gb- ea-04t qb-52gb- ys-01t qb-52gb- yq-01t qb-52gb- hq-01t qb-52gb- nq-01t 64-pin plastic lqfp (gb-gah type) qb-64gb- ea-04t qb-64gb- ys-01t qb-64gb- yq-01t qb-64gb- hq-01t qb-64gb- nq-01t 64-pin plastic lqfp (gk-gaj type) qb-64gk- ea-04t qb-64gk- ys-01t qb-64gk- yq-01t qb-64gk- hq-01t qb-64gk- nq-01t 64-pin plastic tqfp (ga-hab type) qb-64ga- ea-01t qb-64ga- ys-01t qb-64ga- yq-01t qb-64ga- hq-01t qb-64ga- nq-01t 78k0r/ ke3-l 64-pin plastic fbga (f1-an1 type) qb-64fc- ea-01t none none none qb-64fc- nq-01t (remarks are listed on the next page or later.) appendix a development tools preliminary user?s manual u19291ej1v0ud 806 remarks 1. the qb-78k0rix3 is supplied with the integrated debugger id78k0r-qb, a usb interface cable, a power supply unit, the on-chip debug emulator qb-mini2, connection cables (10-pin and 16-pin cables), and the 78k0-ocd board. download the software for operating the qb-mini 2 from the download site for development tools (http://www.necel.com/micro/ods/eng/ind ex.html) when using the qb-mini2. 2. the packed contents differ depending on the part number, as follows. packed contents part number in-circuit emulator emulation probe exch ange adapter yq connector target connector qb-78k0rix3-zzz none qb-78k0rix3-t44gb qb-44gb-ea-04t qb-44gb-yq-01t qb-44gb-nq-01t qb-78k0rix3-t48ga qb-48ga-ea-04t qb-48ga-yq-01t qb-48ga-nq-01t qb-78k0rix3-t52gb qb-52gb-ea-04t qb-52gb-yq-01t qb-52gb-nq-01t qb-78k0rix3-t64gb qb-64gb-ea-04t qb-64gb-yq-01t qb-64gb-nq-01t qb-78k0rix3-t64gk qb-64gk-ea-04t qb-64gk-yq-01t qb-64gk-nq-01t qb-78k0rix3-t64ga qb-64ga-ea-01t qb-64ga-yq-01t qb-64ga-nq-01t qb-78k0rix3-t64f1 qb-78k0rix3 note qb-80-ep-01t qb-64fc-ea-01t none qb-64fc-nq-01t note under development a.4.2 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this on-chip debug emulator serves to debug hardware and software when developing application systems using the 78k0r/kx3-l microc ontrollers. it is available also as flash memory programmer dedicated to microcontro llers with on-chip flash memory. when using this as on-chip debug emulator, it shou ld be used in combination with a connection cable (16-pin cable) and a usb interface cable that is used to connect the host machine. remark download the software for operating the qb-mi ni2 from the download site for minicube2 (http://www.necel.com/micro/en/developmen t/asia/minicube2/minicube2.html). a.5 debugging tools (software) sm+ for 78k0r note system simulator sm+ for 78k0r is windows-based software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of sm+ for 78k0r allows the exec ution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development e fficiency and software quality. sm+ for 78k0r should be used in combination with the device file (df781009). id78k0r-qb integrated debugger this debugger supports the in-circuit emulat ors for the 78k0r microcontrollers. the id78k0r-qb is windows-based software. it has improved c-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory di splay with the trace result. it should be used in combination with the device file (df781009). note under development nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, japan tel: 044-435-5111 http://www.necel.com/ [america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554, u.s.a. tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ [asia & oceania] nec electronics (china) co., ltd 7th floor, quantum plaza, no. 27 zhichunlu haidian district, beijing 100083, p.r.china tel: 010-8235-1155 http://www.cn.necel.com/ shanghai branch room 2509-2510, bank of china tower, 200 yincheng road central, pudong new area, shanghai, p.r.china p.c:200120 tel:021-5888-5400 http://www.cn.necel.com/ shenzhen branch unit 01, 39/f, excellence times square building, no. 4068 yi tian road, futian district, shenzhen, p.r.china p.c:518048 tel:0755-8282-9800 http://www.cn.necel.com/ nec electronics hong kong ltd. unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: 2886-9318 http://www.hk.necel.com/ nec electronics taiwan ltd. 7f, no. 363 fu shing north road taipei, taiwan, r. o. c. tel: 02-8175-9600 http://www.tw.necel.com/ nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 tel: 6253-8311 http://www.sg.necel.com/ nec electronics korea ltd. 11f., samik lavied?or bldg., 720-2, yeoksam-dong, kangnam-ku, seoul, 135-080, korea tel: 02-558-3737 http://www.kr.necel.com/ for further information, please contact: g0706 [europe] nec electronics (europe) gmbh arcadiastrasse 10 40472 dsseldorf, germany tel: 0211-65030 http://www.eu.necel.com/ hanover office podbielskistrasse 166 b 30177 hannover tel: 0 511 33 40 2-0 munich office werner-eckert-strasse 9 81829 mnchen tel: 0 89 92 10 03-0 stuttgart office industriestrasse 3 70565 stuttgart tel: 0 711 99 01 0-0 united kingdom branch cygnus house, sunrise parkway linford wood, milton keynes mk14 6np, u.k. tel: 01908-691-133 succursale fran?aise 9, rue paul dautier, b.p. 52 78142 velizy-villacoublay cdex france tel: 01-3067-5800 sucursal en espa?a juan esplandiu, 15 28007 madrid, spain tel: 091-504-2787 tyskland filial t?by centrum entrance s (7th floor) 18322 t?by, sweden tel: 08 638 72 00 filiale italiana via fabio filzi, 25/a 20124 milano, italy tel: 02-667541 branch the netherlands steijgerweg 6 5616 hs eindhoven the netherlands tel: 040 265 40 10 |
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